Commit Graph

153 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
6d34476cd6 Propagate affinities for EBB arguments.
A priory, an EBB argument value only gets an affinity if it is used
directly by a non-ghost instruction. A use by a branch passing arguments
to an EBB doesn't count.

When an EBB argument value does have an affinity, the values passed by
all the predecessors must also have affinities. This can cause EBB
argument values to get affinities recursively.

- Add a second pass to the liveness computation for propagating EBB
  argument affinities, possibly recursively.
- Verify EBB argument affinities correctly: A value passed to a branch
  must have an affinity only if the corresponding EBB argument value in
  the destination has an affinity.
2017-06-29 10:30:26 -07:00
Jakob Stoklund Olesen
cd1503eced Make sure return values are assigned an affinity.
When an EBB argument value is used only as a return value, it still
needs to be given a register affinity. Otherwise it would appear as a
ghost value with no affinity.

Do the same to call arguments.
2017-06-29 09:24:05 -07:00
Jakob Stoklund Olesen
c4532b901e Don't coalesce incoming stack arguments.
A function parameter in an incoming_arg stack slot should not be
coalesced into any virtual registers. We don't want to force the whole
virtual register to spill to the incoming_arg slot.
2017-06-28 15:37:38 -07:00
Jakob Stoklund Olesen
2a600b3632 Assign stack slots to incoming function arguments.
Function arguments that don't fit in registers are passed on the stack.

Create "incoming_arg" stack slots representing the stack arguments, and
assign them to the value arguments during spilling.
2017-06-28 15:03:59 -07:00
Jakob Stoklund Olesen
ed3157f508 Add an offset to StackSlotData.
The offset is relative to the stack pointer in the calling function, so
it excludes the return address pushed by the call instruction itself on
Intel ISAs.

Change the ArgumentLoc::Stack offset to an i32, so it matches the stack
slot offsets.
2017-06-28 14:38:13 -07:00
Jakob Stoklund Olesen
1d20c92ffe Color EBB arguments.
When coloring registers for a branch instruction, also make sure that
the values passed as EBB arguments are in the registers expected by the
EBB.

The first time a branch to an EBB is processed, assign the EBB arguments
to the registers where the branch arguments already reside so no
regmoves are needed.
2017-06-27 16:35:38 -07:00
Jakob Stoklund Olesen
cf967642a3 Add a coalescing pass to the register allocator.
Coalescing means creating virtual registers and transforming the code
into conventional SSA form. This means that every value used as a branch
argument will belong to the same virtual register as the corresponding
EBB argument value.

Conventional SSA form makes it easy to avoid memory-memory copies when
spilling values, and the virtual registers can be used as hints when
picking registers too. This reduces the number of register moves needed
for EBB arguments.
2017-06-22 15:03:48 -07:00
Dan Gohman
e094389f12 Add a simple_gvn test that includes some basic control flow. 2017-06-22 14:34:21 -07:00
Jakob Stoklund Olesen
9e02b9818f Encode iconst.i32 for RISC-V.
For large constants with the low 12 bits clear, we already have the
"lui" encoding. Add "addi %x0" encodings for signed 12-bit constants.
2017-06-22 12:13:37 -07:00
Jakob Stoklund Olesen
342121aba0 Assign spill slots to spilled values.
As soon as a value is spilled, also assign it to a spill slot.

For now, create a new spill slot for each spilled value. In the future,
values will be sharing spill slots of they are phi-related.
2017-06-16 13:34:18 -07:00
Jakob Stoklund Olesen
91d919c11a Track stack slot kinds.
Add a StackSlotKind enumeration to help keep track of the different
kinds of stack slots supported:

- Incoming and outgoing function arguments on the stack.
- Spill slots and locals.

Change the text format syntax for declaring a stack slot to use a kind
keyword rather than just 'stack_slot'.
2017-06-16 11:01:22 -07:00
Jakob Stoklund Olesen
66bc0a9c8b Make register copies for incompatible operands.
An instruction may have fixed operand constraints that make it
impossibly to use a single register value to satisfy two at a time.

Detect when the same value is used for multiple fixed register operands
and insert copies during the spilling pass.
2017-06-15 13:12:13 -07:00
Jakob Stoklund Olesen
9eb0778f9b Add RISC-V encodings for call_indirect. 2017-06-14 16:14:16 -07:00
Jakob Stoklund Olesen
66af915eed Add RISC-V encodings for copy instructions. 2017-06-14 15:36:25 -07:00
Jakob Stoklund Olesen
f2f162f37e Spill values live across calls.
Calls clobber many registers, so spill everything that is live across a
call for now.

In the future, we may add support for callee-saved registers.
2017-06-14 08:55:01 -07:00
Jakob Stoklund Olesen
5a23f975fc Extract spill insertion into a reload::insert_spill function.
Make sure that spill instructions are generated in the same way
everywhere, including adding encoding and updating live ranges.
2017-06-13 15:46:11 -07:00
Jakob Stoklund Olesen
6381da948f Handle ABI arguments correctly in the reload pass.
Values passed as arguments to calls and return instructions may also be
reload candidates.
2017-06-13 15:13:36 -07:00
Jakob Stoklund Olesen
36f189810e Basic spilling implementation.
Add a spilling pass which lowers register pressure by assigning SSA
values to the stack. Important missing features:

- Resolve conflicts where an instruction uses the same value more than
  once in incompatible ways.
- Deal with EBB arguments.

Fix bugs in the reload pass exposed by the first test case:

- Create live ranges for temporary registers.
- Set encodings on created spill and fill instructions.
2017-06-13 13:58:20 -07:00
Aleksey Kuznetsov
8b484b1c77 Binary function names (#91)
* Function names should start with %

* Create FunctionName from string

* Implement displaying of FunctionName as %nnnn with fallback to #xxxx

* Run rustfmt and fix FunctionName::with_string in parser

* Implement FunctionName::new as a generic function

* Binary function names should start with #

* Implement NameRepr for function name

* Fix examples in docs to reflect that function names start with %

* Rebase and fix filecheck tests
2017-06-10 10:30:37 -07:00
Denis Merigoux
9b06f76057 LICM pass (#87)
* LICM pass

* Uses loop analysis to detect loop tree
* For each loop (starting with the inner ones), create a pre-header and move there loop-invariant instructions
* An instruction is loop invariant if it does not use as argument a value defined earlier in the loop
* File tests to check LICM's correctness
* Optimized pre-header creation
If the loop already has a natural pre-header, we use it instead of creating a new one.
The natural pre-header of a loop is the only predecessor of the header it doesn't dominate.
2017-06-07 11:27:22 -07:00
Dan Gohman
059845880c Fix more GVN issues (#83)
* Fix GVN skipping the instruction after a deleted instruction.

* Teach GVN to resolve aliases as it proceeds.

* Clean up an obsolete reference to extended_values.
2017-05-25 16:37:31 -07:00
Dan Gohman
dc809628f4 Start a very simple GVN pass (#79)
* Skeleton simple_gvn pass.
* Basic testing infrastructure for simple-gvn.
* Add can_load and can_store flags to instructions.
* Move the replace_values function into the DataFlowGraph.
* Make InstructionData derive from Hash, PartialEq, and Eq.
* Make EntityList's hash and eq functions panic.
* Change Ieee32 and Ieee64 to store u32 and u64, respectively.
2017-05-18 18:18:57 -07:00
Jakob Stoklund Olesen
9629867d0c Encodings for load/store instructions.
We don't support the full set of Intel addressing modes yet. So far we
have:

- Register indirect, no displacement.
- Register indirect, 8-bit signed displacement.
- Register indirect, 32-bit signed displacement.

The SIB addressing modes will need new Cretonne instruction formats to
represent.
2017-05-12 16:49:39 -07:00
Jakob Stoklund Olesen
c998df6274 Add subtract and logical instruction encodings to Intel-32.
Also add versions with 8-bit and 32-bit immediate operands.
2017-05-12 15:37:12 -07:00
Jakob Stoklund Olesen
663b50efcc Add fixed constraints for ABI arguments and return values.
We can start adding some real test cases for the move resolver now.
2017-05-11 12:02:02 -07:00
Jakob Stoklund Olesen
9f743cf3a5 Always create live ranges for dead EBB arguments.
The live value tracker expects them to be there.

We may eventually delete dead arguments from internal EBBs, but at least
the entry block needs to be able to handle dead function arguments.
2017-05-11 11:42:44 -07:00
Jakob Stoklund Olesen
cdb3a71dd1 Add encodings for Intel dynamic shift instructions.
These instructions have a fixed register constraint; the shift amount is
passed in CL.

Add meta language syntax so a fixed register can be specified as
"GPR.rcx".
2017-05-09 13:11:50 -07:00
Jakob Stoklund Olesen
5bdb61a5f1 Add the very basics of Intel 32-bit instruction encodings.
Tabulate the Intel opcode representations and implement an OP() function
which computes the encoding bits.

Implement the single-byte opcode with a reg-reg ModR/M byte.
2017-05-08 16:57:38 -07:00
Jakob Stoklund Olesen
8cd67f08a9 Add a regmove instruction.
This will be used to locally change the register locations of values in
order to satisfy instruction constraints.
2017-05-02 11:32:12 -07:00
Jakob Stoklund Olesen
4c8eb85f39 Color entry block arguments using the function signature.
The arguments to the entry block arrive in registers determined by the
ABI. This information is stored in the signature.

Use a separate function for coloring entry block arguments using the
signature information. We can't handle stack arguments yet.
2017-04-26 14:38:16 -07:00
Jakob Stoklund Olesen
bb8ae9a4fb Add a TargetIsa::allocatable_registers() method.
This gives the target ISA a chance to reserve registers like the stack
pointer or hard-wired 0 registers like %x0 on RISC-V.
2017-04-26 13:54:40 -07:00
Jakob Stoklund Olesen
305de3e73b Add an enable_e setting for the RV32E instruction set.
This limited RISC-V version only has registers %x0 - %x15.

Make sure the ABI lowering code doesn't use the banned registers for
arguments.
2017-04-26 13:50:52 -07:00
Eric Anholt
100666e300 Verify that the instruction encoding matches what the ISA would encode.
Fixes #69
2017-04-23 17:21:32 -07:00
Jakob Stoklund Olesen
9c23196049 Implement binary emission of RISC-V return instructions.
The return address is now always supplied in %x1, so the return address
predictor will recognize the jalr as a return and not some indirect
branch.
2017-04-19 16:26:04 -07:00
Jakob Stoklund Olesen
832247019b Remove the return_reg instruction.
RISC architectures that take a return address in a register can use a
special-purpose `link` return value to do so.
2017-04-19 16:08:16 -07:00
Jakob Stoklund Olesen
315c858b48 Append link and sret arguments in legalize_signature.
These special-purpose arguments and return values are only relevant for
the function being compiled, so add a `current` flag to
legalize_signature().

- Add the necessary argument values to the entry block to represent
  the special-purpose arguments.
- Propagate the link and sret arguments to return instructions if the
  legalized signature asks for it.
2017-04-19 15:55:12 -07:00
Jakob Stoklund Olesen
74595c6623 Fix broken test. 2017-04-17 15:45:55 -07:00
Jakob Stoklund Olesen
7e9bdcf059 Allow for special purpose function arguments and return values.
Enumerate a set of special purposes for function arguments that general
purpose code needs to know about. Some of these argument purposes will
only appear in the signature of the current function, representing
things the prologue and epilogues need to know about like the link
register and callee-saved registers.

Get rid of the 'inreg' argument flag. Arguments can be pre-assigned to a
specific register instead.
2017-04-17 15:06:30 -07:00
Jakob Stoklund Olesen
f9d3e65419 Don't create value aliases when legalizing ABI boundaries.
When converting from ABI types to original program types, the final
conversion instruction can place its result into the original value, so
it doesn't need to be changed to an alias.
2017-04-13 10:16:58 -07:00
Jakob Stoklund Olesen
3ae0fe6e2b Avoid creating aliases when expanding legalizer patterns.
Now that we can detach and reuse all values, there is no longer a need
to create a lot of alias values during pattern expansion. Instead, reuse
the values from the source pattern when emitting instructions in the
destination pattern.

If a destination instruction produces the exact same values as a source
instruction, simply leave the values attached and replace the
instruction it. Otherwise, detach the source values, reuse them in the
expansion, and remove the source instruction afterwards.
2017-04-13 09:30:21 -07:00
Jakob Stoklund Olesen
23ae70cacf Flatten the Value reference representation.
All values are now references into the value table, so drop the
distinction between direct and table values. Direct values don't exist
any more.

Also remove the parser support for the 'vxNN' syntax. Only 'vNN' values
can be parsed now.
2017-04-12 14:45:22 -07:00
Jakob Stoklund Olesen
b9808bedc4 Stop calling Value::new_direct.
We only ever create table values now.

Simplify legalizer::legalize_inst_results. Instead of calling
detach_secondary_results, just detach all the results and don't treat
the first result specially.
2017-04-12 14:32:13 -07:00
Jakob Stoklund Olesen
0be78f970c Make tests less sensitive to specific value numbers. 2017-04-12 14:32:13 -07:00
Jakob Stoklund Olesen
1c890f317d Add RISC-V call instruction encodings.
Calls are jal with a fixed %x1 link register.
2017-04-11 10:40:38 -07:00
Jakob Stoklund Olesen
9d9807688c Add load and store instructions.
Define a MemFlags class, currently holding a notrap and aligned flag.
2017-04-11 09:54:55 -07:00
Jakob Stoklund Olesen
b5237b6a4a Add heap_load, heap_store, and heap_addr instructions.
These are used when lowering WebAssembly sandbox code.
2017-04-10 15:04:33 -07:00
Jakob Stoklund Olesen
c52e3e0b3f Define stack_load, stack_store, and stack_addr instructions. 2017-04-10 13:56:57 -07:00
Jakob Stoklund Olesen
13b0046ed7 Syntax tweak: Omit comma after an initial enum immediate.
This affects the comparison instructions which now read "icmp ult a, b".
This mimics LLVM's style and makes it simpler to add instruction flags
in the future, such as "load v1" -> "load aligned v1".

These enumerated operands and flags feel like opcode modifiers rather
than value operands, so displaying them differently makes sense.

Value and numeric operands are still comma separated.
2017-04-10 10:28:37 -07:00
Jakob Stoklund Olesen
d2f575b54a Add jump encodings to RISC-V.
Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
e5e5b30315 Add a fallthrough instruction.
Change jumps to fallthroughs in the branch relaxation pass before
computing the EBB offsets.
2017-04-06 14:22:32 -07:00