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Add encodings for Intel dynamic shift instructions.

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These instructions have a fixed register constraint; the shift amount is
passed in CL.

Add meta language syntax so a fixed register can be specified as
"GPR.rcx".
This commit is contained in:
Jakob Stoklund Olesen
2017-05-08 20:56:08 -07:00
parent db9f64d2f3
commit cdb3a71dd1
5 changed files with 72 additions and 5 deletions
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15
filetests/isa/intel/binary32.cton
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@@ -19,5 +19,20 @@ ebb0:
; asm: addl %ecx, %esi
[-,%rsi] v11 = iadd v2, v1 ; bin: 01 ce
; Dynamic shifts take the shift amount in %rcx.
; asm: shll %cl, %esi
[-,%rsi] v12 = ishl v2, v1 ; bin: d3 e6
; asm: shll %cl, %ecx
[-,%rcx] v13 = ishl v1, v1 ; bin: d3 e1
; asm: shrl %cl, %esi
[-,%rsi] v14 = ushr v2, v1 ; bin: d3 ee
; asm: shrl %cl, %ecx
[-,%rcx] v15 = ushr v1, v1 ; bin: d3 e9
; asm: sarl %cl, %esi
[-,%rsi] v16 = sshr v2, v1 ; bin: d3 fe
; asm: sarl %cl, %ecx
[-,%rcx] v17 = sshr v1, v1 ; bin: d3 f9
return
}