Generate SSA code from returns (#5172)

Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.

cranelift/codegen/src/isa/aarch64/abi.rs

@@ -398,7 +398,7 @@ impl ABIMachineSpec for AArch64MachineDeps {
         Inst::Args { args }
     }
 
-    fn gen_ret(setup_frame: bool, isa_flags: &aarch64_settings::Flags, rets: Vec<Reg>) -> Inst {
+    fn gen_ret(setup_frame: bool, isa_flags: &aarch64_settings::Flags, rets: Vec<RetPair>) -> Inst {
         if isa_flags.sign_return_address() && (setup_frame || isa_flags.sign_return_address_all()) {
             let key = if isa_flags.sign_return_address_with_bkey() {
                 APIKey::B

cranelift/codegen/src/isa/aarch64/inst.isle

@@ -787,7 +787,7 @@
 
        ;; A machine return instruction.
        (Ret
-        (rets VecReg))
+        (rets VecRetPair))
 
        ;; A machine return instruction with pointer authentication using SP as the
        ;; modifier. This instruction requires pointer authentication support
@@ -797,7 +797,7 @@
        (AuthenticatedRet
         (key APIKey)
         (is_hint bool)
-        (rets VecReg))
+        (rets VecRetPair))
 
        ;; An unconditional branch.
        (Jump

cranelift/codegen/src/isa/aarch64/inst/mod.rs

@@ -1022,8 +1022,8 @@ fn aarch64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             }
         }
         &Inst::Ret { ref rets } | &Inst::AuthenticatedRet { ref rets, .. } => {
-            for &ret in rets {
+            for ret in rets {
-                collector.reg_use(ret);
+                collector.reg_fixed_use(ret.vreg, ret.preg);
             }
         }
         &Inst::Jump { .. } => {}

cranelift/codegen/src/isa/aarch64/mod.rs

@@ -265,12 +265,15 @@ mod test {
         let buffer = backend.compile_function(&mut func, false).unwrap().buffer;
         let code = buffer.data();
 
-        // mov x3, #0x1234
+        // To update this comment, write the golden bytes to a file, and run the following command
-        // add w0, w0, w3
+        // on it to update:
-        // ret
+        // > aarch64-linux-gnu-objdump -b binary -D <file> -m aarch64
-        let golden = vec![
+        //
-            0x83, 0x46, 0x82, 0xd2, 0x00, 0x00, 0x03, 0x0b, 0xc0, 0x03, 0x5f, 0xd6,
+        // 0:   d2824682        mov     x2, #0x1234                     // #4660
-        ];
+        // 4:   0b020000        add     w0, w0, w2
+        // 8:   d65f03c0        ret
+
+        let golden = vec![130, 70, 130, 210, 0, 0, 2, 11, 192, 3, 95, 214];
 
         assert_eq!(code, &golden[..]);
     }
@@ -320,24 +323,28 @@ mod test {
             .unwrap();
         let code = result.buffer.data();
 
-        // mov     x10, #0x1234                    // #4660
+        // To update this comment, write the golden bytes to a file, and run the following command
-        // add     w12, w0, w10
+        // on it to update:
-        // mov     w11, w12
+        // > aarch64-linux-gnu-objdump -b binary -D <file> -m aarch64
-        // cbnz    x11, 0x20
+        //
-        // mov     x13, #0x1234                    // #4660
+        //   0:   d2824689        mov     x9, #0x1234                     // #4660
-        // add     w15, w12, w13
+        //   4:   0b09000b        add     w11, w0, w9
-        // mov     w14, w15
+        //   8:   2a0b03ea        mov     w10, w11
-        // cbnz    x14, 0x10
+        //   c:   b50000aa        cbnz    x10, 0x20
-        // mov     w1, w12
+        //  10:   d282468c        mov     x12, #0x1234                    // #4660
-        // cbnz    x1, 0x10
+        //  14:   0b0c016e        add     w14, w11, w12
-        // mov     x2, #0x1234                     // #4660
+        //  18:   2a0e03ed        mov     w13, w14
-        // sub     w0, w12, w2
+        //  1c:   b5ffffad        cbnz    x13, 0x10
-        // ret
+        //  20:   2a0b03e0        mov     w0, w11
+        //  24:   b5ffff60        cbnz    x0, 0x10
+        //  28:   d2824681        mov     x1, #0x1234                     // #4660
+        //  2c:   4b010160        sub     w0, w11, w1
+        //  30:   d65f03c0        ret
 
         let golden = vec![
-            138, 70, 130, 210, 12, 0, 10, 11, 235, 3, 12, 42, 171, 0, 0, 181, 141, 70, 130, 210,
+            137, 70, 130, 210, 11, 0, 9, 11, 234, 3, 11, 42, 170, 0, 0, 181, 140, 70, 130, 210,
-            143, 1, 13, 11, 238, 3, 15, 42, 174, 255, 255, 181, 225, 3, 12, 42, 97, 255, 255, 181,
+            110, 1, 12, 11, 237, 3, 14, 42, 173, 255, 255, 181, 224, 3, 11, 42, 96, 255, 255, 181,
-            130, 70, 130, 210, 128, 1, 2, 75, 192, 3, 95, 214,
+            129, 70, 130, 210, 96, 1, 1, 75, 192, 3, 95, 214,
         ];
 
         assert_eq!(code, &golden[..]);
@@ -393,14 +400,18 @@ mod test {
             .unwrap();
         let code = result.buffer.data();
 
+        // To update this comment, write the golden bytes to a file, and run the following command
+        // on it to update:
+        // > aarch64-linux-gnu-objdump -b binary -D <file> -m aarch64
+        //
         //   0:   7100081f        cmp     w0, #0x2
         //   4:   54000122        b.cs    0x28  // b.hs, b.nlast
-        //   8:   9a8023e9        csel    x9, xzr, x0, cs  // cs = hs, nlast
+        //   8:   9a8023e8        csel    x8, xzr, x0, cs  // cs = hs, nlast
         //   c:   d503229f        csdb
-        //  10:   10000088        adr     x8, 0x1c
+        //  10:   10000087        adr     x7, 0x20
-        //  14:   b8a95909        ldrsw   x9, [x8, w9, uxtw #2]
+        //  14:   b8a858e8        ldrsw   x8, [x7, w8, uxtw #2]
-        //  18:   8b090108        add     x8, x8, x9
+        //  18:   8b0800e7        add     x7, x7, x8
-        //  1c:   d61f0100        br      x8
+        //  1c:   d61f00e0        br      x7
         //  20:   00000010        udf     #16
         //  24:   00000018        udf     #24
         //  28:   d2800060        mov     x0, #0x3                        // #3
@@ -411,9 +422,10 @@ mod test {
         //  3c:   d65f03c0        ret
 
         let golden = vec![
-            31, 8, 0, 113, 34, 1, 0, 84, 233, 35, 128, 154, 159, 34, 3, 213, 136, 0, 0, 16, 9, 89,
+            31, 8, 0, 113, 34, 1, 0, 84, 232, 35, 128, 154, 159, 34, 3, 213, 135, 0, 0, 16, 232,
-            169, 184, 8, 1, 9, 139, 0, 1, 31, 214, 16, 0, 0, 0, 24, 0, 0, 0, 96, 0, 128, 210, 192,
+            88, 168, 184, 231, 0, 8, 139, 224, 0, 31, 214, 16, 0, 0, 0, 24, 0, 0, 0, 96, 0, 128,
-            3, 95, 214, 32, 0, 128, 210, 192, 3, 95, 214, 64, 0, 128, 210, 192, 3, 95, 214,
+            210, 192, 3, 95, 214, 32, 0, 128, 210, 192, 3, 95, 214, 64, 0, 128, 210, 192, 3, 95,
+            214,
         ];
 
         assert_eq!(code, &golden[..]);

cranelift/codegen/src/isa/riscv64/abi.rs

@@ -235,7 +235,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
         Inst::Args { args }
     }
 
-    fn gen_ret(_setup_frame: bool, _isa_flags: &Self::F, rets: Vec<Reg>) -> Inst {
+    fn gen_ret(_setup_frame: bool, _isa_flags: &Self::F, rets: Vec<RetPair>) -> Inst {
         Inst::Ret { rets }
     }
 

cranelift/codegen/src/isa/riscv64/inst.isle

@@ -71,7 +71,7 @@
     (Args
       (args VecArgPair))
 
-    (Ret (rets VecReg))
+    (Ret (rets VecRetPair))
 
      (Extend
       (rd WritableReg)

cranelift/codegen/src/isa/riscv64/inst/mod.rs

@@ -352,7 +352,9 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             }
         }
         &Inst::Ret { ref rets } => {
-            collector.reg_uses(&rets[..]);
+            for ret in rets {
+                collector.reg_fixed_use(ret.vreg, ret.preg);
+            }
         }
 
         &Inst::Extend { rd, rn, .. } => {

cranelift/codegen/src/isa/riscv64/mod.rs

@@ -233,13 +233,18 @@ mod test {
         );
         let buffer = backend.compile_function(&mut func, true).unwrap();
         let code = buffer.buffer.data();
-        // 0:   000015b7                lui     a1,0x1
+
-        // 4:   23458593                addi    a1,a1,564 # 0x1234
+        // To update this comment, write the golden bytes to a file, and run the following command
-        // 8:   00b5053b                addw    a0,a0,a1
+        // on it to update:
+        // > riscv64-linux-gnu-objdump -b binary -D <file> -m riscv
+        //
+        // 0:   000013b7                lui     t2,0x1
+        // 4:   23438393                addi    t2,t2,564 # 0x1234
+        // 8:   0075053b                .4byte  0x75053b
         // c:   00008067                ret
+
         let golden = vec![
-            0xb7, 0x15, 0x0, 0x0, 0x93, 0x85, 0x45, 0x23, 0x3b, 0x5, 0xb5, 0x0, 0x67, 0x80, 0x0,
+            183, 19, 0, 0, 147, 131, 67, 35, 59, 5, 117, 0, 103, 128, 0, 0,
-            0x0,
         ];
         assert_eq!(code, &golden[..]);
     }

cranelift/codegen/src/isa/s390x/abi.rs

@@ -457,7 +457,7 @@ impl ABIMachineSpec for S390xMachineDeps {
         Inst::Args { args }
     }
 
-    fn gen_ret(_setup_frame: bool, _isa_flags: &s390x_settings::Flags, rets: Vec<Reg>) -> Inst {
+    fn gen_ret(_setup_frame: bool, _isa_flags: &s390x_settings::Flags, rets: Vec<RetPair>) -> Inst {
         Inst::Ret {
             link: gpr(14),
             rets,

cranelift/codegen/src/isa/s390x/inst.isle

@@ -906,7 +906,7 @@
     ;; A machine return instruction.
     (Ret
       (link Reg)
-      (rets VecReg))
+      (rets VecRetPair))
 
     ;; An unconditional branch.
     (Jump

cranelift/codegen/src/isa/s390x/inst/emit.rs

@@ -3480,7 +3480,7 @@ impl Inst {
             }
 
             &Inst::Call { link, ref info } => {
-                let link = allocs.next_writable(link);
+                debug_assert_eq!(link.to_reg(), gpr(14));
 
                 // Add relocation for TLS libcalls to enable linker optimizations.
                 match &info.tls_symbol {
@@ -3509,7 +3509,7 @@ impl Inst {
                 }
             }
             &Inst::CallInd { link, ref info } => {
-                let link = allocs.next_writable(link);
+                debug_assert_eq!(link.to_reg(), gpr(14));
                 let rn = allocs.next(info.rn);
 
                 let opcode = 0x0d; // BASR
@@ -3523,7 +3523,7 @@ impl Inst {
             }
             &Inst::Args { .. } => {}
             &Inst::Ret { link, .. } => {
-                let link = allocs.next(link);
+                debug_assert_eq!(link, gpr(14));
 
                 let opcode = 0x07; // BCR
                 put(sink, &enc_rr(opcode, gpr(15), link));

cranelift/codegen/src/isa/s390x/inst/mod.rs

@@ -1009,17 +1009,17 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
             collector.reg_use(rn);
         }
         &Inst::Call { link, ref info } => {
-            collector.reg_def(link);
             for u in &info.uses {
                 collector.reg_fixed_use(u.vreg, u.preg);
             }
             for d in &info.defs {
                 collector.reg_fixed_def(d.vreg, d.preg);
             }
-            collector.reg_clobbers(info.clobbers);
+            let mut clobbers = info.clobbers.clone();
+            clobbers.add(link.to_reg().to_real_reg().unwrap().into());
+            collector.reg_clobbers(clobbers);
         }
         &Inst::CallInd { link, ref info } => {
-            collector.reg_def(link);
             collector.reg_use(info.rn);
             for u in &info.uses {
                 collector.reg_fixed_use(u.vreg, u.preg);
@@ -1027,16 +1027,21 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
             for d in &info.defs {
                 collector.reg_fixed_def(d.vreg, d.preg);
             }
-            collector.reg_clobbers(info.clobbers);
+            let mut clobbers = info.clobbers.clone();
+            clobbers.add(link.to_reg().to_real_reg().unwrap().into());
+            collector.reg_clobbers(clobbers);
         }
         &Inst::Args { ref args } => {
             for arg in args {
                 collector.reg_fixed_def(arg.vreg, arg.preg);
             }
         }
-        &Inst::Ret { link, ref rets } => {
+        &Inst::Ret { ref rets, .. } => {
-            collector.reg_use(link);
+            // NOTE: we explicitly don't mark the link register as used here, as the use is only in
-            collector.reg_uses(&rets[..]);
+            // the epilog where callee-save registers are restored.
+            for ret in rets {
+                collector.reg_fixed_use(ret.vreg, ret.preg);
+            }
         }
         &Inst::Jump { .. } => {}
         &Inst::IndirectBr { rn, .. } => {
@@ -3231,7 +3236,7 @@ impl Inst {
                 format!("{} {}, {}", op, rd, rn)
             }
             &Inst::Call { link, ref info, .. } => {
-                let link = pretty_print_reg(link.to_reg(), allocs);
+                let link = link.to_reg();
                 let tls_symbol = match &info.tls_symbol {
                     None => "".to_string(),
                     Some(SymbolReloc::TlsGd { name }) => {
@@ -3239,12 +3244,19 @@ impl Inst {
                     }
                     _ => unreachable!(),
                 };
-                format!("brasl {}, {}{}", link, info.dest.display(None), tls_symbol)
+                debug_assert_eq!(link, gpr(14));
+                format!(
+                    "brasl {}, {}{}",
+                    show_reg(link),
+                    info.dest.display(None),
+                    tls_symbol
+                )
             }
             &Inst::CallInd { link, ref info, .. } => {
-                let link = pretty_print_reg(link.to_reg(), allocs);
+                let link = link.to_reg();
                 let rn = pretty_print_reg(info.rn, allocs);
-                format!("basr {}, {}", link, rn)
+                debug_assert_eq!(link, gpr(14));
+                format!("basr {}, {}", show_reg(link), rn)
             }
             &Inst::Args { ref args } => {
                 let mut s = "args".to_string();
@@ -3257,8 +3269,8 @@ impl Inst {
                 s
             }
             &Inst::Ret { link, .. } => {
-                let link = pretty_print_reg(link, allocs);
+                debug_assert_eq!(link, gpr(14));
-                format!("br {}", link)
+                format!("br {}", show_reg(link))
             }
             &Inst::Jump { dest } => {
                 let dest = dest.to_string();

cranelift/codegen/src/isa/s390x/mod.rs

@@ -298,26 +298,25 @@ mod test {
 
         // FIXME: the branching logic should be optimized more
 
-        // ahi %r2, 4660
+        // To update this comment, write the golden bytes to a file, and run the following command
-        // chi %r2, 0
+        // on it to update:
-        // jglh label1 ; jg label2
+        // > s390x-linux-gnu-objdump -b binary -D <file> -m s390
-        // jg label6
+        //
-        // jg label3
+        //  0:   a7 2a 12 34             ahi     %r2,4660
-        // ahik %r3, %r2, 4660
+        //  4:   a7 2e 00 00             chi     %r2,0
-        // chi %r3, 0
+        //  8:   c0 64 00 00 00 0b       jglh    0x1e
-        // jglh label4 ; jg label5
+        //  e:   ec 32 12 34 00 d8       ahik    %r3,%r2,4660
-        // jg label3
+        // 14:   a7 3e 00 00             chi     %r3,0
-        // jg label6
+        // 18:   c0 64 ff ff ff fb       jglh    0xe
-        // chi %r2, 0
+        // 1e:   a7 2e 00 00             chi     %r2,0
-        // jglh label7 ; jg label8
+        // 22:   c0 64 ff ff ff f6       jglh    0xe
-        // jg label3
+        // 28:   a7 2a ed cc             ahi     %r2,-4660
-        // ahi %r2, -4660
+        // 2c:   07 fe                   br      %r14
-        // br %r14
 
         let golden = vec![
-            236, 50, 18, 52, 0, 216, 167, 62, 0, 0, 192, 100, 0, 0, 0, 11, 236, 67, 18, 52, 0, 216,
+            167, 42, 18, 52, 167, 46, 0, 0, 192, 100, 0, 0, 0, 11, 236, 50, 18, 52, 0, 216, 167,
-            167, 78, 0, 0, 192, 100, 255, 255, 255, 251, 167, 62, 0, 0, 192, 100, 255, 255, 255,
+            62, 0, 0, 192, 100, 255, 255, 255, 251, 167, 46, 0, 0, 192, 100, 255, 255, 255, 246,
-            246, 236, 35, 237, 204, 0, 216, 7, 254,
+            167, 42, 237, 204, 7, 254,
         ];
 
         assert_eq!(code, &golden[..]);

cranelift/codegen/src/isa/x64/abi.rs

@@ -298,7 +298,11 @@ impl ABIMachineSpec for X64ABIMachineSpec {
         Inst::Args { args }
     }
 
-    fn gen_ret(_setup_frame: bool, _isa_flags: &x64_settings::Flags, rets: Vec<Reg>) -> Self::I {
+    fn gen_ret(
+        _setup_frame: bool,
+        _isa_flags: &x64_settings::Flags,
+        rets: Vec<RetPair>,
+    ) -> Self::I {
         Inst::ret(rets)
     }
 

cranelift/codegen/src/isa/x64/inst.isle

@@ -333,7 +333,7 @@
         (args VecArgPair))
 
        ;; Return.
-       (Ret (rets VecReg))
+       (Ret (rets VecRetPair))
 
        ;; Jump to a known target: jmp simm32.
        (JmpKnown (dst MachLabel))

cranelift/codegen/src/isa/x64/inst/mod.rs

@@ -526,7 +526,7 @@ impl Inst {
         }
     }
 
-    pub(crate) fn ret(rets: Vec<Reg>) -> Inst {
+    pub(crate) fn ret(rets: Vec<RetPair>) -> Inst {
         Inst::Ret { rets }
     }
 
@@ -2081,8 +2081,8 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
         Inst::Ret { rets } => {
             // The return value(s) are live-out; we represent this
             // with register uses on the return instruction.
-            for &ret in rets {
+            for ret in rets.iter() {
-                collector.reg_use(ret);
+                collector.reg_fixed_use(ret.vreg, ret.preg);
             }
         }
 

cranelift/codegen/src/isa/x64/mod.rs

@@ -333,31 +333,36 @@ mod test {
             .unwrap();
         let code = result.buffer.data();
 
-        // 00000000  55                push rbp
+        // To update this comment, write the golden bytes to a file, and run the following
-        // 00000001  4889E5            mov rbp,rsp
+        // command on it:
-        // 00000004  81C734120000      add edi,0x1234
+        // > objdump -b binary -D <file> -m i386:x86-64 -M intel
-        // 0000000A  85FF              test edi,edi
+        //
-        // 0000000C  0F841C000000      jz near 0x2e
+        //  0:   55                      push   rbp
-        // 00000012  4989F8            mov r8,rdi
+        //  1:   48 89 e5                mov    rbp,rsp
-        // 00000015  4889F8            mov rax,rdi
+        //  4:   48 89 fe                mov    rsi,rdi
-        // 00000018  81E834120000      sub eax,0x1234
+        //  7:   81 c6 34 12 00 00       add    esi,0x1234
-        // 0000001E  4401C0            add eax,r8d
+        //  d:   85 f6                   test   esi,esi
-        // 00000021  85FF              test edi,edi
+        //  f:   0f 84 1c 00 00 00       je     0x31
-        // 00000023  0F8505000000      jnz near 0x2e
+        // 15:   49 89 f0                mov    r8,rsi
-        // 00000029  4889EC            mov rsp,rbp
+        // 18:   48 89 f0                mov    rax,rsi
-        // 0000002C  5D                pop rbp
+        // 1b:   81 e8 34 12 00 00       sub    eax,0x1234
-        // 0000002D  C3                ret
+        // 21:   44 01 c0                add    eax,r8d
-        // 0000002E  4989F8            mov r8,rdi
+        // 24:   85 f6                   test   esi,esi
-        // 00000031  4181C034120000    add r8d,0x1234
+        // 26:   0f 85 05 00 00 00       jne    0x31
-        // 00000038  4585C0            test r8d,r8d
+        // 2c:   48 89 ec                mov    rsp,rbp
-        // 0000003B  0F85EDFFFFFF      jnz near 0x2e
+        // 2f:   5d                      pop    rbp
-        // 00000041  E9CFFFFFFF        jmp 0x15
+        // 30:   c3                      ret
+        // 31:   49 89 f0                mov    r8,rsi
+        // 34:   41 81 c0 34 12 00 00    add    r8d,0x1234
+        // 3b:   45 85 c0                test   r8d,r8d
+        // 3e:   0f 85 ed ff ff ff       jne    0x31
+        // 44:   e9 cf ff ff ff          jmp    0x18
 
         let golden = vec![
-            85, 72, 137, 229, 129, 199, 52, 18, 0, 0, 133, 255, 15, 132, 28, 0, 0, 0, 73, 137, 248,
+            85, 72, 137, 229, 72, 137, 254, 129, 198, 52, 18, 0, 0, 133, 246, 15, 132, 28, 0, 0, 0,
-            72, 137, 248, 129, 232, 52, 18, 0, 0, 68, 1, 192, 133, 255, 15, 133, 5, 0, 0, 0, 72,
+            73, 137, 240, 72, 137, 240, 129, 232, 52, 18, 0, 0, 68, 1, 192, 133, 246, 15, 133, 5,
-            137, 236, 93, 195, 73, 137, 248, 65, 129, 192, 52, 18, 0, 0, 69, 133, 192, 15, 133,
+            0, 0, 0, 72, 137, 236, 93, 195, 73, 137, 240, 65, 129, 192, 52, 18, 0, 0, 69, 133, 192,
-            237, 255, 255, 255, 233, 207, 255, 255, 255,
+            15, 133, 237, 255, 255, 255, 233, 207, 255, 255, 255,
         ];
 
         assert_eq!(code, &golden[..]);
@@ -433,35 +438,42 @@ mod test {
             .unwrap();
         let code = result.buffer.data();
 
-        // 00000000  55                push rbp
+        // To update this comment, write the golden bytes to a file, and run the following
-        // 00000001  4889E5            mov rbp,rsp
+        // command on it:
-        // 00000004  83FF02            cmp edi,byte +0x2
+        // > objdump -b binary -D <file> -m i386:x86-64 -M intel
-        // 00000007  0F8327000000      jnc near 0x34
+        //
-        // 0000000D  448BDF            mov r11d,edi
+        //  0:   55                      push   rbp
-        // 00000010  41BA00000000      mov r10d,0x0
+        //  1:   48 89 e5                mov    rbp,rsp
-        // 00000016  4D0F43DA          cmovnc r11,r10
+        //  4:   83 ff 02                cmp    edi,0x2
-        // 0000001A  4C8D150B000000    lea r10,[rel 0x2c]
+        //  7:   0f 83 27 00 00 00       jae    0x34
-        // 00000021  4F635C9A00        movsxd r11,dword [r10+r11*4+0x0]
+        //  d:   44 8b d7                mov    r10d,edi
-        // 00000026  4D01DA            add r10,r11
+        // 10:   41 b9 00 00 00 00       mov    r9d,0x0
-        // 00000029  41FFE2            jmp r10
+        // 16:   4d 0f 43 d1             cmovae r10,r9
-        // 0000002C  120000001C000000  (jumptable data)
+        // 1a:   4c 8d 0d 0b 00 00 00    lea    r9,[rip+0xb]        # 0x2c
-        // 00000034  B803000000        mov eax,0x3
+        // 21:   4f 63 54 91 00          movsxd r10,DWORD PTR [r9+r10*4+0x0]
-        // 00000039  4889EC            mov rsp,rbp
+        // 26:   4d 01 d1                add    r9,r10
-        // 0000003C  5D                pop rbp
+        // 29:   41 ff e1                jmp    r9
-        // 0000003D  C3                ret
+        // 2c:   12 00                   adc    al,BYTE PTR [rax]
-        // 0000003E  B801000000        mov eax,0x1
+        // 2e:   00 00                   add    BYTE PTR [rax],al
-        // 00000043  4889EC            mov rsp,rbp
+        // 30:   1c 00                   sbb    al,0x0
-        // 00000046  5D                pop rbp
+        // 32:   00 00                   add    BYTE PTR [rax],al
-        // 00000047  C3                ret
+        // 34:   b8 03 00 00 00          mov    eax,0x3
-        // 00000048  B802000000        mov eax,0x2
+        // 39:   48 89 ec                mov    rsp,rbp
-        // 0000004D  4889EC            mov rsp,rbp
+        // 3c:   5d                      pop    rbp
-        // 00000050  5D                pop rbp
+        // 3d:   c3                      ret
-        // 00000051  C3                ret
+        // 3e:   b8 01 00 00 00          mov    eax,0x1
+        // 43:   48 89 ec                mov    rsp,rbp
+        // 46:   5d                      pop    rbp
+        // 47:   c3                      ret
+        // 48:   b8 02 00 00 00          mov    eax,0x2
+        // 4d:   48 89 ec                mov    rsp,rbp
+        // 50:   5d                      pop    rbp
+        // 51:   c3                      ret
 
         let golden = vec![
-            85, 72, 137, 229, 131, 255, 2, 15, 131, 39, 0, 0, 0, 68, 139, 223, 65, 186, 0, 0, 0, 0,
+            85, 72, 137, 229, 131, 255, 2, 15, 131, 39, 0, 0, 0, 68, 139, 215, 65, 185, 0, 0, 0, 0,
-            77, 15, 67, 218, 76, 141, 21, 11, 0, 0, 0, 79, 99, 92, 154, 0, 77, 1, 218, 65, 255,
+            77, 15, 67, 209, 76, 141, 13, 11, 0, 0, 0, 79, 99, 84, 145, 0, 77, 1, 209, 65, 255,
-            226, 18, 0, 0, 0, 28, 0, 0, 0, 184, 3, 0, 0, 0, 72, 137, 236, 93, 195, 184, 1, 0, 0, 0,
+            225, 18, 0, 0, 0, 28, 0, 0, 0, 184, 3, 0, 0, 0, 72, 137, 236, 93, 195, 184, 1, 0, 0, 0,
             72, 137, 236, 93, 195, 184, 2, 0, 0, 0, 72, 137, 236, 93, 195,
         ];
 

cranelift/codegen/src/machinst/abi.rs

@@ -136,6 +136,17 @@ pub struct ArgPair {
     pub preg: Reg,
 }
 
+/// A type used by backends to track return register binding info in the "ret"
+/// pseudoinst. The pseudoinst holds a vec of `RetPair` structs.
+#[derive(Clone, Debug)]
+pub struct RetPair {
+    /// The vreg that is returned by this pseudionst.
+    pub vreg: Reg,
+    /// The preg that the arg is returned through; this constrains the vreg's
+    /// placement at the pseudoinst.
+    pub preg: Reg,
+}
+
 /// A location for (part of) an argument or return value. These "storage slots"
 /// are specified for each register-sized part of an argument.
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -421,7 +432,7 @@ pub trait ABIMachineSpec {
     fn gen_args(isa_flags: &Self::F, args: Vec<ArgPair>) -> Self::I;
 
     /// Generate a return instruction.
-    fn gen_ret(setup_frame: bool, isa_flags: &Self::F, rets: Vec<Reg>) -> Self::I;
+    fn gen_ret(setup_frame: bool, isa_flags: &Self::F, rets: Vec<RetPair>) -> Self::I;
 
     /// Generate an add-with-immediate. Note that even if this uses a scratch
     /// register, it must satisfy two requirements:
@@ -1483,8 +1494,10 @@ impl<M: ABIMachineSpec> Callee<M> {
         &self,
         sigs: &SigSet,
         idx: usize,
-        from_regs: ValueRegs<Writable<Reg>>,
+        from_regs: ValueRegs<Reg>,
-    ) -> SmallInstVec<M::I> {
+        vregs: &mut VRegAllocator<M::I>,
+    ) -> (SmallVec<[RetPair; 2]>, SmallInstVec<M::I>) {
+        let mut reg_pairs = smallvec![];
         let mut ret = smallvec![];
         let word_bits = M::word_bits() as u8;
         match &sigs[self.sig].rets(sigs)[idx] {
@@ -1497,24 +1510,31 @@ impl<M: ABIMachineSpec> Callee<M> {
                         } => {
                             let from_bits = ty_bits(ty) as u8;
                             let ext = M::get_ext_mode(sigs[self.sig].call_conv, extension);
-                            let reg: Writable<Reg> = Writable::from_reg(Reg::from(reg));
+                            let vreg = match (ext, from_bits) {
-                            match (ext, from_bits) {
+                                (ir::ArgumentExtension::Uext, n)
-                                (ArgumentExtension::Uext, n) | (ArgumentExtension::Sext, n)
+                                | (ir::ArgumentExtension::Sext, n)
                                     if n < word_bits =>
                                 {
-                                    let signed = ext == ArgumentExtension::Sext;
+                                    let signed = ext == ir::ArgumentExtension::Sext;
+                                    let dst = writable_value_regs(vregs.alloc(ty).unwrap())
+                                        .only_reg()
+                                        .unwrap();
                                     ret.push(M::gen_extend(
-                                        reg,
+                                        dst, from_reg, signed, from_bits,
-                                        from_reg.to_reg(),
-                                        signed,
-                                        from_bits,
                                         /* to_bits = */ word_bits,
                                     ));
+                                    dst.to_reg()
                                 }
                                 _ => {
-                                    ret.push(M::gen_move(reg, from_reg.to_reg(), ty));
+                                    // No move needed, regalloc2 will emit it using the constraint
+                                    // added by the RetPair.
+                                    from_reg
                                 }
                             };
+                            reg_pairs.push(RetPair {
+                                vreg,
+                                preg: Reg::from(reg),
+                            });
                         }
                         &ABIArgSlot::Stack {
                             offset,
@@ -1533,16 +1553,17 @@ impl<M: ABIMachineSpec> Callee<M> {
                             let ext = M::get_ext_mode(sigs[self.sig].call_conv, extension);
                             // Trash the from_reg; it should be its last use.
                             match (ext, from_bits) {
-                                (ArgumentExtension::Uext, n) | (ArgumentExtension::Sext, n)
+                                (ir::ArgumentExtension::Uext, n)
+                                | (ir::ArgumentExtension::Sext, n)
                                     if n < word_bits =>
                                 {
-                                    assert_eq!(M::word_reg_class(), from_reg.to_reg().class());
+                                    assert_eq!(M::word_reg_class(), from_reg.class());
-                                    let signed = ext == ArgumentExtension::Sext;
+                                    let signed = ext == ir::ArgumentExtension::Sext;
+                                    let dst = writable_value_regs(vregs.alloc(ty).unwrap())
+                                        .only_reg()
+                                        .unwrap();
                                     ret.push(M::gen_extend(
-                                        Writable::from_reg(from_reg.to_reg()),
+                                        dst, from_reg, signed, from_bits,
-                                        from_reg.to_reg(),
-                                        signed,
-                                        from_bits,
                                         /* to_bits = */ word_bits,
                                     ));
                                     // Store the extended version.
@@ -1553,21 +1574,21 @@ impl<M: ABIMachineSpec> Callee<M> {
                             ret.push(M::gen_store_base_offset(
                                 self.ret_area_ptr.unwrap().to_reg(),
                                 off,
-                                from_reg.to_reg(),
+                                from_reg,
                                 ty,
                             ));
                         }
                     }
                 }
             }
-            &ABIArg::StructArg { .. } => {
+            ABIArg::StructArg { .. } => {
                 panic!("StructArg in return position is unsupported");
             }
-            &ABIArg::ImplicitPtrArg { .. } => {
+            ABIArg::ImplicitPtrArg { .. } => {
                 panic!("ImplicitPtrArg in return position is unsupported");
             }
         }
-        ret
+        (reg_pairs, ret)
     }
 
     /// Generate any setup instruction needed to save values to the
@@ -1594,22 +1615,7 @@ impl<M: ABIMachineSpec> Callee<M> {
     }
 
     /// Generate a return instruction.
-    pub fn gen_ret(&self, sigs: &SigSet) -> M::I {
+    pub fn gen_ret(&self, rets: Vec<RetPair>) -> M::I {
-        let mut rets = vec![];
-        for ret in sigs[self.sig].rets(sigs) {
-            match ret {
-                ABIArg::Slots { slots, .. } => {
-                    for slot in slots {
-                        match slot {
-                            ABIArgSlot::Reg { reg, .. } => rets.push(Reg::from(*reg)),
-                            _ => {}
-                        }
-                    }
-                }
-                _ => {}
-            }
-        }
-
         M::gen_ret(self.setup_frame, &self.isa_flags, rets)
     }
 

cranelift/codegen/src/machinst/isle.rs

@@ -7,8 +7,9 @@ use std::cell::Cell;
 use target_lexicon::Triple;
 
 pub use super::MachLabel;
+use super::RetPair;
 pub use crate::ir::{
-    condcodes, condcodes::CondCode, dynamic_to_fixed, ArgumentExtension, Constant,
+    condcodes, condcodes::CondCode, dynamic_to_fixed, ArgumentExtension, ArgumentPurpose, Constant,
     DynamicStackSlot, ExternalName, FuncRef, GlobalValue, Immediate, SigRef, StackSlot,
 };
 pub use crate::isa::unwind::UnwindInst;
@@ -23,7 +24,7 @@ pub type ValueSlice = (ValueList, usize);
 pub type ValueArray2 = [Value; 2];
 pub type ValueArray3 = [Value; 3];
 pub type WritableReg = Writable<Reg>;
-pub type VecReg = Vec<Reg>;
+pub type VecRetPair = Vec<RetPair>;
 pub type VecMask = Vec<u8>;
 pub type ValueRegs = crate::machinst::ValueRegs<Reg>;
 pub type WritableValueRegs = crate::machinst::ValueRegs<WritableReg>;
@@ -422,10 +423,6 @@ macro_rules! isle_lower_prelude_methods {
             ))
         }
 
-        fn retval(&mut self, i: usize) -> WritableValueRegs {
-            self.lower_ctx.retval(i)
-        }
-
         fn only_writable_reg(&mut self, regs: WritableValueRegs) -> Option<WritableReg> {
             regs.only_reg()
         }
@@ -590,6 +587,17 @@ macro_rules! isle_lower_prelude_methods {
         fn floatcc_inverse(&mut self, cc: &FloatCC) -> FloatCC {
             cc.inverse()
         }
+
+        /// Generate the return instruction.
+        fn gen_return(&mut self, (list, off): ValueSlice) {
+            let rets = (off..list.len(&self.lower_ctx.dfg().value_lists))
+                .map(|ix| {
+                    let val = list.get(ix, &self.lower_ctx.dfg().value_lists).unwrap();
+                    self.put_in_regs(val)
+                })
+                .collect();
+            self.lower_ctx.gen_return(rets);
+        }
     };
 }
 

cranelift/codegen/src/machinst/lower.rs

@@ -158,8 +158,8 @@ pub struct Lower<'func, I: VCodeInst> {
     /// Mapping from `Value` (SSA value in IR) to virtual register.
     value_regs: SecondaryMap<Value, ValueRegs<Reg>>,
 
-    /// Return-value vregs.
+    /// sret registers, if needed.
-    retval_regs: Vec<ValueRegs<Reg>>,
+    sret_reg: Option<ValueRegs<Reg>>,
 
     /// Instruction colors at block exits. From this map, we can recover all
     /// instruction colors by scanning backward from the block end and
@@ -370,12 +370,13 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
             }
         }
 
-        // Assign vreg(s) to each return value.
+        // Make a sret register, if one is needed.
-        let mut retval_regs = vec![];
+        let mut sret_reg = None;
         for ret in &vcode.abi().signature().returns.clone() {
-            let regs = vregs.alloc(ret.value_type)?;
+            if ret.purpose == ArgumentPurpose::StructReturn {
-            retval_regs.push(regs);
+                assert!(sret_reg.is_none());
-            trace!("retval gets regs {:?}", regs);
+                sret_reg = Some(vregs.alloc(ret.value_type)?);
+            }
         }
 
         // Compute instruction colors, find constant instructions, and find instructions with
@@ -414,7 +415,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
             vcode,
             vregs,
             value_regs,
-            retval_regs,
+            sret_reg,
             block_end_colors,
             side_effect_inst_entry_colors,
             inst_constants,
@@ -576,15 +577,15 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
                     let ty = self.abi().signature().params[i].value_type;
                     // The ABI implementation must have ensured that a StructReturn
                     // arg is present in the return values.
-                    let struct_ret_idx = self
+                    assert!(self
                         .abi()
                         .signature()
                         .returns
                         .iter()
                         .position(|ret| ret.purpose == ArgumentPurpose::StructReturn)
-                        .expect("StructReturn return value not present!");
+                        .is_some());
                     self.emit(I::gen_move(
-                        Writable::from_reg(self.retval_regs[struct_ret_idx].regs()[0]),
+                        Writable::from_reg(self.sret_reg.unwrap().regs()[0]),
                         regs.regs()[0].to_reg(),
                         ty,
                     ));
@@ -611,21 +612,36 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
         }
     }
 
-    fn gen_retval_setup(&mut self) {
+    /// Generate the return instruction.
-        let retval_regs = self.retval_regs.clone();
+    pub fn gen_return(&mut self, rets: Vec<ValueRegs<Reg>>) {
-        for (i, regs) in retval_regs.into_iter().enumerate() {
+        let mut out_rets = vec![];
-            let regs = writable_value_regs(regs);
+
-            for insn in self
+        let mut rets = rets.into_iter();
-                .vcode
+        for (i, ret) in self
             .abi()
-                .gen_copy_regs_to_retval(self.sigs(), i, regs)
+            .signature()
+            .returns
+            .clone()
             .into_iter()
+            .enumerate()
         {
+            let regs = if ret.purpose == ArgumentPurpose::StructReturn {
+                self.sret_reg.unwrap().clone()
+            } else {
+                rets.next().unwrap()
+            };
+
+            let (regs, insns) = self.vcode.abi().gen_copy_regs_to_retval(
+                self.vcode.sigs(),
+                i,
+                regs,
+                &mut self.vregs,
+            );
+            out_rets.extend(regs);
+            for insn in insns {
                 self.emit(insn);
             }
         }
-        let inst = self.vcode.abi().gen_ret(self.sigs());
-        self.emit(inst);
 
         // Hack: generate a virtual instruction that uses vmctx in
         // order to keep it alive for the duration of the function,
@@ -636,6 +652,9 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
                 self.emit(I::gen_dummy_use(vmctx_reg));
             }
         }
+
+        let inst = self.abi().gen_ret(out_rets);
+        self.emit(inst);
     }
 
     /// Has this instruction been sunk to a use-site (i.e., away from its
@@ -720,10 +739,6 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
                 trace!("lowering: inst {}: {:?}", inst, self.f.dfg[inst]);
                 backend.lower(self, inst)?;
             }
-            if data.opcode().is_return() {
-                // Return: handle specially, using ABI-appropriate sequence.
-                self.gen_retval_setup();
-            }
 
             let loc = self.srcloc(inst);
             self.finish_ir_inst(loc);
@@ -1026,14 +1041,6 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
     pub fn abi_mut(&mut self) -> &mut Callee<I::ABIMachineSpec> {
         self.vcode.abi_mut()
     }
-
-    /// Get the (virtual) register that receives the return value. A return
-    /// instruction should lower into a sequence that fills this register. (Why
-    /// not allow the backend to specify its own result register for the return?
-    /// Because there may be multiple return points.)
-    pub fn retval(&self, idx: usize) -> ValueRegs<Writable<Reg>> {
-        writable_value_regs(self.retval_regs[idx])
-    }
 }
 
 /// Instruction input/output queries.

cranelift/codegen/src/prelude_lower.isle

@@ -158,6 +158,7 @@
 (type BoxExternalName (primitive BoxExternalName))
 (type RelocDistance (primitive RelocDistance))
 (type VecArgPair extern (enum))
+(type VecRetPair extern (enum))
 
 ;;;; Helper Clif Extractors ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -614,10 +615,6 @@
 
 ;;;; Helpers for generating returns ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-;; The (writable) register(s) that will contain the n'th return value.
-(decl retval (usize) WritableValueRegs)
-(extern constructor retval retval)
-
 ;; Extractor to check for the special case that a `WritableValueRegs`
 ;; contains only a single register.
 (decl only_writable_reg (WritableReg) WritableValueRegs)
@@ -725,31 +722,14 @@
 (decl gen_move (Type WritableReg Reg) MInst)
 (extern constructor gen_move gen_move)
 
-;; Copy a return value to a set of registers.
+;; Generate a return instruction
-(decl copy_to_regs (WritableValueRegs Value) Unit)
-(rule (copy_to_regs dsts val @ (value_type ty))
-      (let ((srcs ValueRegs (put_in_regs val)))
-        (copy_to_regs_range ty (value_regs_range srcs) dsts srcs)))
-
-;; Helper for `copy_to_regs` that uses a range to index into the reg/value
-;; vectors. Fails for the empty range.
-(decl copy_to_regs_range (Type Range WritableValueRegs ValueRegs) Unit)
-
-(rule (copy_to_regs_range ty (range_empty) dsts srcs)
-      (unit))
-
-(rule (copy_to_regs_range ty (range_unwrap head tail) dsts srcs)
-      (let ((dst WritableReg (writable_regs_get dsts head))
-            (src Reg (value_regs_get srcs head))
-            (_ Unit (emit (gen_move ty dst src))))
-        (copy_to_regs_range ty tail dsts srcs)))
-
-
 (decl lower_return (Range ValueSlice) InstOutput)
-(rule (lower_return (range_empty) _) (output_none))
+(rule (lower_return _ vals)
-(rule (lower_return (range_unwrap head tail) args)
+      (let ((_ Unit (gen_return vals)))
-      (let ((_ Unit (copy_to_regs (retval head) (value_slice_get args head))))
+        (output_none)))
-        (lower_return tail args)))
+
+(decl gen_return (ValueSlice) Unit)
+(extern constructor gen_return gen_return)
 
 ;;;; Automatic conversions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 

cranelift/filetests/filetests/isa/aarch64/amodes.clif

@@ -36,8 +36,8 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   mov w4, w0
+;   mov w3, w0
-;   ldr w0, [x4, w1, UXTW]
+;   ldr w0, [x3, w1, UXTW]
 ;   ret
 
 function %f8(i64, i32) -> i32 {
@@ -52,10 +52,10 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   add x4, x0, #68
+;   add x3, x0, #68
-;   add x4, x4, x0
+;   add x3, x3, x0
-;   add x4, x4, x1, SXTW
+;   add x3, x3, x1, SXTW
-;   ldr w0, [x4, w1, SXTW]
+;   ldr w0, [x3, w1, SXTW]
 ;   ret
 
 function %f9(i64, i64, i64) -> i32 {
@@ -69,10 +69,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   mov x6, x0
+;   mov x5, x0
-;   add x6, x6, x2
+;   add x5, x5, x2
-;   add x6, x6, x1
+;   add x5, x5, x1
-;   ldr w0, [x6, #48]
+;   ldr w0, [x5, #48]
 ;   ret
 
 function %f10(i64, i64, i64) -> i32 {
@@ -86,10 +86,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x5, #4100
+;   movz x4, #4100
-;   add x5, x5, x1
+;   add x4, x4, x1
-;   add x5, x5, x2
+;   add x4, x4, x2
-;   ldr w0, [x5, x0]
+;   ldr w0, [x4, x0]
 ;   ret
 
 function %f10() -> i32 {
@@ -100,8 +100,8 @@ block0:
 }
 
 ; block0:
-;   movz x1, #1234
+;   movz x0, #1234
-;   ldr w0, [x1]
+;   ldr w0, [x0]
 ;   ret
 
 function %f11(i64) -> i32 {
@@ -113,8 +113,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   add x3, x0, #8388608
+;   add x2, x0, #8388608
-;   ldr w0, [x3]
+;   ldr w0, [x2]
 ;   ret
 
 function %f12(i64) -> i32 {
@@ -126,8 +126,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   sub x3, x0, #4
+;   sub x2, x0, #4
-;   ldr w0, [x3]
+;   ldr w0, [x2]
 ;   ret
 
 function %f13(i64) -> i32 {
@@ -139,10 +139,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz w3, #51712
+;   movz w2, #51712
-;   movk w3, w3, #15258, LSL #16
+;   movk w2, w2, #15258, LSL #16
-;   add x3, x3, x0
+;   add x2, x2, x0
-;   ldr w0, [x3]
+;   ldr w0, [x2]
 ;   ret
 
 function %f14(i32) -> i32 {
@@ -153,8 +153,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sxtw x3, w0
+;   sxtw x2, w0
-;   ldr w0, [x3]
+;   ldr w0, [x2]
 ;   ret
 
 function %f15(i32, i32) -> i32 {
@@ -167,8 +167,8 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sxtw x4, w0
+;   sxtw x3, w0
-;   ldr w0, [x4, w1, SXTW]
+;   ldr w0, [x3, w1, SXTW]
 ;   ret
 
 function %f18(i64, i64, i64) -> i32 {
@@ -180,8 +180,8 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movn w5, #4097
+;   movn w4, #4097
-;   ldrsh x0, [x5]
+;   ldrsh x0, [x4]
 ;   ret
 
 function %f19(i64, i64, i64) -> i32 {
@@ -193,8 +193,8 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x5, #4098
+;   movz x4, #4098
-;   ldrsh x0, [x5]
+;   ldrsh x0, [x4]
 ;   ret
 
 function %f20(i64, i64, i64) -> i32 {
@@ -206,9 +206,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movn w5, #4097
+;   movn w4, #4097
-;   sxtw x7, w5
+;   sxtw x6, w4
-;   ldrsh x0, [x7]
+;   ldrsh x0, [x6]
 ;   ret
 
 function %f21(i64, i64, i64) -> i32 {
@@ -220,9 +220,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x5, #4098
+;   movz x4, #4098
-;   sxtw x7, w5
+;   sxtw x6, w4
-;   ldrsh x0, [x7]
+;   ldrsh x0, [x6]
 ;   ret
 
 function %i128(i64) -> i128 {
@@ -233,11 +233,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
+;   mov x6, x0
-;   mov x6, x8
+;   mov x4, x6
-;   ldp x0, x1, [x6]
+;   ldp x0, x1, [x4]
-;   mov x7, x8
+;   mov x5, x6
-;   stp x0, x1, [x7]
+;   stp x0, x1, [x5]
 ;   ret
 
 function %i128_imm_offset(i64) -> i128 {
@@ -248,11 +248,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
+;   mov x6, x0
-;   mov x6, x8
+;   mov x4, x6
-;   ldp x0, x1, [x6, #16]
+;   ldp x0, x1, [x4, #16]
-;   mov x7, x8
+;   mov x5, x6
-;   stp x0, x1, [x7, #16]
+;   stp x0, x1, [x5, #16]
 ;   ret
 
 function %i128_imm_offset_large(i64) -> i128 {
@@ -263,11 +263,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
+;   mov x6, x0
-;   mov x6, x8
+;   mov x4, x6
-;   ldp x0, x1, [x6, #504]
+;   ldp x0, x1, [x4, #504]
-;   mov x7, x8
+;   mov x5, x6
-;   stp x0, x1, [x7, #504]
+;   stp x0, x1, [x5, #504]
 ;   ret
 
 function %i128_imm_offset_negative_large(i64) -> i128 {
@@ -278,11 +278,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
+;   mov x6, x0
-;   mov x6, x8
+;   mov x4, x6
-;   ldp x0, x1, [x6, #-512]
+;   ldp x0, x1, [x4, #-512]
-;   mov x7, x8
+;   mov x5, x6
-;   stp x0, x1, [x7, #-512]
+;   stp x0, x1, [x5, #-512]
 ;   ret
 
 function %i128_add_offset(i64) -> i128 {
@@ -294,11 +294,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
+;   mov x6, x0
-;   mov x6, x8
+;   mov x4, x6
-;   ldp x0, x1, [x6, #32]
+;   ldp x0, x1, [x4, #32]
-;   mov x7, x8
+;   mov x5, x6
-;   stp x0, x1, [x7, #32]
+;   stp x0, x1, [x5, #32]
 ;   ret
 
 function %i128_32bit_sextend_simple(i32) -> i128 {
@@ -310,11 +310,11 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sxtw x6, w0
+;   sxtw x4, w0
-;   ldp x10, x1, [x6]
+;   mov x11, x0
-;   sxtw x7, w0
+;   ldp x0, x1, [x4]
-;   mov x0, x10
+;   sxtw x5, w11
-;   stp x0, x1, [x7]
+;   stp x0, x1, [x5]
 ;   ret
 
 function %i128_32bit_sextend(i64, i32) -> i128 {
@@ -328,13 +328,13 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   mov x11, x0
+;   mov x9, x0
-;   mov x7, x11
+;   mov x5, x9
-;   add x7, x7, x1, SXTW
+;   add x5, x5, x1, SXTW
-;   ldp x0, x10, [x7, #24]
+;   mov x11, x1
-;   mov x9, x11
+;   ldp x0, x1, [x5, #24]
-;   add x9, x9, x1, SXTW
+;   mov x7, x9
-;   mov x1, x10
+;   add x7, x7, x11, SXTW
-;   stp x0, x1, [x9, #24]
+;   stp x0, x1, [x7, #24]
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/arithmetic.clif

@@ -74,8 +74,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz w3, #2
+;   movz w2, #2
-;   sdiv x0, x0, x3
+;   sdiv x0, x0, x2
 ;   ret
 
 function %f8(i64, i64) -> i64 {
@@ -97,8 +97,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   orr x3, xzr, #2
+;   orr x2, xzr, #2
-;   udiv x0, x0, x3
+;   udiv x0, x0, x2
 ;   ret
 
 function %f10(i64, i64) -> i64 {
@@ -109,8 +109,8 @@ block0(v0: i64, v1: i64):
 
 ; block0:
 ;   cbnz x1, 8 ; udf
-;   sdiv x5, x0, x1
+;   sdiv x4, x0, x1
-;   msub x0, x5, x1, x0
+;   msub x0, x4, x1, x0
 ;   ret
 
 function %f11(i64, i64) -> i64 {
@@ -121,8 +121,8 @@ block0(v0: i64, v1: i64):
 
 ; block0:
 ;   cbnz x1, 8 ; udf
-;   udiv x5, x0, x1
+;   udiv x4, x0, x1
-;   msub x0, x5, x1, x0
+;   msub x0, x4, x1, x0
 ;   ret
 
 function %f12(i32, i32) -> i32 {
@@ -132,13 +132,13 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sxtw x4, w0
+;   sxtw x3, w0
-;   sxtw x6, w1
+;   sxtw x5, w1
-;   cbnz x6, 8 ; udf
+;   cbnz x5, 8 ; udf
-;   adds wzr, w6, #1
+;   adds wzr, w5, #1
-;   ccmp w4, #1, #nzcv, eq
+;   ccmp w3, #1, #nzcv, eq
 ;   b.vc 8 ; udf
-;   sdiv x0, x4, x6
+;   sdiv x0, x3, x5
 ;   ret
 
 function %f13(i32) -> i32 {
@@ -149,9 +149,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sxtw x3, w0
+;   sxtw x2, w0
-;   movz w5, #2
+;   movz w4, #2
-;   sdiv x0, x3, x5
+;   sdiv x0, x2, x4
 ;   ret
 
 function %f14(i32, i32) -> i32 {
@@ -161,10 +161,10 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   mov w4, w0
+;   mov w3, w0
-;   mov w6, w1
+;   mov w5, w1
-;   cbnz x6, 8 ; udf
+;   cbnz x5, 8 ; udf
-;   udiv x0, x4, x6
+;   udiv x0, x3, x5
 ;   ret
 
 function %f15(i32) -> i32 {
@@ -175,9 +175,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   mov w3, w0
+;   mov w2, w0
-;   orr w5, wzr, #2
+;   orr w4, wzr, #2
-;   udiv x0, x3, x5
+;   udiv x0, x2, x4
 ;   ret
 
 function %f16(i32, i32) -> i32 {
@@ -187,11 +187,11 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sxtw x4, w0
+;   sxtw x3, w0
-;   sxtw x6, w1
+;   sxtw x5, w1
-;   cbnz x6, 8 ; udf
+;   cbnz x5, 8 ; udf
-;   sdiv x9, x4, x6
+;   sdiv x8, x3, x5
-;   msub x0, x9, x6, x4
+;   msub x0, x8, x5, x3
 ;   ret
 
 function %f17(i32, i32) -> i32 {
@@ -201,11 +201,11 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   mov w4, w0
+;   mov w3, w0
-;   mov w6, w1
+;   mov w5, w1
-;   cbnz x6, 8 ; udf
+;   cbnz x5, 8 ; udf
-;   udiv x9, x4, x6
+;   udiv x8, x3, x5
-;   msub x0, x9, x6, x4
+;   msub x0, x8, x5, x3
 ;   ret
 
 function %f18(i64, i64) -> i64 {
@@ -331,8 +331,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz x3, #1
+;   movz x2, #1
-;   sub x0, xzr, x3
+;   sub x0, xzr, x2
 ;   ret
 
 function %f30(i8x16) -> i8x16 {
@@ -343,11 +343,11 @@ block0(v0: i8x16):
 }
 
 ; block0:
-;   movz x3, #1
+;   movz x2, #1
-;   and w5, w3, #7
+;   and w4, w2, #7
-;   sub x7, xzr, x5
+;   sub x6, xzr, x4
-;   dup v17.16b, w7
+;   dup v16.16b, w6
-;   ushl v0.16b, v0.16b, v17.16b
+;   ushl v0.16b, v0.16b, v16.16b
 ;   ret
 
 function %add_i128(i128, i128) -> i128 {
@@ -379,9 +379,9 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   umulh x7, x0, x2
+;   umulh x5, x0, x2
-;   madd x9, x0, x3, x7
+;   madd x7, x0, x3, x5
-;   madd x1, x1, x2, x9
+;   madd x1, x1, x2, x7
 ;   madd x0, x0, x2, xzr
 ;   ret
 
@@ -437,8 +437,8 @@ block0(v0: i32, v1: i32, v2: i32):
 }
 
 ; block0:
-;   madd w6, w1, w2, wzr
+;   madd w5, w1, w2, wzr
-;   sub w0, w6, w0
+;   sub w0, w5, w0
 ;   ret
 
 function %imul_sub_i64(i64, i64, i64) -> i64 {
@@ -449,8 +449,8 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   madd x6, x1, x2, xzr
+;   madd x5, x1, x2, xzr
-;   sub x0, x6, x0
+;   sub x0, x5, x0
 ;   ret
 
 function %srem_const (i64) -> i64 {
@@ -461,9 +461,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz w3, #2
+;   movz w2, #2
-;   sdiv x5, x0, x3
+;   sdiv x4, x0, x2
-;   msub x0, x5, x3, x0
+;   msub x0, x4, x2, x0
 ;   ret
 
 function %urem_const (i64) -> i64 {
@@ -474,9 +474,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   orr x3, xzr, #2
+;   orr x2, xzr, #2
-;   udiv x5, x0, x3
+;   udiv x4, x0, x2
-;   msub x0, x5, x3, x0
+;   msub x0, x4, x2, x0
 ;   ret
 
 function %sdiv_minus_one(i64) -> i64 {
@@ -487,9 +487,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movn x3, #0
+;   movn x2, #0
-;   adds xzr, x3, #1
+;   adds xzr, x2, #1
 ;   ccmp x0, #1, #nzcv, eq
 ;   b.vc 8 ; udf
-;   sdiv x0, x0, x3
+;   sdiv x0, x0, x2
 ;   ret
+

cranelift/filetests/filetests/isa/aarch64/bitops.clif

@@ -9,8 +9,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   rbit w3, w0
+;   rbit w2, w0
-;   lsr w0, w3, #24
+;   lsr w0, w2, #24
 ;   ret
 
 function %a(i16) -> i16 {
@@ -20,8 +20,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   rbit w3, w0
+;   rbit w2, w0
-;   lsr w0, w3, #16
+;   lsr w0, w2, #16
 ;   ret
 
 function %a(i32) -> i32 {
@@ -51,9 +51,9 @@ block0(v0: i128):
 }
 
 ; block0:
-;   rbit x5, x0
+;   mov x6, x1
-;   rbit x0, x1
+;   rbit x1, x0
-;   mov x1, x5
+;   rbit x0, x6
 ;   ret
 
 function %b(i8) -> i8 {
@@ -63,9 +63,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w3, w0
+;   uxtb w2, w0
-;   clz w5, w3
+;   clz w4, w2
-;   sub w0, w5, #24
+;   sub w0, w4, #24
 ;   ret
 
 function %b(i16) -> i16 {
@@ -75,9 +75,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   uxth w3, w0
+;   uxth w2, w0
-;   clz w5, w3
+;   clz w4, w2
-;   sub w0, w5, #16
+;   sub w0, w4, #16
 ;   ret
 
 function %b(i32) -> i32 {
@@ -107,10 +107,10 @@ block0(v0: i128):
 }
 
 ; block0:
-;   clz x5, x1
+;   clz x3, x1
-;   clz x7, x0
+;   clz x5, x0
-;   lsr x9, x5, #6
+;   lsr x7, x3, #6
-;   madd x0, x7, x9, x5
+;   madd x0, x5, x7, x3
 ;   movz w1, #0
 ;   ret
 
@@ -121,9 +121,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sxtb w3, w0
+;   sxtb w2, w0
-;   cls w5, w3
+;   cls w4, w2
-;   sub w0, w5, #24
+;   sub w0, w4, #24
 ;   ret
 
 function %c(i16) -> i16 {
@@ -133,9 +133,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sxth w3, w0
+;   sxth w2, w0
-;   cls w5, w3
+;   cls w4, w2
-;   sub w0, w5, #16
+;   sub w0, w4, #16
 ;   ret
 
 function %c(i32) -> i32 {
@@ -165,14 +165,14 @@ block0(v0: i128):
 }
 
 ; block0:
-;   cls x5, x0
+;   cls x3, x0
-;   cls x7, x1
+;   cls x5, x1
-;   eon x9, x1, x0
+;   eon x7, x1, x0
-;   lsr x11, x9, #63
+;   lsr x9, x7, #63
-;   madd x13, x5, x11, x11
+;   madd x11, x3, x9, x9
-;   subs xzr, x7, #63
+;   subs xzr, x5, #63
-;   csel x0, x13, xzr, eq
+;   csel x14, x11, xzr, eq
-;   add x0, x0, x7
+;   add x0, x14, x5
 ;   movz w1, #0
 ;   ret
 
@@ -183,9 +183,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   rbit w3, w0
+;   rbit w2, w0
-;   orr w5, w3, #8388608
+;   orr w4, w2, #8388608
-;   clz w0, w5
+;   clz w0, w4
 ;   ret
 
 function %d(i16) -> i16 {
@@ -195,9 +195,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   rbit w3, w0
+;   rbit w2, w0
-;   orr w5, w3, #32768
+;   orr w4, w2, #32768
-;   clz w0, w5
+;   clz w0, w4
 ;   ret
 
 function %d(i32) -> i32 {
@@ -207,8 +207,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   rbit w3, w0
+;   rbit w2, w0
-;   clz w0, w3
+;   clz w0, w2
 ;   ret
 
 function %d(i64) -> i64 {
@@ -217,24 +217,24 @@ block0(v0: i64):
     return v1
 }
 
+; block0:
+;   rbit x2, x0
+;   clz x0, x2
+;   ret
+
+function %d(i128) -> i128 {
+block0(v0: i128):
+    v1 = ctz v0
+    return v1
+}
+
 ; block0:
 ;   rbit x3, x0
-;   clz x0, x3
+;   rbit x5, x1
-;   ret
+;   clz x7, x3
-
-function %d(i128) -> i128 {
-block0(v0: i128):
-    v1 = ctz v0
-    return v1
-}
-
-; block0:
-;   rbit x5, x0
-;   rbit x7, x1
 ;   clz x9, x5
-;   clz x11, x7
+;   lsr x11, x7, #6
-;   lsr x13, x9, #6
+;   madd x0, x9, x11, x7
-;   madd x0, x11, x13, x9
 ;   movz w1, #0
 ;   ret
 
@@ -245,11 +245,11 @@ block0(v0: i128):
 }
 
 ; block0:
-;   fmov d6, x0
+;   fmov d4, x0
-;   mov v6.d[1], v6.d[1], x1
+;   mov v4.d[1], v4.d[1], x1
-;   cnt v17.16b, v6.16b
+;   cnt v7.16b, v4.16b
-;   addv b19, v17.16b
+;   addv b17, v7.16b
-;   umov w0, v19.b[0]
+;   umov w0, v17.b[0]
 ;   movz w1, #0
 ;   ret
 
@@ -260,10 +260,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   fmov d3, x0
+;   fmov d2, x0
-;   cnt v5.8b, v3.8b
+;   cnt v4.8b, v2.8b
-;   addv b7, v5.8b
+;   addv b6, v4.8b
-;   umov w0, v7.b[0]
+;   umov w0, v6.b[0]
 ;   ret
 
 function %d(i32) -> i32 {
@@ -273,10 +273,10 @@ block0(v0: i32):
 }
 
 ; block0:
-;   fmov s3, w0
+;   fmov s2, w0
-;   cnt v5.8b, v3.8b
+;   cnt v4.8b, v2.8b
-;   addv b7, v5.8b
+;   addv b6, v4.8b
-;   umov w0, v7.b[0]
+;   umov w0, v6.b[0]
 ;   ret
 
 function %d(i16) -> i16 {
@@ -286,10 +286,10 @@ block0(v0: i16):
 }
 
 ; block0:
-;   fmov s3, w0
+;   fmov s2, w0
-;   cnt v5.8b, v3.8b
+;   cnt v4.8b, v2.8b
-;   addp v7.8b, v5.8b, v5.8b
+;   addp v6.8b, v4.8b, v4.8b
-;   umov w0, v7.b[0]
+;   umov w0, v6.b[0]
 ;   ret
 
 function %d(i8) -> i8 {
@@ -299,9 +299,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   fmov s3, w0
+;   fmov s2, w0
-;   cnt v5.8b, v3.8b
+;   cnt v4.8b, v2.8b
-;   umov w0, v5.b[0]
+;   umov w0, v4.b[0]
 ;   ret
 
 function %sextend_i8() -> i32 {
@@ -312,8 +312,8 @@ block0:
 }
 
 ; block0:
-;   movn x1, #0
+;   movn x0, #0
-;   sxtb w0, w1
+;   sxtb w0, w0
 ;   ret
 
 function %sextend_i8() -> i32 {
@@ -324,8 +324,8 @@ block0:
 }
 
 ; block0:
-;   movn x1, #0
+;   movn x0, #0
-;   sxtb w0, w1
+;   sxtb w0, w0
 ;   ret
 
 function %bnot_i32(i32) -> i32 {
@@ -821,15 +821,15 @@ block0(v0: i128, v1: i8):
 }
 
 ; block0:
-;   lsl x6, x0, x2
+;   lsl x4, x0, x2
-;   lsl x8, x1, x2
+;   lsl x6, x1, x2
-;   orn w10, wzr, w2
+;   orn w8, wzr, w2
-;   lsr x12, x0, #1
+;   lsr x10, x0, #1
-;   lsr x14, x12, x10
+;   lsr x12, x10, x8
-;   orr x1, x8, x14
+;   orr x14, x6, x12
 ;   ands xzr, x2, #64
-;   csel x0, xzr, x6, ne
+;   csel x0, xzr, x4, ne
-;   csel x1, x6, x1, ne
+;   csel x1, x4, x14, ne
 ;   ret
 
 function %ishl_i128_i128(i128, i128) -> i128 {
@@ -839,15 +839,15 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   lsl x7, x0, x2
+;   lsl x5, x0, x2
-;   lsl x9, x1, x2
+;   lsl x7, x1, x2
-;   orn w11, wzr, w2
+;   orn w9, wzr, w2
-;   lsr x13, x0, #1
+;   lsr x11, x0, #1
-;   lsr x15, x13, x11
+;   lsr x13, x11, x9
-;   orr x1, x9, x15
+;   orr x15, x7, x13
 ;   ands xzr, x2, #64
-;   csel x0, xzr, x7, ne
+;   csel x0, xzr, x5, ne
-;   csel x1, x7, x1, ne
+;   csel x1, x5, x15, ne
 ;   ret
 
 function %ushr_i128_i8(i128, i8) -> i128 {
@@ -857,15 +857,15 @@ block0(v0: i128, v1: i8):
 }
 
 ; block0:
-;   lsr x6, x0, x2
+;   lsr x4, x0, x2
-;   lsr x8, x1, x2
+;   lsr x6, x1, x2
-;   orn w10, wzr, w2
+;   orn w8, wzr, w2
-;   lsl x12, x1, #1
+;   lsl x10, x1, #1
-;   lsl x14, x12, x10
+;   lsl x12, x10, x8
-;   orr x0, x6, x14
+;   orr x14, x4, x12
 ;   ands xzr, x2, #64
-;   csel x0, x8, x0, ne
+;   csel x0, x6, x14, ne
-;   csel x1, xzr, x8, ne
+;   csel x1, xzr, x6, ne
 ;   ret
 
 function %ushr_i128_i128(i128, i128) -> i128 {
@@ -875,15 +875,15 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   lsr x7, x0, x2
+;   lsr x5, x0, x2
-;   lsr x9, x1, x2
+;   lsr x7, x1, x2
-;   orn w11, wzr, w2
+;   orn w9, wzr, w2
-;   lsl x13, x1, #1
+;   lsl x11, x1, #1
-;   lsl x15, x13, x11
+;   lsl x13, x11, x9
-;   orr x1, x7, x15
+;   orr x15, x5, x13
 ;   ands xzr, x2, #64
-;   csel x0, x9, x1, ne
+;   csel x0, x7, x15, ne
-;   csel x1, xzr, x9, ne
+;   csel x1, xzr, x7, ne
 ;   ret
 
 function %sshr_i128_i8(i128, i8) -> i128 {
@@ -893,16 +893,16 @@ block0(v0: i128, v1: i8):
 }
 
 ; block0:
-;   lsr x6, x0, x2
+;   lsr x4, x0, x2
-;   asr x8, x1, x2
+;   asr x6, x1, x2
-;   orn w10, wzr, w2
+;   orn w8, wzr, w2
-;   lsl x12, x1, #1
+;   lsl x10, x1, #1
-;   lsl x14, x12, x10
+;   lsl x12, x10, x8
-;   asr x1, x1, #63
+;   asr x14, x1, #63
-;   orr x3, x6, x14
+;   orr x0, x4, x12
 ;   ands xzr, x2, #64
-;   csel x0, x8, x3, ne
+;   csel x0, x6, x0, ne
-;   csel x1, x1, x8, ne
+;   csel x1, x14, x6, ne
 ;   ret
 
 function %sshr_i128_i128(i128, i128) -> i128 {
@@ -912,15 +912,15 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   lsr x7, x0, x2
+;   lsr x5, x0, x2
-;   asr x9, x1, x2
+;   asr x7, x1, x2
-;   orn w11, wzr, w2
+;   orn w9, wzr, w2
-;   lsl x13, x1, #1
+;   lsl x11, x1, #1
-;   lsl x15, x13, x11
+;   lsl x13, x11, x9
-;   asr x1, x1, #63
+;   asr x15, x1, #63
-;   orr x3, x7, x15
+;   orr x1, x5, x13
 ;   ands xzr, x2, #64
-;   csel x0, x9, x3, ne
+;   csel x0, x7, x1, ne
-;   csel x1, x1, x9, ne
+;   csel x1, x15, x7, ne
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/bti.clif

@@ -33,7 +33,7 @@ block5(v5: i32):
 ; block0:
 ;   emit_island 44
 ;   subs wzr, w0, #3
-;   b.hs label1 ; csel x1, xzr, x0, hs ; csdb ; adr x15, pc+16 ; ldrsw x1, [x15, x1, uxtw #2] ; add x15, x15, x1 ; br x15 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))]
+;   b.hs label1 ; csel x15, xzr, x0, hs ; csdb ; adr x14, pc+16 ; ldrsw x15, [x14, x15, uxtw #2] ; add x14, x14, x15 ; br x14 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))]
 ; block1:
 ;   movz x5, #4
 ;   b label2
@@ -80,16 +80,17 @@ block2:
 
 ;   bti c
 ; block0:
-;   ldr x6, [x0]
+;   ldr x5, [x0]
+;   mov x8, x5
 ;   emit_island 36
 ;   subs wzr, w0, #1
-;   b.hs label1 ; csel x8, xzr, x0, hs ; csdb ; adr x7, pc+16 ; ldrsw x8, [x7, x8, uxtw #2] ; add x7, x7, x8 ; br x7 ; jt_entries [Label(MachLabel(2))]
+;   b.hs label1 ; csel x7, xzr, x0, hs ; csdb ; adr x6, pc+16 ; ldrsw x7, [x6, x7, uxtw #2] ; add x6, x6, x7 ; br x6 ; jt_entries [Label(MachLabel(2))]
 ; block1:
-;   mov x0, x6
+;   mov x0, x8
 ;   ret
 ; block2:
 ;   bti j
-;   mov x0, x6
+;   mov x0, x8
 ;   add x0, x0, #42
 ;   ret
 
@@ -105,8 +106,8 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/call-pauth.clif

@@ -14,8 +14,8 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   autiasp ; ret
 

cranelift/filetests/filetests/isa/aarch64/call.clif

@@ -14,8 +14,8 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -30,8 +30,8 @@ block0(v0: i32):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -54,8 +54,8 @@ block0(v0: i32):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -105,8 +105,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   mov x8, x0
+;   mov x9, x0
-;   mov x13, x1
+;   mov x8, x1
 ;   movz x0, #42
 ;   movz x1, #42
 ;   movz x2, #42
@@ -115,8 +115,7 @@ block0(v0: i8):
 ;   movz x5, #42
 ;   movz x6, #42
 ;   movz x7, #42
-;   mov x11, x8
+;   strb w9, [x8]
-;   strb w11, [x13]
 ;   ret
 
 function %f8() {
@@ -283,8 +282,8 @@ block0(v0: i64):
 ;   mov x1, x0
 ;   movz x0, #42
 ;   movz x2, #42
-;   ldr x7, 8 ; b 12 ; data TestCase(%f11) + 0
+;   ldr x6, 8 ; b 12 ; data TestCase(%f11) + 0
-;   blr x7
+;   blr x6
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -314,8 +313,8 @@ block0(v0: i64):
 ;   mov x2, x0
 ;   movz x3, #42
 ;   movz x0, #42
-;   ldr x7, 8 ; b 12 ; data TestCase(%f12) + 0
+;   ldr x6, 8 ; b 12 ; data TestCase(%f12) + 0
-;   blr x7
+;   blr x6
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -345,8 +344,8 @@ block0(v0: i64):
 ;   mov x1, x0
 ;   movz x2, #42
 ;   movz x0, #42
-;   ldr x7, 8 ; b 12 ; data TestCase(%f13) + 0
+;   ldr x6, 8 ; b 12 ; data TestCase(%f13) + 0
-;   blr x7
+;   blr x6
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -381,12 +380,12 @@ block0(v0: i128, v1: i64):
 ;   mov x4, x0
 ;   str x1, [sp, #8]
 ;   mov x5, x1
-;   ldr x12, 8 ; b 12 ; data TestCase(%f14) + 0
+;   ldr x10, 8 ; b 12 ; data TestCase(%f14) + 0
 ;   mov x0, x4
 ;   mov x2, x4
 ;   mov x1, x5
 ;   mov x3, x5
-;   blr x12
+;   blr x10
 ;   add sp, sp, #16
 ;   virtual_sp_offset_adjust -16
 ;   ldp fp, lr, [sp], #16
@@ -423,12 +422,12 @@ block0(v0: i128, v1: i64):
 ;   mov x4, x0
 ;   str x1, [sp, #8]
 ;   mov x5, x1
-;   ldr x12, 8 ; b 12 ; data TestCase(%f15) + 0
+;   ldr x10, 8 ; b 12 ; data TestCase(%f15) + 0
 ;   mov x0, x4
 ;   mov x2, x4
 ;   mov x1, x5
 ;   mov x3, x5
-;   blr x12
+;   blr x10
 ;   add sp, sp, #16
 ;   virtual_sp_offset_adjust -16
 ;   ldp fp, lr, [sp], #16
@@ -442,10 +441,10 @@ block0:
 }
 
 ; block0:
-;   mov x11, x0
+;   mov x6, x0
 ;   movz x0, #0
-;   movz x7, #1
+;   movz x4, #1
-;   str w7, [x11]
+;   str w4, [x6]
 ;   ret
 
 function %f17(i64 sret) {
@@ -473,8 +472,8 @@ block0(v0: i64):
 ;   mov fp, sp
 ; block0:
 ;   mov x8, x0
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/compare_zero.clif

@@ -57,8 +57,8 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   cmeq v3.4s, v0.4s, #0
+;   cmeq v2.4s, v0.4s, #0
-;   mvn v0.16b, v3.16b
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f2_vconst(i32x4) -> i32x4 {
@@ -69,8 +69,8 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   cmeq v3.4s, v0.4s, #0
+;   cmeq v2.4s, v0.4s, #0
-;   mvn v0.16b, v3.16b
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f3(i64x2) -> i64x2 {
@@ -82,8 +82,8 @@ block0(v0: i64x2):
 }
 
 ; block0:
-;   cmeq v3.2d, v0.2d, #0
+;   cmeq v2.2d, v0.2d, #0
-;   mvn v0.16b, v3.16b
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f3_vconst(i64x2) -> i64x2 {
@@ -94,8 +94,8 @@ block0(v0: i64x2):
 }
 
 ; block0:
-;   cmeq v3.2d, v0.2d, #0
+;   cmeq v2.2d, v0.2d, #0
-;   mvn v0.16b, v3.16b
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f4(i8x16) -> i8x16 {
@@ -337,8 +337,8 @@ block0(v0: f64x2):
 }
 
 ; block0:
-;   fcmeq v3.2d, v0.2d, #0.0
+;   fcmeq v2.2d, v0.2d, #0.0
-;   mvn v0.16b, v3.16b
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f14_vconst(f64x2) -> i64x2 {
@@ -349,8 +349,8 @@ block0(v0: f64x2):
 }
 
 ; block0:
-;   fcmeq v3.2d, v0.2d, #0.0
+;   fcmeq v2.2d, v0.2d, #0.0
-;   mvn v0.16b, v3.16b
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f15(f32x4) -> i32x4 {
@@ -362,8 +362,8 @@ block0(v0: f32x4):
 }
 
 ; block0:
-;   fcmeq v3.4s, v0.4s, #0.0
+;   fcmeq v2.4s, v0.4s, #0.0
-;   mvn v0.16b, v3.16b
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f15_vconst(f32x4) -> i32x4 {
@@ -374,8 +374,8 @@ block0(v0: f32x4):
 }
 
 ; block0:
-;   fcmeq v3.4s, v0.4s, #0.0
+;   fcmeq v2.4s, v0.4s, #0.0
-;   mvn v0.16b, v3.16b
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f16(f32x4) -> i32x4 {

cranelift/filetests/filetests/isa/aarch64/condbr.clif

@@ -45,10 +45,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, lo
+;   cset x6, lo
 ;   subs xzr, x1, x3
-;   cset x10, lt
+;   cset x9, lt
-;   csel x0, x7, x10, eq
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_ult_i128(i128, i128) -> i8 {
@@ -59,10 +59,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, lo
+;   cset x6, lo
 ;   subs xzr, x1, x3
-;   cset x10, lo
+;   cset x9, lo
-;   csel x0, x7, x10, eq
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_sle_i128(i128, i128) -> i8 {
@@ -73,10 +73,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, ls
+;   cset x6, ls
 ;   subs xzr, x1, x3
-;   cset x10, le
+;   cset x9, le
-;   csel x0, x7, x10, eq
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_ule_i128(i128, i128) -> i8 {
@@ -87,10 +87,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, ls
+;   cset x6, ls
 ;   subs xzr, x1, x3
-;   cset x10, ls
+;   cset x9, ls
-;   csel x0, x7, x10, eq
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_sgt_i128(i128, i128) -> i8 {
@@ -101,10 +101,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, hi
+;   cset x6, hi
 ;   subs xzr, x1, x3
-;   cset x10, gt
+;   cset x9, gt
-;   csel x0, x7, x10, eq
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_ugt_i128(i128, i128) -> i8 {
@@ -115,10 +115,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, hi
+;   cset x6, hi
 ;   subs xzr, x1, x3
-;   cset x10, hi
+;   cset x9, hi
-;   csel x0, x7, x10, eq
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_sge_i128(i128, i128) -> i8 {
@@ -129,10 +129,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, hs
+;   cset x6, hs
 ;   subs xzr, x1, x3
-;   cset x10, ge
+;   cset x9, ge
-;   csel x0, x7, x10, eq
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_uge_i128(i128, i128) -> i8 {
@@ -143,10 +143,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, hs
+;   cset x6, hs
 ;   subs xzr, x1, x3
-;   cset x10, hs
+;   cset x9, hs
-;   csel x0, x7, x10, eq
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %f(i64, i64) -> i64 {

cranelift/filetests/filetests/isa/aarch64/condops.clif

@@ -11,8 +11,8 @@ block0(v0: i8, v1: i8, v2: i8):
 }
 
 ; block0:
-;   uxtb w5, w0
+;   uxtb w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -25,8 +25,8 @@ block0(v0: i8, v1: i16, v2: i16):
 }
 
 ; block0:
-;   uxtb w5, w0
+;   uxtb w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -39,8 +39,8 @@ block0(v0: i8, v1: i32, v2: i32):
 }
 
 ; block0:
-;   uxtb w5, w0
+;   uxtb w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -53,8 +53,8 @@ block0(v0: i8, v1: i64, v2: i64):
 }
 
 ; block0:
-;   uxtb w5, w0
+;   uxtb w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -67,8 +67,8 @@ block0(v0: i8, v1: i128, v2: i128):
 }
 
 ; block0:
-;   uxtb w8, w0
+;   uxtb w6, w0
-;   subs wzr, w8, #42
+;   subs wzr, w6, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
@@ -82,8 +82,8 @@ block0(v0: i16, v1: i8, v2: i8):
 }
 
 ; block0:
-;   uxth w5, w0
+;   uxth w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -96,8 +96,8 @@ block0(v0: i16, v1: i16, v2: i16):
 }
 
 ; block0:
-;   uxth w5, w0
+;   uxth w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -110,8 +110,8 @@ block0(v0: i16, v1: i32, v2: i32):
 }
 
 ; block0:
-;   uxth w5, w0
+;   uxth w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -124,8 +124,8 @@ block0(v0: i16, v1: i64, v2: i64):
 }
 
 ; block0:
-;   uxth w5, w0
+;   uxth w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -138,8 +138,8 @@ block0(v0: i16, v1: i128, v2: i128):
 }
 
 ; block0:
-;   uxth w8, w0
+;   uxth w6, w0
-;   subs wzr, w8, #42
+;   subs wzr, w6, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
@@ -286,10 +286,10 @@ block0(v0: i128, v1: i8, v2: i8):
 }
 
 ; block0:
-;   movz x7, #42
+;   movz x6, #42
-;   movz w9, #0
+;   movz w8, #0
-;   subs xzr, x0, x7
+;   subs xzr, x0, x6
-;   ccmp x1, x9, #nzcv, eq
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 
@@ -303,10 +303,10 @@ block0(v0: i128, v1: i16, v2: i16):
 }
 
 ; block0:
-;   movz x7, #42
+;   movz x6, #42
-;   movz w9, #0
+;   movz w8, #0
-;   subs xzr, x0, x7
+;   subs xzr, x0, x6
-;   ccmp x1, x9, #nzcv, eq
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 
@@ -320,10 +320,10 @@ block0(v0: i128, v1: i32, v2: i32):
 }
 
 ; block0:
-;   movz x7, #42
+;   movz x6, #42
-;   movz w9, #0
+;   movz w8, #0
-;   subs xzr, x0, x7
+;   subs xzr, x0, x6
-;   ccmp x1, x9, #nzcv, eq
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 
@@ -337,10 +337,10 @@ block0(v0: i128, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x7, #42
+;   movz x6, #42
-;   movz w9, #0
+;   movz w8, #0
-;   subs xzr, x0, x7
+;   subs xzr, x0, x6
-;   ccmp x1, x9, #nzcv, eq
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 
@@ -354,10 +354,10 @@ block0(v0: i128, v1: i128, v2: i128):
 }
 
 ; block0:
-;   movz x11, #42
+;   movz x9, #42
-;   movz w13, #0
+;   movz w11, #0
-;   subs xzr, x0, x11
+;   subs xzr, x0, x9
-;   ccmp x1, x13, #nzcv, eq
+;   ccmp x1, x11, #nzcv, eq
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
@@ -371,8 +371,8 @@ block0(v0: i8, v1: i8, v2: i8):
 }
 
 ; block0:
-;   uxtb w5, w0
+;   uxtb w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -386,8 +386,8 @@ block0(v0: i8, v1: i16, v2: i16):
 }
 
 ; block0:
-;   uxtb w5, w0
+;   uxtb w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -401,8 +401,8 @@ block0(v0: i8, v1: i32, v2: i32):
 }
 
 ; block0:
-;   uxtb w5, w0
+;   uxtb w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -416,8 +416,8 @@ block0(v0: i8, v1: i64, v2: i64):
 }
 
 ; block0:
-;   uxtb w5, w0
+;   uxtb w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -431,8 +431,8 @@ block0(v0: i8, v1: i128, v2: i128):
 }
 
 ; block0:
-;   uxtb w8, w0
+;   uxtb w6, w0
-;   subs wzr, w8, #42
+;   subs wzr, w6, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   csdb
@@ -447,8 +447,8 @@ block0(v0: i16, v1: i8, v2: i8):
 }
 
 ; block0:
-;   uxth w5, w0
+;   uxth w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -462,8 +462,8 @@ block0(v0: i16, v1: i16, v2: i16):
 }
 
 ; block0:
-;   uxth w5, w0
+;   uxth w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -477,8 +477,8 @@ block0(v0: i16, v1: i32, v2: i32):
 }
 
 ; block0:
-;   uxth w5, w0
+;   uxth w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -492,8 +492,8 @@ block0(v0: i16, v1: i64, v2: i64):
 }
 
 ; block0:
-;   uxth w5, w0
+;   uxth w4, w0
-;   subs wzr, w5, #42
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -507,8 +507,8 @@ block0(v0: i16, v1: i128, v2: i128):
 }
 
 ; block0:
-;   uxth w8, w0
+;   uxth w6, w0
-;   subs wzr, w8, #42
+;   subs wzr, w6, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   csdb
@@ -666,10 +666,10 @@ block0(v0: i128, v1: i8, v2: i8):
 }
 
 ; block0:
-;   movz x7, #42
+;   movz x6, #42
-;   movz w9, #0
+;   movz w8, #0
-;   subs xzr, x0, x7
+;   subs xzr, x0, x6
-;   ccmp x1, x9, #nzcv, eq
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
@@ -684,10 +684,10 @@ block0(v0: i128, v1: i16, v2: i16):
 }
 
 ; block0:
-;   movz x7, #42
+;   movz x6, #42
-;   movz w9, #0
+;   movz w8, #0
-;   subs xzr, x0, x7
+;   subs xzr, x0, x6
-;   ccmp x1, x9, #nzcv, eq
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
@@ -702,10 +702,10 @@ block0(v0: i128, v1: i32, v2: i32):
 }
 
 ; block0:
-;   movz x7, #42
+;   movz x6, #42
-;   movz w9, #0
+;   movz w8, #0
-;   subs xzr, x0, x7
+;   subs xzr, x0, x6
-;   ccmp x1, x9, #nzcv, eq
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
@@ -720,10 +720,10 @@ block0(v0: i128, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x7, #42
+;   movz x6, #42
-;   movz w9, #0
+;   movz w8, #0
-;   subs xzr, x0, x7
+;   subs xzr, x0, x6
-;   ccmp x1, x9, #nzcv, eq
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
@@ -738,10 +738,10 @@ block0(v0: i128, v1: i128, v2: i128):
 }
 
 ; block0:
-;   movz x11, #42
+;   movz x9, #42
-;   movz w13, #0
+;   movz w11, #0
-;   subs xzr, x0, x11
+;   subs xzr, x0, x9
-;   ccmp x1, x13, #nzcv, eq
+;   ccmp x1, x11, #nzcv, eq
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   csdb
@@ -755,8 +755,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w3, w0
+;   uxtb w2, w0
-;   subs wzr, w3, #42
+;   subs wzr, w2, #42
 ;   cset x0, eq
 ;   ret
 
@@ -767,9 +767,9 @@ block0(v0: i8, v1: i8, v2: i8):
 }
 
 ; block0:
-;   and w5, w1, w0
+;   and w4, w1, w0
-;   bic w7, w2, w0
+;   bic w6, w2, w0
-;   orr w0, w5, w7
+;   orr w0, w4, w6
 ;   ret
 
 function %i(i8, i8, i8) -> i8 {

cranelift/filetests/filetests/isa/aarch64/constants.clif

@@ -224,8 +224,8 @@ block0:
 }
 
 ; block0:
-;   movz x2, #16457, LSL #48
+;   movz x1, #16457, LSL #48
-;   fmov d0, x2
+;   fmov d0, x1
 ;   ret
 
 function %f() -> f32 {
@@ -235,8 +235,8 @@ block0:
 }
 
 ; block0:
-;   movz x2, #16968, LSL #16
+;   movz x1, #16968, LSL #16
-;   fmov s0, w2
+;   fmov s0, w1
 ;   ret
 
 function %f() -> f64 {

cranelift/filetests/filetests/isa/aarch64/dynamic-simd-narrow.clif

@@ -15,9 +15,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v4.4h, w0
+;   dup v3.4h, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
+;   mov v3.d[1], v3.d[1], v3.d[0]
-;   sqxtn v0.8b, v4.8h
+;   sqxtn v0.8b, v3.8h
 ;   ret
 
 function %snarrow_i16x8(i16) -> i8x16 {
@@ -34,9 +34,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v6.8h, w0
+;   dup v5.8h, w0
-;   sqxtn v0.8b, v6.8h
+;   sqxtn v0.8b, v5.8h
-;   sqxtn2 v0.16b, v0.16b, v6.8h
+;   sqxtn2 v0.16b, v0.16b, v5.8h
 ;   ret
 
 function %snarrow_i32x2(i32) -> i16x4 {
@@ -53,9 +53,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v4.2s, w0
+;   dup v3.2s, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
+;   mov v3.d[1], v3.d[1], v3.d[0]
-;   sqxtn v0.4h, v4.4s
+;   sqxtn v0.4h, v3.4s
 ;   ret
 
 function %snarrow_i32x4(i32) -> i16x8 {
@@ -72,9 +72,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v6.4s, w0
+;   dup v5.4s, w0
-;   sqxtn v0.4h, v6.4s
+;   sqxtn v0.4h, v5.4s
-;   sqxtn2 v0.8h, v0.8h, v6.4s
+;   sqxtn2 v0.8h, v0.8h, v5.4s
 ;   ret
 
 function %snarrow_i64x2(i64) -> i32x4 {
@@ -91,9 +91,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   dup v6.2d, x0
+;   dup v5.2d, x0
-;   sqxtn v0.2s, v6.2d
+;   sqxtn v0.2s, v5.2d
-;   sqxtn2 v0.4s, v0.4s, v6.2d
+;   sqxtn2 v0.4s, v0.4s, v5.2d
 ;   ret
 
 function %unarrow_i16x4(i16) -> i8x8 {
@@ -110,9 +110,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v4.4h, w0
+;   dup v3.4h, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
+;   mov v3.d[1], v3.d[1], v3.d[0]
-;   sqxtun v0.8b, v4.8h
+;   sqxtun v0.8b, v3.8h
 ;   ret
 
 function %unarrow_i16x8(i16) -> i8x16 {
@@ -129,9 +129,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v6.8h, w0
+;   dup v5.8h, w0
-;   sqxtun v0.8b, v6.8h
+;   sqxtun v0.8b, v5.8h
-;   sqxtun2 v0.16b, v0.16b, v6.8h
+;   sqxtun2 v0.16b, v0.16b, v5.8h
 ;   ret
 
 function %unarrow_i32x2(i32) -> i16x4 {
@@ -148,9 +148,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v4.2s, w0
+;   dup v3.2s, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
+;   mov v3.d[1], v3.d[1], v3.d[0]
-;   sqxtun v0.4h, v4.4s
+;   sqxtun v0.4h, v3.4s
 ;   ret
 
 function %unarrow_i32x4(i32) -> i16x8 {
@@ -167,9 +167,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v6.4s, w0
+;   dup v5.4s, w0
-;   sqxtun v0.4h, v6.4s
+;   sqxtun v0.4h, v5.4s
-;   sqxtun2 v0.8h, v0.8h, v6.4s
+;   sqxtun2 v0.8h, v0.8h, v5.4s
 ;   ret
 
 function %unarrow_i64x2(i64) -> i32x4 {
@@ -186,9 +186,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   dup v6.2d, x0
+;   dup v5.2d, x0
-;   sqxtun v0.2s, v6.2d
+;   sqxtun v0.2s, v5.2d
-;   sqxtun2 v0.4s, v0.4s, v6.2d
+;   sqxtun2 v0.4s, v0.4s, v5.2d
 ;   ret
 
 function %uunarrow_i16x4(i16) -> i8x8 {
@@ -205,9 +205,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v4.4h, w0
+;   dup v3.4h, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
+;   mov v3.d[1], v3.d[1], v3.d[0]
-;   uqxtn v0.8b, v4.8h
+;   uqxtn v0.8b, v3.8h
 ;   ret
 
 function %uunarrow_i16x8(i16) -> i8x16 {
@@ -224,9 +224,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v6.8h, w0
+;   dup v5.8h, w0
-;   uqxtn v0.8b, v6.8h
+;   uqxtn v0.8b, v5.8h
-;   uqxtn2 v0.16b, v0.16b, v6.8h
+;   uqxtn2 v0.16b, v0.16b, v5.8h
 ;   ret
 
 function %uunarrow_i32x2(i32) -> i16x4 {
@@ -243,9 +243,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v4.2s, w0
+;   dup v3.2s, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
+;   mov v3.d[1], v3.d[1], v3.d[0]
-;   uqxtn v0.4h, v4.4s
+;   uqxtn v0.4h, v3.4s
 ;   ret
 
 function %uunarrow_i32x4(i32) -> i16x8 {
@@ -262,9 +262,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v6.4s, w0
+;   dup v5.4s, w0
-;   uqxtn v0.4h, v6.4s
+;   uqxtn v0.4h, v5.4s
-;   uqxtn2 v0.8h, v0.8h, v6.4s
+;   uqxtn2 v0.8h, v0.8h, v5.4s
 ;   ret
 
 function %uunarrow_i64x2(i64) -> i32x4 {
@@ -281,8 +281,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   dup v6.2d, x0
+;   dup v5.2d, x0
-;   uqxtn v0.2s, v6.2d
+;   uqxtn v0.2s, v5.2d
-;   uqxtn2 v0.4s, v0.4s, v6.2d
+;   uqxtn2 v0.4s, v0.4s, v5.2d
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/dynamic-simd-neon.clif

@@ -14,9 +14,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   dup v7.16b, w0
+;   dup v6.16b, w0
-;   dup v16.16b, w1
+;   dup v7.16b, w1
-;   add v0.16b, v7.16b, v16.16b
+;   add v0.16b, v6.16b, v7.16b
 ;   ret
 
 function %i16x8_splat_add(i16, i16) -> i16x8 {
@@ -32,9 +32,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   dup v7.8h, w0
+;   dup v6.8h, w0
-;   dup v16.8h, w1
+;   dup v7.8h, w1
-;   add v0.8h, v7.8h, v16.8h
+;   add v0.8h, v6.8h, v7.8h
 ;   ret
 
 function %i32x4_splat_mul(i32, i32) -> i32x4 {
@@ -50,9 +50,9 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   dup v7.4s, w0
+;   dup v6.4s, w0
-;   dup v16.4s, w1
+;   dup v7.4s, w1
-;   mul v0.4s, v7.4s, v16.4s
+;   mul v0.4s, v6.4s, v7.4s
 ;   ret
 
 function %i64x2_splat_sub(i64, i64) -> i64x2 {
@@ -68,9 +68,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   dup v7.2d, x0
+;   dup v6.2d, x0
-;   dup v16.2d, x1
+;   dup v7.2d, x1
-;   sub v0.2d, v7.2d, v16.2d
+;   sub v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f32x4_splat_add(f32, f32) -> f32x4 {
@@ -86,9 +86,9 @@ block0(v0: f32, v1: f32):
 }
 
 ; block0:
-;   dup v7.4s, v0.s[0]
+;   dup v6.4s, v0.s[0]
-;   dup v16.4s, v1.s[0]
+;   dup v7.4s, v1.s[0]
-;   fadd v0.4s, v7.4s, v16.4s
+;   fadd v0.4s, v6.4s, v7.4s
 ;   ret
 
 function %f64x2_splat_sub(f64, f64) -> f64x2 {
@@ -104,9 +104,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v7.2d, v0.d[0]
+;   dup v6.2d, v0.d[0]
-;   dup v16.2d, v1.d[0]
+;   dup v7.2d, v1.d[0]
-;   fsub v0.2d, v7.2d, v16.2d
+;   fsub v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f64x2_splat_mul(f64, f64) -> f64x2 {
@@ -122,9 +122,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v7.2d, v0.d[0]
+;   dup v6.2d, v0.d[0]
-;   dup v16.2d, v1.d[0]
+;   dup v7.2d, v1.d[0]
-;   fmul v0.2d, v7.2d, v16.2d
+;   fmul v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f64x2_splat_div(f64, f64) -> f64x2 {
@@ -140,9 +140,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v7.2d, v0.d[0]
+;   dup v6.2d, v0.d[0]
-;   dup v16.2d, v1.d[0]
+;   dup v7.2d, v1.d[0]
-;   fdiv v0.2d, v7.2d, v16.2d
+;   fdiv v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f64x2_splat_min(f64, f64) -> f64x2 {
@@ -158,9 +158,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v7.2d, v0.d[0]
+;   dup v6.2d, v0.d[0]
-;   dup v16.2d, v1.d[0]
+;   dup v7.2d, v1.d[0]
-;   fmin v0.2d, v7.2d, v16.2d
+;   fmin v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f64x2_splat_max(f64, f64) -> f64x2 {
@@ -176,9 +176,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v7.2d, v0.d[0]
+;   dup v6.2d, v0.d[0]
-;   dup v16.2d, v1.d[0]
+;   dup v7.2d, v1.d[0]
-;   fmax v0.2d, v7.2d, v16.2d
+;   fmax v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f64x2_splat_min_pseudo(f64, f64) -> f64x2 {
@@ -194,10 +194,10 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v16.2d, v0.d[0]
+;   dup v7.2d, v0.d[0]
-;   dup v17.2d, v1.d[0]
+;   dup v16.2d, v1.d[0]
-;   fcmgt v0.2d, v16.2d, v17.2d
+;   fcmgt v0.2d, v7.2d, v16.2d
-;   bsl v0.16b, v0.16b, v17.16b, v16.16b
+;   bsl v0.16b, v0.16b, v16.16b, v7.16b
 ;   ret
 
 function %f64x2_splat_max_pseudo(f64, f64) -> f64x2 {
@@ -213,9 +213,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v16.2d, v0.d[0]
+;   dup v7.2d, v0.d[0]
-;   dup v17.2d, v1.d[0]
+;   dup v16.2d, v1.d[0]
-;   fcmgt v0.2d, v17.2d, v16.2d
+;   fcmgt v0.2d, v16.2d, v7.2d
-;   bsl v0.16b, v0.16b, v17.16b, v16.16b
+;   bsl v0.16b, v0.16b, v16.16b, v7.16b
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/dynamic-simd-widen.clif

@@ -15,8 +15,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   dup v5.16b, w0
+;   dup v4.16b, w0
-;   sxtl2 v0.8h, v5.16b
+;   sxtl2 v0.8h, v4.16b
 ;   ret
 
 function %swidenhigh_i16x8(i16) -> i32x4 {
@@ -33,8 +33,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v5.8h, w0
+;   dup v4.8h, w0
-;   sxtl2 v0.4s, v5.8h
+;   sxtl2 v0.4s, v4.8h
 ;   ret
 
 function %swidenhigh_i32x4(i32) -> i64x2 {
@@ -51,8 +51,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v5.4s, w0
+;   dup v4.4s, w0
-;   sxtl2 v0.2d, v5.4s
+;   sxtl2 v0.2d, v4.4s
 ;   ret
 
 function %swidenlow_i8x16(i8) -> i16x8 {
@@ -69,8 +69,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   dup v5.16b, w0
+;   dup v4.16b, w0
-;   sxtl v0.8h, v5.8b
+;   sxtl v0.8h, v4.8b
 ;   ret
 
 function %swidenlow_i16x8(i16) -> i32x4 {
@@ -87,8 +87,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v5.8h, w0
+;   dup v4.8h, w0
-;   sxtl v0.4s, v5.4h
+;   sxtl v0.4s, v4.4h
 ;   ret
 
 function %swidenlow_i32x4(i32) -> i64x2 {
@@ -105,6 +105,7 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v5.4s, w0
+;   dup v4.4s, w0
-;   sxtl v0.2d, v5.2s
+;   sxtl v0.2d, v4.2s
 ;   ret
+

cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif

@@ -80,8 +80,8 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #16
 ; block0:
-;   mov x3, sp
+;   mov x2, sp
-;   ldr q0, [x3]
+;   ldr q0, [x2]
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret

cranelift/filetests/filetests/isa/aarch64/extend-op.clif

@@ -11,8 +11,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sxtb x4, w0
+;   sxtb x3, w0
-;   add x0, x4, #42
+;   add x0, x3, #42
 ;   ret
 
 function %f2(i8, i64) -> i64 {

cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif

@@ -9,8 +9,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w3, w0
+;   uxtb w2, w0
-;   ucvtf s0, w3
+;   ucvtf s0, w2
 ;   ret
 
 function u0:0(i8) -> f64 {
@@ -20,8 +20,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w3, w0
+;   uxtb w2, w0
-;   ucvtf d0, w3
+;   ucvtf d0, w2
 ;   ret
 
 function u0:0(i16) -> f32 {
@@ -31,8 +31,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   uxth w3, w0
+;   uxth w2, w0
-;   ucvtf s0, w3
+;   ucvtf s0, w2
 ;   ret
 
 function u0:0(i16) -> f64 {
@@ -42,8 +42,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   uxth w3, w0
+;   uxth w2, w0
-;   ucvtf d0, w3
+;   ucvtf d0, w2
 ;   ret
 
 function u0:0(f32) -> i8 {
@@ -55,12 +55,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
+;   fmov s4, #-1
-;   fcmp s0, s5
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #17280, LSL #16
+;   movz x9, #17280, LSL #16
-;   fmov s18, w10
+;   fmov s17, w9
-;   fcmp s0, s18
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
@@ -74,12 +74,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
+;   fmov d4, #-1
-;   fcmp d0, d5
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16496, LSL #48
+;   movz x9, #16496, LSL #48
-;   fmov d18, x10
+;   fmov d17, x9
-;   fcmp d0, d18
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
@@ -93,12 +93,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
+;   fmov s4, #-1
-;   fcmp s0, s5
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #18304, LSL #16
+;   movz x9, #18304, LSL #16
-;   fmov s18, w10
+;   fmov s17, w9
-;   fcmp s0, s18
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
@@ -112,12 +112,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
+;   fmov d4, #-1
-;   fcmp d0, d5
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16624, LSL #48
+;   movz x9, #16624, LSL #48
-;   fmov d18, x10
+;   fmov d17, x9
-;   fcmp d0, d18
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret

cranelift/filetests/filetests/isa/aarch64/fcvt.clif

@@ -8,8 +8,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sxtb w3, w0
+;   sxtb w2, w0
-;   scvtf s0, w3
+;   scvtf s0, w2
 ;   ret
 
 function %f2(i16) -> f32 {
@@ -19,8 +19,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sxth w3, w0
+;   sxth w2, w0
-;   scvtf s0, w3
+;   scvtf s0, w2
 ;   ret
 
 function %f3(i32) -> f32 {
@@ -50,8 +50,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sxtb w3, w0
+;   sxtb w2, w0
-;   scvtf d0, w3
+;   scvtf d0, w2
 ;   ret
 
 function %f6(i16) -> f64 {
@@ -61,8 +61,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sxth w3, w0
+;   sxth w2, w0
-;   scvtf d0, w3
+;   scvtf d0, w2
 ;   ret
 
 function %f7(i32) -> f64 {
@@ -92,8 +92,8 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   sxtl v3.2d, v0.2s
+;   sxtl v2.2d, v0.2s
-;   scvtf v0.2d, v3.2d
+;   scvtf v0.2d, v2.2d
 ;   ret
 
 function %f10(i8, i16, i32, i64) -> f32 {
@@ -109,15 +109,15 @@ block0(v0: i8, v1: i16, v2: i32, v3: i64):
 }
 
 ; block0:
-;   uxtb w13, w0
+;   uxtb w12, w0
-;   ucvtf s23, w13
+;   ucvtf s22, w12
-;   uxth w13, w1
+;   uxth w12, w1
-;   ucvtf s24, w13
+;   ucvtf s23, w12
-;   ucvtf s22, w2
+;   ucvtf s21, w2
-;   ucvtf s25, x3
+;   ucvtf s24, x3
-;   fadd s23, s23, s24
+;   fadd s22, s22, s23
-;   fadd s22, s23, s22
+;   fadd s21, s22, s21
-;   fadd s0, s22, s25
+;   fadd s0, s21, s24
 ;   ret
 
 function %f11(i32x4) -> f64x2 {
@@ -128,8 +128,8 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   uxtl v4.2d, v0.2s
+;   uxtl v3.2d, v0.2s
-;   ucvtf v0.2d, v4.2d
+;   ucvtf v0.2d, v3.2d
 ;   ret
 
 function %f12(i32x4) -> f32x4 {
@@ -151,12 +151,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
+;   fmov s4, #-1
-;   fcmp s0, s5
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #20352, LSL #16
+;   movz x9, #20352, LSL #16
-;   fmov s18, w10
+;   fmov s17, w9
-;   fcmp s0, s18
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
@@ -170,12 +170,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
+;   fmov s4, #-1
-;   fcmp s0, s5
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #24448, LSL #16
+;   movz x9, #24448, LSL #16
-;   fmov s18, w10
+;   fmov s17, w9
-;   fcmp s0, s18
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, s0
 ;   ret
@@ -189,12 +189,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
+;   fmov d4, #-1
-;   fcmp d0, d5
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16880, LSL #48
+;   movz x9, #16880, LSL #48
-;   fmov d18, x10
+;   fmov d17, x9
-;   fcmp d0, d18
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
@@ -208,12 +208,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
+;   fmov d4, #-1
-;   fcmp d0, d5
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #17392, LSL #48
+;   movz x9, #17392, LSL #48
-;   fmov d18, x10
+;   fmov d17, x9
-;   fcmp d0, d18
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, d0
 ;   ret
@@ -267,13 +267,13 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   movz x6, #52992, LSL #16
+;   movz x5, #52992, LSL #16
-;   fmov s6, w6
+;   fmov s5, w5
-;   fcmp s0, s6
+;   fcmp s0, s5
 ;   b.ge 8 ; udf
-;   movz x12, #20224, LSL #16
+;   movz x11, #20224, LSL #16
-;   fmov s20, w12
+;   fmov s19, w11
-;   fcmp s0, s20
+;   fcmp s0, s19
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, s0
 ;   ret
@@ -287,13 +287,13 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   movz x6, #57088, LSL #16
+;   movz x5, #57088, LSL #16
-;   fmov s6, w6
+;   fmov s5, w5
-;   fcmp s0, s6
+;   fcmp s0, s5
 ;   b.ge 8 ; udf
-;   movz x12, #24320, LSL #16
+;   movz x11, #24320, LSL #16
-;   fmov s20, w12
+;   fmov s19, w11
-;   fcmp s0, s20
+;   fcmp s0, s19
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, s0
 ;   ret
@@ -307,12 +307,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   ldr d5, pc+8 ; b 12 ; data.f64 -2147483649
+;   ldr d4, pc+8 ; b 12 ; data.f64 -2147483649
-;   fcmp d0, d5
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16864, LSL #48
+;   movz x9, #16864, LSL #48
-;   fmov d18, x10
+;   fmov d17, x9
-;   fcmp d0, d18
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, d0
 ;   ret
@@ -326,13 +326,13 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   movz x6, #50144, LSL #48
+;   movz x5, #50144, LSL #48
-;   fmov d6, x6
+;   fmov d5, x5
-;   fcmp d0, d6
+;   fcmp d0, d5
 ;   b.ge 8 ; udf
-;   movz x12, #17376, LSL #48
+;   movz x11, #17376, LSL #48
-;   fmov d20, x12
+;   fmov d19, x11
-;   fcmp d0, d20
+;   fcmp d0, d19
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, d0
 ;   ret
@@ -404,10 +404,10 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvtzu w3, s0
+;   fcvtzu w2, s0
-;   movz w5, #255
+;   movz w4, #255
-;   subs wzr, w3, w5
+;   subs wzr, w2, w4
-;   csel x0, x5, x3, hi
+;   csel x0, x4, x2, hi
 ;   ret
 
 function %f32(f32) -> i8 {
@@ -417,13 +417,13 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvtzs w3, s0
+;   fcvtzs w2, s0
-;   movz w5, #127
+;   movz w4, #127
-;   movn x7, #127
+;   movn x6, #127
-;   subs wzr, w3, w5
+;   subs wzr, w2, w4
-;   csel x10, x5, x3, gt
+;   csel x9, x4, x2, gt
-;   subs wzr, w10, w7
+;   subs wzr, w9, w6
-;   csel x0, x7, x10, lt
+;   csel x0, x6, x9, lt
 ;   ret
 
 function %f33(f32) -> i16 {
@@ -433,10 +433,10 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvtzu w3, s0
+;   fcvtzu w2, s0
-;   movz w5, #65535
+;   movz w4, #65535
-;   subs wzr, w3, w5
+;   subs wzr, w2, w4
-;   csel x0, x5, x3, hi
+;   csel x0, x4, x2, hi
 ;   ret
 
 function %f34(f32) -> i16 {
@@ -446,13 +446,13 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvtzs w3, s0
+;   fcvtzs w2, s0
-;   movz w5, #32767
+;   movz w4, #32767
-;   movn x7, #32767
+;   movn x6, #32767
-;   subs wzr, w3, w5
+;   subs wzr, w2, w4
-;   csel x10, x5, x3, gt
+;   csel x9, x4, x2, gt
-;   subs wzr, w10, w7
+;   subs wzr, w9, w6
-;   csel x0, x7, x10, lt
+;   csel x0, x6, x9, lt
 ;   ret
 
 function %f35(f64) -> i8 {
@@ -462,10 +462,10 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvtzu w3, d0
+;   fcvtzu w2, d0
-;   movz w5, #255
+;   movz w4, #255
-;   subs wzr, w3, w5
+;   subs wzr, w2, w4
-;   csel x0, x5, x3, hi
+;   csel x0, x4, x2, hi
 ;   ret
 
 function %f36(f64) -> i8 {
@@ -475,13 +475,13 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvtzs w3, d0
+;   fcvtzs w2, d0
-;   movz w5, #127
+;   movz w4, #127
-;   movn x7, #127
+;   movn x6, #127
-;   subs wzr, w3, w5
+;   subs wzr, w2, w4
-;   csel x10, x5, x3, gt
+;   csel x9, x4, x2, gt
-;   subs wzr, w10, w7
+;   subs wzr, w9, w6
-;   csel x0, x7, x10, lt
+;   csel x0, x6, x9, lt
 ;   ret
 
 function %f37(f64) -> i16 {
@@ -491,10 +491,10 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvtzu w3, d0
+;   fcvtzu w2, d0
-;   movz w5, #65535
+;   movz w4, #65535
-;   subs wzr, w3, w5
+;   subs wzr, w2, w4
-;   csel x0, x5, x3, hi
+;   csel x0, x4, x2, hi
 ;   ret
 
 function %f38(f64) -> i16 {
@@ -504,12 +504,12 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvtzs w3, d0
+;   fcvtzs w2, d0
-;   movz w5, #32767
+;   movz w4, #32767
-;   movn x7, #32767
+;   movn x6, #32767
-;   subs wzr, w3, w5
+;   subs wzr, w2, w4
-;   csel x10, x5, x3, gt
+;   csel x9, x4, x2, gt
-;   subs wzr, w10, w7
+;   subs wzr, w9, w6
-;   csel x0, x7, x10, lt
+;   csel x0, x6, x9, lt
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/floating-point.clif

@@ -309,8 +309,8 @@ block0(v0: f32, v1: f32):
 }
 
 ; block0:
-;   ushr v5.2s, v1.2s, #31
+;   ushr v4.2s, v1.2s, #31
-;   sli v0.2s, v0.2s, v5.2s, #31
+;   sli v0.2s, v0.2s, v4.2s, #31
 ;   ret
 
 function %f32(f64, f64) -> f64 {
@@ -320,8 +320,8 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   ushr d5, d1, #63
+;   ushr d4, d1, #63
-;   sli d0, d0, d5, #63
+;   sli d0, d0, d4, #63
 ;   ret
 
 function %f33(f32) -> i32 {
@@ -333,12 +333,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
+;   fmov s4, #-1
-;   fcmp s0, s5
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #20352, LSL #16
+;   movz x9, #20352, LSL #16
-;   fmov s18, w10
+;   fmov s17, w9
-;   fcmp s0, s18
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
@@ -352,13 +352,13 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   movz x6, #52992, LSL #16
+;   movz x5, #52992, LSL #16
-;   fmov s6, w6
+;   fmov s5, w5
-;   fcmp s0, s6
+;   fcmp s0, s5
 ;   b.ge 8 ; udf
-;   movz x12, #20224, LSL #16
+;   movz x11, #20224, LSL #16
-;   fmov s20, w12
+;   fmov s19, w11
-;   fcmp s0, s20
+;   fcmp s0, s19
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, s0
 ;   ret
@@ -372,12 +372,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
+;   fmov s4, #-1
-;   fcmp s0, s5
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #24448, LSL #16
+;   movz x9, #24448, LSL #16
-;   fmov s18, w10
+;   fmov s17, w9
-;   fcmp s0, s18
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, s0
 ;   ret
@@ -391,13 +391,13 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   movz x6, #57088, LSL #16
+;   movz x5, #57088, LSL #16
-;   fmov s6, w6
+;   fmov s5, w5
-;   fcmp s0, s6
+;   fcmp s0, s5
 ;   b.ge 8 ; udf
-;   movz x12, #24320, LSL #16
+;   movz x11, #24320, LSL #16
-;   fmov s20, w12
+;   fmov s19, w11
-;   fcmp s0, s20
+;   fcmp s0, s19
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, s0
 ;   ret
@@ -411,12 +411,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
+;   fmov d4, #-1
-;   fcmp d0, d5
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16880, LSL #48
+;   movz x9, #16880, LSL #48
-;   fmov d18, x10
+;   fmov d17, x9
-;   fcmp d0, d18
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
@@ -430,12 +430,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   ldr d5, pc+8 ; b 12 ; data.f64 -2147483649
+;   ldr d4, pc+8 ; b 12 ; data.f64 -2147483649
-;   fcmp d0, d5
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16864, LSL #48
+;   movz x9, #16864, LSL #48
-;   fmov d18, x10
+;   fmov d17, x9
-;   fcmp d0, d18
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, d0
 ;   ret
@@ -449,12 +449,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
+;   fmov d4, #-1
-;   fcmp d0, d5
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #17392, LSL #48
+;   movz x9, #17392, LSL #48
-;   fmov d18, x10
+;   fmov d17, x9
-;   fcmp d0, d18
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, d0
 ;   ret
@@ -468,13 +468,13 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   movz x6, #50144, LSL #48
+;   movz x5, #50144, LSL #48
-;   fmov d6, x6
+;   fmov d5, x5
-;   fcmp d0, d6
+;   fcmp d0, d5
 ;   b.ge 8 ; udf
-;   movz x12, #17376, LSL #48
+;   movz x11, #17376, LSL #48
-;   fmov d20, x12
+;   fmov d19, x11
-;   fcmp d0, d20
+;   fcmp d0, d19
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, d0
 ;   ret
@@ -776,9 +776,9 @@ block0(v0: f32x4, v1: f32x4, v2: f32x4):
 }
 
 ; block0:
-;   mov v5.16b, v2.16b
+;   mov v5.16b, v0.16b
-;   fmla v5.4s, v5.4s, v0.4s, v1.4s
+;   mov v0.16b, v2.16b
-;   mov v0.16b, v5.16b
+;   fmla v0.4s, v0.4s, v5.4s, v1.4s
 ;   ret
 
 function %f71(f32x2, f32x2, f32x2) -> f32x2 {
@@ -788,9 +788,9 @@ block0(v0: f32x2, v1: f32x2, v2: f32x2):
 }
 
 ; block0:
-;   mov v5.16b, v2.16b
+;   mov v5.16b, v0.16b
-;   fmla v5.2s, v5.2s, v0.2s, v1.2s
+;   mov v0.16b, v2.16b
-;   mov v0.16b, v5.16b
+;   fmla v0.2s, v0.2s, v5.2s, v1.2s
 ;   ret
 
 function %f72(f64x2, f64x2, f64x2) -> f64x2 {
@@ -800,9 +800,9 @@ block0(v0: f64x2, v1: f64x2, v2: f64x2):
 }
 
 ; block0:
-;   mov v5.16b, v2.16b
+;   mov v5.16b, v0.16b
-;   fmla v5.2d, v5.2d, v0.2d, v1.2d
+;   mov v0.16b, v2.16b
-;   mov v0.16b, v5.16b
+;   fmla v0.2d, v0.2d, v5.2d, v1.2d
 ;   ret
 
 function %f73(f32x2, f32x2) -> f32x2 {
@@ -812,8 +812,8 @@ block0(v0: f32x2, v1: f32x2):
 }
 
 ; block0:
-;   ushr v5.2s, v1.2s, #31
+;   ushr v4.2s, v1.2s, #31
-;   sli v0.2s, v0.2s, v5.2s, #31
+;   sli v0.2s, v0.2s, v4.2s, #31
 ;   ret
 
 function %f74(f32x4, f32x4) -> f32x4 {
@@ -823,8 +823,8 @@ block0(v0: f32x4, v1: f32x4):
 }
 
 ; block0:
-;   ushr v5.4s, v1.4s, #31
+;   ushr v4.4s, v1.4s, #31
-;   sli v0.4s, v0.4s, v5.4s, #31
+;   sli v0.4s, v0.4s, v4.4s, #31
 ;   ret
 
 function %f75(f64x2, f64x2) -> f64x2 {
@@ -834,6 +834,7 @@ block0(v0: f64x2, v1: f64x2):
 }
 
 ; block0:
-;   ushr v5.2d, v1.2d, #63
+;   ushr v4.2d, v1.2d, #63
-;   sli v0.2d, v0.2d, v5.2d, #63
+;   sli v0.2d, v0.2d, v4.2d, #63
 ;   ret
+

cranelift/filetests/filetests/isa/aarch64/heap_addr.clif

@@ -14,16 +14,16 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   mov w9, w1
+;   mov w8, w1
-;   ldr x10, [x0]
+;   ldr x9, [x0]
-;   mov x10, x10
+;   mov x9, x9
-;   subs xzr, x9, x10
+;   subs xzr, x8, x9
 ;   b.ls label1 ; b label2
 ; block1:
-;   add x11, x0, x1, UXTW
+;   add x10, x0, x1, UXTW
-;   movz x12, #0
+;   movz x11, #0
-;   subs xzr, x9, x10
+;   subs xzr, x8, x9
-;   csel x0, x12, x11, hi
+;   csel x0, x11, x10, hi
 ;   csdb
 ;   ret
 ; block2:
@@ -39,14 +39,14 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   mov w7, w1
+;   mov w6, w1
-;   subs xzr, x7, #65536
+;   subs xzr, x6, #65536
 ;   b.ls label1 ; b label2
 ; block1:
-;   add x9, x0, x1, UXTW
+;   add x8, x0, x1, UXTW
-;   movz x8, #0
+;   movz x7, #0
-;   subs xzr, x7, #65536
+;   subs xzr, x6, #65536
-;   csel x0, x8, x9, hi
+;   csel x0, x7, x8, hi
 ;   csdb
 ;   ret
 ; block2:

cranelift/filetests/filetests/isa/aarch64/i128-bmask.clif

@@ -8,8 +8,8 @@ block0(v0: i128):
 }
 
 ; block0:
-;   orr x5, x0, x1
+;   orr x3, x0, x1
-;   subs xzr, x5, #0
+;   subs xzr, x3, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret
@@ -21,8 +21,8 @@ block0(v0: i128):
 }
 
 ; block0:
-;   orr x4, x0, x1
+;   orr x3, x0, x1
-;   subs xzr, x4, #0
+;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
 
@@ -33,8 +33,8 @@ block0(v0: i128):
 }
 
 ; block0:
-;   orr x4, x0, x1
+;   orr x3, x0, x1
-;   subs xzr, x4, #0
+;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
 
@@ -45,8 +45,8 @@ block0(v0: i128):
 }
 
 ; block0:
-;   orr x4, x0, x1
+;   orr x3, x0, x1
-;   subs xzr, x4, #0
+;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
 
@@ -57,8 +57,8 @@ block0(v0: i128):
 }
 
 ; block0:
-;   orr x4, x0, x1
+;   orr x3, x0, x1
-;   subs xzr, x4, #0
+;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
 
@@ -93,8 +93,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   and w4, w0, #65535
+;   and w2, w0, #65535
-;   subs wzr, w4, #0
+;   subs wzr, w2, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret
@@ -106,8 +106,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   and w4, w0, #255
+;   and w2, w0, #255
-;   subs wzr, w4, #0
+;   subs wzr, w2, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret

cranelift/filetests/filetests/isa/aarch64/iabs.clif

@@ -79,9 +79,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sxtb w3, w0
+;   sxtb w2, w0
-;   subs wzr, w3, #0
+;   subs wzr, w2, #0
-;   csneg x0, x3, x3, gt
+;   csneg x0, x2, x2, gt
 ;   ret
 
 function %f9(i16) -> i16 {
@@ -91,9 +91,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sxth w3, w0
+;   sxth w2, w0
-;   subs wzr, w3, #0
+;   subs wzr, w2, #0
-;   csneg x0, x3, x3, gt
+;   csneg x0, x2, x2, gt
 ;   ret
 
 function %f10(i32) -> i32 {

cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif

@@ -14,10 +14,10 @@ block0:
 }
 
 ; block0:
-;   movz x1, #56780
+;   movz x0, #56780
-;   uxth w3, w1
+;   uxth w2, w0
-;   movz x5, #56780
+;   movz x4, #56780
-;   subs wzr, w3, w5, UXTH
+;   subs wzr, w2, w4, UXTH
 ;   cset x0, ne
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/jumptable.clif

@@ -32,7 +32,7 @@ block5(v5: i32):
 ; block0:
 ;   emit_island 44
 ;   subs wzr, w0, #3
-;   b.hs label1 ; csel x1, xzr, x0, hs ; csdb ; adr x15, pc+16 ; ldrsw x1, [x15, x1, uxtw #2] ; add x15, x15, x1 ; br x15 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))]
+;   b.hs label1 ; csel x15, xzr, x0, hs ; csdb ; adr x14, pc+16 ; ldrsw x15, [x14, x15, uxtw #2] ; add x14, x14, x15 ; br x14 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))]
 ; block1:
 ;   movz x5, #4
 ;   b label2
@@ -56,3 +56,4 @@ block5(v5: i32):
 ; block9:
 ;   add w0, w0, w5
 ;   ret
+

cranelift/filetests/filetests/isa/aarch64/prologue.clif

@@ -82,6 +82,7 @@ block0(v0: f64):
 ;   stp d10, d11, [sp, #-16]!
 ;   stp d8, d9, [sp, #-16]!
 ; block0:
+;   fadd d23, d0, d0
 ;   fadd d24, d0, d0
 ;   fadd d25, d0, d0
 ;   fadd d26, d0, d0
@@ -104,7 +105,7 @@ block0(v0: f64):
 ;   fadd d20, d0, d0
 ;   fadd d21, d0, d0
 ;   fadd d22, d0, d0
-;   fadd d23, d0, d0
+;   fadd d15, d0, d0
 ;   fadd d8, d0, d0
 ;   fadd d9, d0, d0
 ;   fadd d10, d0, d0
@@ -112,38 +113,37 @@ block0(v0: f64):
 ;   fadd d12, d0, d0
 ;   fadd d13, d0, d0
 ;   fadd d14, d0, d0
-;   fadd d15, d0, d0
+;   fadd d23, d0, d23
-;   fadd d24, d0, d24
-;   fadd d25, d25, d26
-;   fadd d26, d27, d28
-;   fadd d27, d29, d30
-;   fadd d28, d31, d1
-;   fadd d29, d2, d3
-;   fadd d30, d4, d5
-;   fadd d31, d6, d7
-;   fadd d0, d16, d17
-;   fadd d1, d18, d19
-;   fadd d2, d20, d21
-;   fadd d3, d22, d23
-;   fadd d4, d8, d9
-;   fadd d5, d10, d11
-;   fadd d6, d12, d13
-;   fadd d7, d14, d15
 ;   fadd d24, d24, d25
 ;   fadd d25, d26, d27
 ;   fadd d26, d28, d29
 ;   fadd d27, d30, d31
-;   fadd d28, d0, d1
+;   fadd d28, d1, d2
-;   fadd d29, d2, d3
+;   fadd d29, d3, d4
-;   fadd d30, d4, d5
+;   fadd d30, d5, d6
-;   fadd d31, d6, d7
+;   fadd d31, d7, d16
-;   fadd d24, d24, d25
+;   fadd d0, d17, d18
-;   fadd d25, d26, d27
+;   fadd d1, d19, d20
-;   fadd d26, d28, d29
+;   fadd d2, d21, d22
-;   fadd d27, d30, d31
+;   fadd d3, d15, d8
-;   fadd d24, d24, d25
+;   fadd d4, d9, d10
-;   fadd d25, d26, d27
+;   fadd d5, d11, d12
-;   fadd d0, d24, d25
+;   fadd d6, d13, d14
+;   fadd d23, d23, d24
+;   fadd d24, d25, d26
+;   fadd d25, d27, d28
+;   fadd d26, d29, d30
+;   fadd d27, d31, d0
+;   fadd d28, d1, d2
+;   fadd d29, d3, d4
+;   fadd d30, d5, d6
+;   fadd d23, d23, d24
+;   fadd d24, d25, d26
+;   fadd d25, d27, d28
+;   fadd d26, d29, d30
+;   fadd d23, d23, d24
+;   fadd d24, d25, d26
+;   fadd d0, d23, d24
 ;   ldp d8, d9, [sp], #16
 ;   ldp d10, d11, [sp], #16
 ;   ldp d12, d13, [sp], #16
@@ -200,9 +200,10 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
-;   stp x19, x21, [sp, #-16]!
+;   stp x21, x27, [sp, #-16]!
 ; block0:
-;   add x6, x0, x0
+;   add x5, x0, x0
+;   add x6, x0, x5
 ;   add x7, x0, x6
 ;   add x8, x0, x7
 ;   add x9, x0, x8
@@ -216,29 +217,29 @@ block0(v0: i64):
 ;   add x2, x0, x1
 ;   add x3, x0, x2
 ;   add x4, x0, x3
-;   add x5, x0, x4
+;   add x27, x0, x4
-;   add x28, x0, x5
+;   add x28, x0, x27
 ;   add x21, x0, x28
-;   add x19, x0, x21
+;   add x5, x0, x5
-;   add x6, x0, x6
-;   add x7, x7, x8
-;   add x8, x9, x10
-;   add x9, x11, x12
-;   add x10, x13, x14
-;   add x11, x15, x1
-;   add x12, x2, x3
-;   add x13, x4, x5
-;   add x14, x28, x21
-;   add x6, x19, x6
-;   add x7, x7, x8
-;   add x8, x9, x10
-;   add x9, x11, x12
-;   add x10, x13, x14
 ;   add x6, x6, x7
 ;   add x7, x8, x9
-;   add x6, x10, x6
+;   add x8, x10, x11
-;   add x0, x7, x6
+;   add x9, x12, x13
-;   ldp x19, x21, [sp], #16
+;   add x10, x14, x15
+;   add x11, x1, x2
+;   add x12, x3, x4
+;   add x13, x27, x28
+;   add x5, x21, x5
+;   add x6, x6, x7
+;   add x7, x8, x9
+;   add x8, x10, x11
+;   add x9, x12, x13
+;   add x5, x5, x6
+;   add x6, x7, x8
+;   add x5, x9, x5
+;   add x0, x6, x5
+;   ldp x21, x27, [sp], #16
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+

cranelift/filetests/filetests/isa/aarch64/reftypes.clif

@@ -69,28 +69,28 @@ block3(v7: r64, v8: r64):
 ; block0:
 ;   str x0, [sp, #8]
 ;   str x1, [sp, #16]
-;   ldr x3, 8 ; b 12 ; data TestCase(%f) + 0
+;   ldr x1, 8 ; b 12 ; data TestCase(%f) + 0
-;   blr x3
+;   blr x1
-;   mov x2, sp
+;   mov x15, sp
-;   ldr x9, [sp, #8]
+;   ldr x6, [sp, #8]
-;   str x9, [x2]
+;   str x6, [x15]
-;   uxtb w3, w0
+;   uxtb w0, w0
-;   cbz x3, label1 ; b label3
+;   cbz x0, label1 ; b label3
 ; block1:
 ;   b label2
 ; block2:
-;   mov x1, x9
+;   mov x1, x6
 ;   ldr x0, [sp, #16]
 ;   b label5
 ; block3:
 ;   b label4
 ; block4:
-;   mov x0, x9
+;   mov x0, x6
 ;   ldr x1, [sp, #16]
 ;   b label5
 ; block5:
-;   mov x4, sp
+;   mov x2, sp
-;   ldr x2, [x4]
+;   ldr x2, [x2]
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret

cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif

@@ -13,28 +13,28 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   orr x7, xzr, #128
+;   orr x5, xzr, #128
-;   sub x9, x7, x2
+;   sub x7, x5, x2
-;   lsr x11, x0, x2
+;   lsr x9, x0, x2
-;   lsr x13, x1, x2
+;   lsr x11, x1, x2
-;   orn w15, wzr, w2
+;   orn w13, wzr, w2
-;   lsl x3, x1, #1
+;   lsl x15, x1, #1
-;   lsl x3, x3, x15
+;   lsl x3, x15, x13
-;   orr x5, x11, x3
+;   orr x3, x9, x3
 ;   ands xzr, x2, #64
-;   csel x8, x13, x5, ne
+;   csel x6, x11, x3, ne
-;   csel x10, xzr, x13, ne
+;   csel x8, xzr, x11, ne
-;   lsl x12, x0, x9
+;   lsl x10, x0, x7
-;   lsl x14, x1, x9
+;   lsl x12, x1, x7
-;   orn w1, wzr, w9
+;   orn w14, wzr, w7
-;   lsr x2, x0, #1
+;   lsr x0, x0, #1
-;   lsr x4, x2, x1
+;   lsr x2, x0, x14
-;   orr x6, x14, x4
+;   orr x4, x12, x2
-;   ands xzr, x9, #64
+;   ands xzr, x7, #64
-;   csel x9, xzr, x12, ne
+;   csel x7, xzr, x10, ne
-;   csel x11, x12, x6, ne
+;   csel x9, x10, x4, ne
-;   orr x1, x10, x11
+;   orr x1, x8, x9
-;   orr x0, x8, x9
+;   orr x0, x6, x7
 ;   ret
 
 function %f0(i64, i64) -> i64 {
@@ -64,13 +64,13 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   uxth w4, w0
+;   uxth w3, w0
-;   and w6, w1, #15
+;   and w5, w1, #15
-;   sub w8, w6, #16
+;   sub w7, w5, #16
-;   sub w10, wzr, w8
+;   sub w9, wzr, w7
-;   lsr w12, w4, w6
+;   lsr w11, w3, w5
-;   lsl w14, w4, w10
+;   lsl w13, w3, w9
-;   orr w0, w14, w12
+;   orr w0, w13, w11
 ;   ret
 
 function %f3(i8, i8) -> i8 {
@@ -80,13 +80,13 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   uxtb w4, w0
+;   uxtb w3, w0
-;   and w6, w1, #7
+;   and w5, w1, #7
-;   sub w8, w6, #8
+;   sub w7, w5, #8
-;   sub w10, wzr, w8
+;   sub w9, wzr, w7
-;   lsr w12, w4, w6
+;   lsr w11, w3, w5
-;   lsl w14, w4, w10
+;   lsl w13, w3, w9
-;   orr w0, w14, w12
+;   orr w0, w13, w11
 ;   ret
 
 function %i128_rotl(i128, i128) -> i128 {
@@ -96,28 +96,28 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   orr x7, xzr, #128
+;   orr x5, xzr, #128
-;   sub x9, x7, x2
+;   sub x7, x5, x2
-;   lsl x11, x0, x2
+;   lsl x9, x0, x2
-;   lsl x13, x1, x2
+;   lsl x11, x1, x2
-;   orn w15, wzr, w2
+;   orn w13, wzr, w2
-;   lsr x3, x0, #1
+;   lsr x15, x0, #1
-;   lsr x3, x3, x15
+;   lsr x3, x15, x13
-;   orr x5, x13, x3
+;   orr x3, x11, x3
 ;   ands xzr, x2, #64
-;   csel x8, xzr, x11, ne
+;   csel x6, xzr, x9, ne
-;   csel x10, x11, x5, ne
+;   csel x8, x9, x3, ne
-;   lsr x12, x0, x9
+;   lsr x10, x0, x7
-;   lsr x14, x1, x9
+;   lsr x12, x1, x7
-;   orn w0, wzr, w9
+;   orn w14, wzr, w7
-;   lsl x2, x1, #1
+;   lsl x0, x1, #1
-;   lsl x4, x2, x0
+;   lsl x2, x0, x14
-;   orr x6, x12, x4
+;   orr x4, x10, x2
-;   ands xzr, x9, #64
+;   ands xzr, x7, #64
-;   csel x9, x14, x6, ne
+;   csel x7, x12, x4, ne
-;   csel x11, xzr, x14, ne
+;   csel x9, xzr, x12, ne
-;   orr x0, x8, x9
+;   orr x0, x6, x7
-;   orr x1, x10, x11
+;   orr x1, x8, x9
 ;   ret
 
 function %f4(i64, i64) -> i64 {
@@ -127,8 +127,8 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   sub x4, xzr, x1
+;   sub x3, xzr, x1
-;   ror x0, x0, x4
+;   ror x0, x0, x3
 ;   ret
 
 function %f5(i32, i32) -> i32 {
@@ -138,8 +138,8 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sub w4, wzr, w1
+;   sub w3, wzr, w1
-;   ror w0, w0, w4
+;   ror w0, w0, w3
 ;   ret
 
 function %f6(i16, i16) -> i16 {
@@ -149,14 +149,14 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   sub w4, wzr, w1
+;   sub w3, wzr, w1
-;   uxth w6, w0
+;   uxth w5, w0
-;   and w8, w4, #15
+;   and w7, w3, #15
-;   sub w10, w8, #16
+;   sub w9, w7, #16
-;   sub w12, wzr, w10
+;   sub w11, wzr, w9
-;   lsr w14, w6, w8
+;   lsr w13, w5, w7
-;   lsl w0, w6, w12
+;   lsl w15, w5, w11
-;   orr w0, w0, w14
+;   orr w0, w15, w13
 ;   ret
 
 function %f7(i8, i8) -> i8 {
@@ -166,14 +166,14 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   sub w4, wzr, w1
+;   sub w3, wzr, w1
-;   uxtb w6, w0
+;   uxtb w5, w0
-;   and w8, w4, #7
+;   and w7, w3, #7
-;   sub w10, w8, #8
+;   sub w9, w7, #8
-;   sub w12, wzr, w10
+;   sub w11, wzr, w9
-;   lsr w14, w6, w8
+;   lsr w13, w5, w7
-;   lsl w0, w6, w12
+;   lsl w15, w5, w11
-;   orr w0, w0, w14
+;   orr w0, w15, w13
 ;   ret
 
 function %f8(i64, i64) -> i64 {
@@ -203,9 +203,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   uxth w4, w0
+;   uxth w3, w0
-;   and w6, w1, #15
+;   and w5, w1, #15
-;   lsr w0, w4, w6
+;   lsr w0, w3, w5
 ;   ret
 
 function %f11(i8, i8) -> i8 {
@@ -215,9 +215,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   uxtb w4, w0
+;   uxtb w3, w0
-;   and w6, w1, #7
+;   and w5, w1, #7
-;   lsr w0, w4, w6
+;   lsr w0, w3, w5
 ;   ret
 
 function %f12(i64, i64) -> i64 {
@@ -247,8 +247,8 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   and w4, w1, #15
+;   and w3, w1, #15
-;   lsl w0, w0, w4
+;   lsl w0, w0, w3
 ;   ret
 
 function %f15(i8, i8) -> i8 {
@@ -258,8 +258,8 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   and w4, w1, #7
+;   and w3, w1, #7
-;   lsl w0, w0, w4
+;   lsl w0, w0, w3
 ;   ret
 
 function %f16(i64, i64) -> i64 {
@@ -289,9 +289,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   sxth w4, w0
+;   sxth w3, w0
-;   and w6, w1, #15
+;   and w5, w1, #15
-;   asr w0, w4, w6
+;   asr w0, w3, w5
 ;   ret
 
 function %f19(i8, i8) -> i8 {
@@ -301,9 +301,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   sxtb w4, w0
+;   sxtb w3, w0
-;   and w6, w1, #7
+;   and w5, w1, #7
-;   asr w0, w4, w6
+;   asr w0, w3, w5
 ;   ret
 
 function %f20(i64) -> i64 {
@@ -347,10 +347,10 @@ block0(v0: i16):
 }
 
 ; block0:
-;   uxth w3, w0
+;   uxth w2, w0
-;   lsr w5, w3, #6
+;   lsr w4, w2, #6
-;   lsl w7, w3, #10
+;   lsl w6, w2, #10
-;   orr w0, w7, w5
+;   orr w0, w6, w4
 ;   ret
 
 function %f24(i8) -> i8 {
@@ -361,10 +361,10 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w3, w0
+;   uxtb w2, w0
-;   lsr w5, w3, #5
+;   lsr w4, w2, #5
-;   lsl w7, w3, #3
+;   lsl w6, w2, #3
-;   orr w0, w7, w5
+;   orr w0, w6, w4
 ;   ret
 
 function %f25(i64) -> i64 {

cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif

@@ -69,13 +69,13 @@ block0(v0: i64x2, v1: i64x2):
 }
 
 ; block0:
-;   movz x5, #1
+;   movz x4, #1
-;   dup v5.2d, x5
+;   dup v4.2d, x4
-;   orr v16.16b, v0.16b, v1.16b
+;   orr v7.16b, v0.16b, v1.16b
-;   and v18.16b, v16.16b, v5.16b
+;   and v17.16b, v7.16b, v4.16b
-;   ushr v20.2d, v0.2d, #1
+;   ushr v19.2d, v0.2d, #1
-;   ushr v22.2d, v1.2d, #1
+;   ushr v21.2d, v1.2d, #1
-;   add v24.2d, v20.2d, v22.2d
+;   add v23.2d, v19.2d, v21.2d
-;   add v0.2d, v18.2d, v24.2d
+;   add v0.2d, v17.2d, v23.2d
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif

@@ -103,9 +103,9 @@ block0:
 
 ; block0:
 ;   movi v0.16b, #0
+;   movi v3.16b, #0
 ;   movi v4.16b, #0
-;   movi v5.16b, #0
+;   bsl v0.16b, v0.16b, v3.16b, v4.16b
-;   bsl v0.16b, v0.16b, v4.16b, v5.16b
 ;   ret
 
 function %vselect_i16x8(i16x8, i16x8, i16x8) -> i16x8 {
@@ -146,10 +146,10 @@ block0(v0: i32):
 }
 
 ; block0:
-;   ldr q6, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
+;   ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
-;   and w4, w0, #7
+;   and w3, w0, #7
-;   dup v7.16b, w4
+;   dup v6.16b, w3
-;   sshl v0.16b, v6.16b, v7.16b
+;   sshl v0.16b, v5.16b, v6.16b
 ;   ret
 
 function %ushr_i8x16_imm() -> i8x16 {
@@ -161,12 +161,12 @@ block0:
 }
 
 ; block0:
-;   ldr q6, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
+;   ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
-;   movz x2, #1
+;   movz x1, #1
-;   and w4, w2, #7
+;   and w3, w1, #7
-;   sub x6, xzr, x4
+;   sub x5, xzr, x3
-;   dup v16.16b, w6
+;   dup v7.16b, w5
-;   ushl v0.16b, v6.16b, v16.16b
+;   ushl v0.16b, v5.16b, v7.16b
 ;   ret
 
 function %sshr_i8x16(i32) -> i8x16 {
@@ -177,11 +177,11 @@ block0(v0: i32):
 }
 
 ; block0:
-;   ldr q7, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
+;   ldr q6, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
-;   and w4, w0, #7
+;   and w3, w0, #7
-;   sub x6, xzr, x4
+;   sub x5, xzr, x3
-;   dup v16.16b, w6
+;   dup v7.16b, w5
-;   sshl v0.16b, v7.16b, v16.16b
+;   sshl v0.16b, v6.16b, v7.16b
 ;   ret
 
 function %sshr_i8x16_imm(i8x16, i32) -> i8x16 {
@@ -191,11 +191,11 @@ block0(v0: i8x16, v1: i32):
 }
 
 ; block0:
-;   movz x4, #3
+;   movz x3, #3
-;   and w6, w4, #7
+;   and w5, w3, #7
-;   sub x8, xzr, x6
+;   sub x7, xzr, x5
-;   dup v18.16b, w8
+;   dup v17.16b, w7
-;   sshl v0.16b, v0.16b, v18.16b
+;   sshl v0.16b, v0.16b, v17.16b
 ;   ret
 
 function %sshr_i64x2(i64x2, i32) -> i64x2 {
@@ -205,9 +205,9 @@ block0(v0: i64x2, v1: i32):
 }
 
 ; block0:
-;   and w4, w0, #63
+;   and w3, w0, #63
-;   sub x6, xzr, x4
+;   sub x5, xzr, x3
-;   dup v16.2d, x6
+;   dup v7.2d, x5
-;   sshl v0.2d, v0.2d, v16.2d
+;   sshl v0.2d, v0.2d, v7.2d
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif

@@ -9,8 +9,8 @@ block0(v0: i32x4, v1: i32x4):
 }
 
 ; block0:
-;   cmeq v4.4s, v0.4s, v1.4s
+;   cmeq v3.4s, v0.4s, v1.4s
-;   mvn v0.16b, v4.16b
+;   mvn v0.16b, v3.16b
 ;   ret
 
 function %icmp_ugt_i32x4(i32x4, i32x4) -> i32x4 {

cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif

@@ -14,10 +14,10 @@ block0:
 
 ; block0:
 ;   movi v30.16b, #0
-;   movz x5, #1
+;   movz x4, #1
-;   fmov s31, w5
+;   fmov s31, w4
-;   ldr q4, pc+8 ; b 20 ; data.f128 0x11000000000000000000000000000000
+;   ldr q3, pc+8 ; b 20 ; data.f128 0x11000000000000000000000000000000
-;   tbl v0.16b, { v30.16b, v31.16b }, v4.16b
+;   tbl v0.16b, { v30.16b, v31.16b }, v3.16b
 ;   ret
 
 function %shuffle_same_ssa_value() -> i8x16 {
@@ -28,11 +28,11 @@ block0:
 }
 
 ; block0:
-;   movz x4, #1
+;   movz x3, #1
-;   fmov s31, w4
+;   fmov s31, w3
-;   ldr q3, pc+8 ; b 20 ; data.f128 0x13000000000000000000000000000000
+;   ldr q2, pc+8 ; b 20 ; data.f128 0x13000000000000000000000000000000
 ;   mov v30.16b, v31.16b
-;   tbl v0.16b, { v30.16b, v31.16b }, v3.16b
+;   tbl v0.16b, { v30.16b, v31.16b }, v2.16b
 ;   ret
 
 function %swizzle() -> i8x16 {
@@ -44,9 +44,9 @@ block0:
 }
 
 ; block0:
+;   ldr q2, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
 ;   ldr q3, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
-;   ldr q4, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
+;   tbl v0.16b, { v2.16b }, v3.16b
-;   tbl v0.16b, { v3.16b }, v4.16b
 ;   ret
 
 function %splat_i8(i8) -> i8x16 {
@@ -98,8 +98,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldr w4, [x0]
+;   ldr w3, [x0]
-;   fmov s0, w4
+;   fmov s0, w3
 ;   ret
 
 function %load32_zero_int(i32) -> i32x4 {

cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif

@@ -19,9 +19,9 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   umaxp v3.4s, v0.4s, v0.4s
+;   umaxp v2.4s, v0.4s, v0.4s
-;   mov x5, v3.d[0]
+;   mov x4, v2.d[0]
-;   subs xzr, x5, #0
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -32,9 +32,9 @@ block0(v0: i64x2):
 }
 
 ; block0:
-;   cmeq v3.2d, v0.2d, #0
+;   cmeq v2.2d, v0.2d, #0
-;   addp v5.2d, v3.2d, v3.2d
+;   addp v4.2d, v2.2d, v2.2d
-;   fcmp d5, d5
+;   fcmp d4, d4
 ;   cset x0, eq
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/simd-narrow.clif

@@ -9,9 +9,9 @@ block0(v0: i16x4, v1: i16x4):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
+;   mov v3.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
+;   mov v3.d[1], v3.d[1], v1.d[0]
-;   sqxtn v0.8b, v4.8h
+;   sqxtn v0.8b, v3.8h
 ;   ret
 
 function %snarrow_i16x8(i16x8, i16x8) -> i8x16 {
@@ -32,9 +32,9 @@ block0(v0: i32x2, v1: i32x2):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
+;   mov v3.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
+;   mov v3.d[1], v3.d[1], v1.d[0]
-;   sqxtn v0.4h, v4.4s
+;   sqxtn v0.4h, v3.4s
 ;   ret
 
 function %snarrow_i32x4(i32x4, i32x4) -> i16x8 {
@@ -66,9 +66,9 @@ block0(v0: i16x4, v1: i16x4):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
+;   mov v3.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
+;   mov v3.d[1], v3.d[1], v1.d[0]
-;   sqxtun v0.8b, v4.8h
+;   sqxtun v0.8b, v3.8h
 ;   ret
 
 function %unarrow_i16x8(i16x8, i16x8) -> i8x16 {
@@ -89,9 +89,9 @@ block0(v0: i32x2, v1: i32x2):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
+;   mov v3.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
+;   mov v3.d[1], v3.d[1], v1.d[0]
-;   sqxtun v0.4h, v4.4s
+;   sqxtun v0.4h, v3.4s
 ;   ret
 
 function %unarrow_i32x4(i32x4, i32x4) -> i16x8 {
@@ -123,9 +123,9 @@ block0(v0: i16x4, v1: i16x4):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
+;   mov v3.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
+;   mov v3.d[1], v3.d[1], v1.d[0]
-;   uqxtn v0.8b, v4.8h
+;   uqxtn v0.8b, v3.8h
 ;   ret
 
 function %uunarrow_i16x8(i16x8, i16x8) -> i8x16 {
@@ -146,9 +146,9 @@ block0(v0: i32x2, v1: i32x2):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
+;   mov v3.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
+;   mov v3.d[1], v3.d[1], v1.d[0]
-;   uqxtn v0.4h, v4.4s
+;   uqxtn v0.4h, v3.4s
 ;   ret
 
 function %uunarrow_i32x4(i32x4, i32x4) -> i16x8 {

cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif

@@ -9,9 +9,9 @@ block0(v0: i8x8):
 }
 
 ; block0:
-;   uminv b3, v0.8b
+;   uminv b2, v0.8b
-;   mov x5, v3.d[0]
+;   mov x4, v2.d[0]
-;   subs xzr, x5, #0
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -22,9 +22,9 @@ block0(v0: i8x16):
 }
 
 ; block0:
-;   uminv b3, v0.16b
+;   uminv b2, v0.16b
-;   mov x5, v3.d[0]
+;   mov x4, v2.d[0]
-;   subs xzr, x5, #0
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -35,9 +35,9 @@ block0(v0: i16x4):
 }
 
 ; block0:
-;   uminv h3, v0.4h
+;   uminv h2, v0.4h
-;   mov x5, v3.d[0]
+;   mov x4, v2.d[0]
-;   subs xzr, x5, #0
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -48,9 +48,9 @@ block0(v0: i16x8):
 }
 
 ; block0:
-;   uminv h3, v0.8h
+;   uminv h2, v0.8h
-;   mov x5, v3.d[0]
+;   mov x4, v2.d[0]
-;   subs xzr, x5, #0
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -61,9 +61,9 @@ block0(v0: i32x2):
 }
 
 ; block0:
-;   mov x3, v0.d[0]
+;   mov x2, v0.d[0]
-;   subs xzr, xzr, x3, LSR 32
+;   subs xzr, xzr, x2, LSR 32
-;   ccmp w3, #0, #nZcv, ne
+;   ccmp w2, #0, #nZcv, ne
 ;   cset x0, ne
 ;   ret
 
@@ -74,9 +74,9 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   uminv s3, v0.4s
+;   uminv s2, v0.4s
-;   mov x5, v3.d[0]
+;   mov x4, v2.d[0]
-;   subs xzr, x5, #0
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -87,9 +87,9 @@ block0(v0: i64x2):
 }
 
 ; block0:
-;   cmeq v3.2d, v0.2d, #0
+;   cmeq v2.2d, v0.2d, #0
-;   addp v5.2d, v3.2d, v3.2d
+;   addp v4.2d, v2.2d, v2.2d
-;   fcmp d5, d5
+;   fcmp d4, d4
 ;   cset x0, eq
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/simd.clif

@@ -10,9 +10,9 @@ block0:
 }
 
 ; block0:
-;   movz x2, #1
+;   movz x1, #1
-;   movk x2, x2, #1, LSL #48
+;   movk x1, x1, #1, LSL #48
-;   dup v0.2d, x2
+;   dup v0.2d, x1
 ;   ret
 
 function %f2() -> i16x8 {
@@ -24,8 +24,8 @@ block0:
 }
 
 ; block0:
-;   movz x2, #42679
+;   movz x1, #42679
-;   dup v0.8h, w2
+;   dup v0.8h, w1
 ;   ret
 
 function %f4(i32, i8x16, i8x16) -> i8x16 {
@@ -74,9 +74,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   ldrb w7, [x0]
+;   ldrb w5, [x0]
 ;   ld1r { v0.16b }, [x1]
-;   dup v1.16b, w7
+;   dup v1.16b, w5
 ;   ret
 
 function %f8(i64, i64) -> i8x16, i8x16 {
@@ -88,9 +88,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   ldrb w7, [x0]
+;   ldrb w5, [x0]
-;   dup v0.16b, w7
+;   dup v0.16b, w5
-;   dup v1.16b, w7
+;   dup v1.16b, w5
 ;   ret
 
 function %f9() -> i32x2 {

cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif

@@ -10,9 +10,9 @@ block0:
 }
 
 ; block0:
-;   movz x1, #1
+;   movz x0, #1
-;   movk x1, x1, #1, LSL #48
+;   movk x0, x0, #1, LSL #48
-;   fmov d0, x1
+;   fmov d0, x0
 ;   ret
 
 function %f2() -> i32x4 {
@@ -23,8 +23,8 @@ block0:
 }
 
 ; block0:
-;   movz x1, #42679
+;   movz x0, #42679
-;   fmov s0, w1
+;   fmov s0, w0
 ;   ret
 
 function %f3() -> f32x4 {
@@ -35,8 +35,8 @@ block0:
 }
 
 ; block0:
-;   fmov s1, #1
+;   fmov s0, #1
-;   fmov s0, s1
+;   fmov s0, s0
 ;   ret
 
 function %f4() -> f64x2 {
@@ -47,7 +47,7 @@ block0:
 }
 
 ; block0:
-;   fmov d1, #1
+;   fmov d0, #1
-;   fmov d0, d1
+;   fmov d0, d0
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/stack.clif

@@ -53,8 +53,8 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #16
 ; block0:
-;   mov x2, sp
+;   mov x1, sp
-;   ldr x0, [x2]
+;   ldr x0, [x1]
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -74,8 +74,8 @@ block0:
 ;   movk w16, w16, #1, LSL #16
 ;   sub sp, sp, x16, UXTX
 ; block0:
-;   mov x2, sp
+;   mov x1, sp
-;   ldr x0, [x2]
+;   ldr x0, [x1]
 ;   movz w16, #34480
 ;   movk w16, w16, #1, LSL #16
 ;   add sp, sp, x16, UXTX
@@ -284,142 +284,142 @@ block0(v0: i8):
 ;   sub sp, sp, #1152
 ; block0:
 ;   str x0, [sp, #1000]
-;   movz x8, #2
+;   movz x6, #2
-;   add x11, x8, #1
+;   add x9, x6, #1
-;   str x11, [sp, #1136]
+;   str x9, [sp, #1136]
-;   movz x8, #4
+;   movz x6, #4
-;   add x12, x8, #3
+;   add x10, x6, #3
-;   str x12, [sp, #1128]
+;   str x10, [sp, #1128]
-;   movz x8, #6
+;   movz x6, #6
-;   add x13, x8, #5
+;   add x11, x6, #5
-;   str x13, [sp, #1120]
+;   str x11, [sp, #1120]
-;   movz x8, #8
+;   movz x6, #8
-;   add x14, x8, #7
+;   add x12, x6, #7
-;   str x14, [sp, #1112]
+;   str x12, [sp, #1112]
-;   movz x8, #10
+;   movz x6, #10
-;   add x15, x8, #9
+;   add x13, x6, #9
-;   str x15, [sp, #1104]
+;   str x13, [sp, #1104]
-;   movz x8, #12
+;   movz x6, #12
-;   add x1, x8, #11
+;   add x14, x6, #11
-;   str x1, [sp, #1096]
+;   str x14, [sp, #1096]
-;   movz x8, #14
+;   movz x6, #14
-;   add x2, x8, #13
+;   add x15, x6, #13
-;   str x2, [sp, #1088]
+;   str x15, [sp, #1088]
-;   movz x8, #16
+;   movz x6, #16
-;   add x3, x8, #15
+;   add x1, x6, #15
-;   str x3, [sp, #1080]
+;   str x1, [sp, #1080]
-;   movz x8, #18
+;   movz x6, #18
-;   add x4, x8, #17
+;   add x2, x6, #17
-;   str x4, [sp, #1072]
+;   str x2, [sp, #1072]
-;   movz x8, #20
+;   movz x6, #20
-;   add x5, x8, #19
+;   add x3, x6, #19
-;   str x5, [sp, #1064]
+;   str x3, [sp, #1064]
-;   movz x8, #22
+;   movz x6, #22
-;   add x6, x8, #21
+;   add x4, x6, #21
-;   str x6, [sp, #1056]
+;   str x4, [sp, #1056]
-;   movz x8, #24
+;   movz x6, #24
-;   add x7, x8, #23
+;   add x5, x6, #23
-;   str x7, [sp, #1048]
+;   str x5, [sp, #1048]
-;   movz x8, #26
+;   movz x6, #26
-;   add x8, x8, #25
+;   add x6, x6, #25
-;   str x8, [sp, #1040]
+;   str x6, [sp, #1040]
-;   movz x8, #28
+;   movz x6, #28
-;   add x9, x8, #27
+;   add x7, x6, #27
-;   str x9, [sp, #1032]
+;   str x7, [sp, #1032]
-;   movz x8, #30
+;   movz x6, #30
-;   add x26, x8, #29
+;   add x24, x6, #29
-;   str x26, [sp, #1024]
+;   str x24, [sp, #1024]
-;   movz x8, #32
+;   movz x6, #32
-;   add x27, x8, #31
+;   add x25, x6, #31
-;   str x27, [sp, #1016]
+;   str x25, [sp, #1016]
-;   movz x8, #34
+;   movz x6, #34
-;   add x28, x8, #33
+;   add x26, x6, #33
-;   movz x8, #36
+;   movz x6, #36
-;   add x21, x8, #35
+;   add x27, x6, #35
-;   str x21, [sp, #1008]
+;   str x27, [sp, #1008]
-;   movz x8, #38
+;   movz x6, #38
-;   add x21, x8, #37
+;   add x27, x6, #37
-;   movz x8, #30
+;   movz x6, #30
-;   add x19, x8, #39
+;   add x28, x6, #39
-;   movz x8, #32
+;   movz x6, #32
-;   add x20, x8, #31
+;   add x21, x6, #31
-;   movz x8, #34
+;   movz x6, #34
-;   add x22, x8, #33
+;   add x19, x6, #33
-;   movz x8, #36
+;   movz x6, #36
-;   add x23, x8, #35
+;   add x20, x6, #35
-;   movz x8, #38
+;   movz x6, #38
-;   add x24, x8, #37
+;   add x22, x6, #37
-;   movz x8, #30
+;   movz x6, #30
-;   add x25, x8, #39
+;   add x23, x6, #39
-;   movz x8, #32
+;   movz x6, #32
-;   add x0, x8, #31
+;   add x0, x6, #31
-;   movz x8, #34
+;   movz x6, #34
-;   add x10, x8, #33
+;   add x8, x6, #33
-;   movz x8, #36
+;   movz x6, #36
-;   add x11, x8, #35
+;   add x9, x6, #35
-;   movz x8, #38
+;   movz x6, #38
-;   add x12, x8, #37
+;   add x10, x6, #37
-;   movz x8, #30
+;   movz x6, #30
-;   add x13, x8, #39
+;   add x11, x6, #39
-;   movz x8, #32
+;   movz x6, #32
-;   add x14, x8, #31
+;   add x12, x6, #31
-;   movz x8, #34
+;   movz x6, #34
-;   add x15, x8, #33
+;   add x13, x6, #33
-;   movz x8, #36
+;   movz x6, #36
-;   add x1, x8, #35
+;   add x14, x6, #35
-;   movz x8, #38
+;   movz x6, #38
-;   add x2, x8, #37
+;   add x15, x6, #37
-;   ldr x3, [sp, #1136]
+;   ldr x1, [sp, #1136]
-;   add x3, x3, #39
+;   add x1, x1, #39
-;   ldr x5, [sp, #1120]
+;   ldr x3, [sp, #1120]
-;   ldr x4, [sp, #1128]
+;   ldr x2, [sp, #1128]
-;   add x4, x4, x5
+;   add x2, x2, x3
-;   ldr x5, [sp, #1104]
+;   ldr x3, [sp, #1104]
-;   ldr x8, [sp, #1112]
+;   ldr x6, [sp, #1112]
-;   add x5, x8, x5
+;   add x3, x6, x3
-;   ldr x6, [sp, #1088]
+;   ldr x4, [sp, #1088]
-;   ldr x7, [sp, #1096]
+;   ldr x5, [sp, #1096]
-;   add x6, x7, x6
+;   add x4, x5, x4
-;   ldr x7, [sp, #1072]
+;   ldr x5, [sp, #1072]
-;   ldr x8, [sp, #1080]
+;   ldr x6, [sp, #1080]
-;   add x7, x8, x7
+;   add x5, x6, x5
-;   ldr x9, [sp, #1056]
+;   ldr x7, [sp, #1056]
-;   ldr x8, [sp, #1064]
+;   ldr x6, [sp, #1064]
+;   add x6, x6, x7
+;   ldr x7, [sp, #1040]
+;   ldr x24, [sp, #1048]
+;   add x7, x24, x7
+;   ldr x24, [sp, #1024]
+;   ldr x25, [sp, #1032]
+;   add x24, x25, x24
+;   ldr x25, [sp, #1016]
+;   add x25, x25, x26
+;   ldr x26, [sp, #1008]
+;   add x26, x26, x27
+;   add x27, x28, x21
+;   add x28, x19, x20
+;   add x23, x22, x23
+;   add x8, x0, x8
+;   add x9, x9, x10
+;   add x10, x11, x12
+;   add x11, x13, x14
+;   add x12, x15, x1
+;   add x13, x2, x3
+;   add x14, x4, x5
+;   add x7, x6, x7
+;   add x15, x24, x25
+;   add x0, x26, x27
+;   add x1, x28, x23
 ;   add x8, x8, x9
-;   ldr x9, [sp, #1040]
+;   add x9, x10, x11
-;   ldr x26, [sp, #1048]
+;   add x10, x12, x13
-;   add x9, x26, x9
+;   add x7, x14, x7
-;   ldr x26, [sp, #1024]
+;   add x11, x15, x0
-;   ldr x27, [sp, #1032]
+;   add x8, x1, x8
-;   add x26, x27, x26
+;   add x9, x9, x10
-;   ldr x27, [sp, #1016]
+;   add x7, x7, x11
-;   add x27, x27, x28
+;   add x8, x8, x9
-;   ldr x28, [sp, #1008]
+;   add x1, x7, x8
-;   add x28, x28, x21
-;   add x21, x19, x20
-;   add x19, x22, x23
-;   add x25, x24, x25
-;   add x10, x0, x10
-;   add x11, x11, x12
-;   add x12, x13, x14
-;   add x13, x15, x1
-;   add x14, x2, x3
-;   add x15, x4, x5
-;   add x0, x6, x7
-;   add x9, x8, x9
-;   add x1, x26, x27
-;   add x2, x28, x21
-;   add x3, x19, x25
-;   add x10, x10, x11
-;   add x11, x12, x13
-;   add x12, x14, x15
-;   add x9, x0, x9
-;   add x13, x1, x2
-;   add x10, x3, x10
-;   add x11, x11, x12
-;   add x9, x9, x13
-;   add x10, x10, x11
-;   add x1, x9, x10
 ;   ldr x0, [sp, #1000]
 ;   add sp, sp, #1152
 ;   ldp x19, x20, [sp], #16
@@ -502,8 +502,8 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #16
 ; block0:
-;   mov x5, sp
+;   mov x3, sp
-;   ldp x0, x1, [x5]
+;   ldp x0, x1, [x3]
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -521,8 +521,8 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #32
 ; block0:
-;   add x5, sp, #32
+;   add x3, sp, #32
-;   ldp x0, x1, [x5]
+;   ldp x0, x1, [x3]
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -542,8 +542,8 @@ block0:
 ;   movk w16, w16, #1, LSL #16
 ;   sub sp, sp, x16, UXTX
 ; block0:
-;   mov x5, sp
+;   mov x3, sp
-;   ldp x0, x1, [x5]
+;   ldp x0, x1, [x3]
 ;   movz w16, #34480
 ;   movk w16, w16, #1, LSL #16
 ;   add sp, sp, x16, UXTX

cranelift/filetests/filetests/isa/aarch64/tls-elf-gd.clif

@@ -12,22 +12,21 @@ block0(v0: i32):
 
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
-;   str x25, [sp, #-16]!
+;   str x24, [sp, #-16]!
 ;   stp d14, d15, [sp, #-16]!
 ;   stp d12, d13, [sp, #-16]!
 ;   stp d10, d11, [sp, #-16]!
 ;   stp d8, d9, [sp, #-16]!
 ; block0:
-;   mov x25, x0
+;   mov x24, x0
 ;   elf_tls_get_addr x0, userextname0
-;   mov x7, x25
 ;   mov x1, x0
-;   mov x0, x7
+;   mov x0, x24
 ;   ldp d8, d9, [sp], #16
 ;   ldp d10, d11, [sp], #16
 ;   ldp d12, d13, [sp], #16
 ;   ldp d14, d15, [sp], #16
-;   ldr x25, [sp], #16
+;   ldr x24, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif

@@ -9,8 +9,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   movz x3, #127
+;   movz x2, #127
-;   adds w0, w0, w3
+;   adds w0, w0, w2
 ;   b.lo 8 ; udf
 ;   ret
 
@@ -22,8 +22,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   movz x3, #127
+;   movz x2, #127
-;   adds w0, w3, w0
+;   adds w0, w2, w0
 ;   b.lo 8 ; udf
 ;   ret
 
@@ -46,8 +46,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz x3, #127
+;   movz x2, #127
-;   adds x0, x0, x3
+;   adds x0, x0, x2
 ;   b.lo 8 ; udf
 ;   ret
 
@@ -59,8 +59,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz x3, #127
+;   movz x2, #127
-;   adds x0, x3, x0
+;   adds x0, x2, x0
 ;   b.lo 8 ; udf
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/vhigh_bits.clif

@@ -8,17 +8,17 @@ block0(v0: i8x16):
 }
 
 ; block0:
-;   sshr v3.16b, v0.16b, #7
+;   sshr v2.16b, v0.16b, #7
-;   movz x6, #513
+;   movz x5, #513
-;   movk x6, x6, #2052, LSL #16
+;   movk x5, x5, #2052, LSL #16
-;   movk x6, x6, #8208, LSL #32
+;   movk x5, x5, #8208, LSL #32
-;   movk x6, x6, #32832, LSL #48
+;   movk x5, x5, #32832, LSL #48
-;   dup v17.2d, x6
+;   dup v16.2d, x5
-;   and v20.16b, v3.16b, v17.16b
+;   and v19.16b, v2.16b, v16.16b
-;   ext v22.16b, v20.16b, v20.16b, #8
+;   ext v21.16b, v19.16b, v19.16b, #8
-;   zip1 v24.16b, v20.16b, v22.16b
+;   zip1 v23.16b, v19.16b, v21.16b
-;   addv h26, v24.8h
+;   addv h25, v23.8h
-;   umov w0, v26.h[0]
+;   umov w0, v25.h[0]
 ;   ret
 
 function %f2(i8x16) -> i16 {
@@ -28,17 +28,17 @@ block0(v0: i8x16):
 }
 
 ; block0:
-;   sshr v3.16b, v0.16b, #7
+;   sshr v2.16b, v0.16b, #7
-;   movz x6, #513
+;   movz x5, #513
-;   movk x6, x6, #2052, LSL #16
+;   movk x5, x5, #2052, LSL #16
-;   movk x6, x6, #8208, LSL #32
+;   movk x5, x5, #8208, LSL #32
-;   movk x6, x6, #32832, LSL #48
+;   movk x5, x5, #32832, LSL #48
-;   dup v17.2d, x6
+;   dup v16.2d, x5
-;   and v20.16b, v3.16b, v17.16b
+;   and v19.16b, v2.16b, v16.16b
-;   ext v22.16b, v20.16b, v20.16b, #8
+;   ext v21.16b, v19.16b, v19.16b, #8
-;   zip1 v24.16b, v20.16b, v22.16b
+;   zip1 v23.16b, v19.16b, v21.16b
-;   addv h26, v24.8h
+;   addv h25, v23.8h
-;   umov w0, v26.h[0]
+;   umov w0, v25.h[0]
 ;   ret
 
 function %f3(i16x8) -> i8 {
@@ -48,11 +48,11 @@ block0(v0: i16x8):
 }
 
 ; block0:
-;   sshr v3.8h, v0.8h, #15
+;   sshr v2.8h, v0.8h, #15
-;   ldr q5, pc+8 ; b 20 ; data.f128 0x00800040002000100008000400020001
+;   ldr q4, pc+8 ; b 20 ; data.f128 0x00800040002000100008000400020001
-;   and v7.16b, v3.16b, v5.16b
+;   and v6.16b, v2.16b, v4.16b
-;   addv h17, v7.8h
+;   addv h16, v6.8h
-;   umov w0, v17.h[0]
+;   umov w0, v16.h[0]
 ;   ret
 
 function %f4(i32x4) -> i8 {
@@ -62,11 +62,11 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   sshr v3.4s, v0.4s, #31
+;   sshr v2.4s, v0.4s, #31
-;   ldr q5, pc+8 ; b 20 ; data.f128 0x00000008000000040000000200000001
+;   ldr q4, pc+8 ; b 20 ; data.f128 0x00000008000000040000000200000001
-;   and v7.16b, v3.16b, v5.16b
+;   and v6.16b, v2.16b, v4.16b
-;   addv s17, v7.4s
+;   addv s16, v6.4s
-;   mov w0, v17.s[0]
+;   mov w0, v16.s[0]
 ;   ret
 
 function %f5(i64x2) -> i8 {
@@ -76,10 +76,10 @@ block0(v0: i64x2):
 }
 
 ; block0:
-;   mov x3, v0.d[1]
+;   mov x2, v0.d[1]
-;   mov x5, v0.d[0]
+;   mov x4, v0.d[0]
-;   lsr x7, x3, #63
+;   lsr x6, x2, #63
-;   lsr x9, x5, #63
+;   lsr x8, x4, #63
-;   add x0, x9, x7, LSL 1
+;   add x0, x8, x6, LSL 1
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/amodes.clif

@@ -11,9 +11,9 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   sext.w a3,a1
+;   sext.w a2,a1
-;   add a3,a0,a3
+;   add a2,a0,a2
-;   lw a0,0(a3)
+;   lw a0,0(a2)
 ;   ret
 
 function %f6(i64, i32) -> i32 {
@@ -25,9 +25,9 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   sext.w a3,a1
+;   sext.w a2,a1
-;   add a3,a3,a0
+;   add a2,a2,a0
-;   lw a0,0(a3)
+;   lw a0,0(a2)
 ;   ret
 
 function %f7(i32, i32) -> i32 {
@@ -40,10 +40,10 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   uext.w a4,a0
+;   uext.w a3,a0
-;   uext.w a5,a1
+;   uext.w a4,a1
-;   add a4,a4,a5
+;   add a3,a3,a4
-;   lw a0,0(a4)
+;   lw a0,0(a3)
 ;   ret
 
 function %f8(i64, i32) -> i32 {
@@ -58,11 +58,11 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   sext.w a5,a1
+;   sext.w a4,a1
-;   addi a5,a5,32
+;   addi a4,a4,32
-;   add a5,a5,a0
+;   add a4,a4,a0
-;   add a5,a5,a5
+;   add a4,a4,a4
-;   lw a0,4(a5)
+;   lw a0,4(a4)
 ;   ret
 
 function %f9(i64, i64, i64) -> i32 {
@@ -76,10 +76,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   add a5,a0,a1
+;   add a4,a0,a1
-;   add a5,a5,a2
+;   add a4,a4,a2
-;   addi a5,a5,48
+;   addi a4,a4,48
-;   lw a0,0(a5)
+;   lw a0,0(a4)
 ;   ret
 
 function %f10(i64, i64, i64) -> i32 {
@@ -93,12 +93,12 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   add a6,a0,a1
+;   add a5,a0,a1
-;   add a6,a6,a2
+;   add a5,a5,a2
-;   lui a5,1
+;   lui a4,1
-;   addi a5,a5,4
+;   addi a4,a4,4
-;   add t3,a6,a5
+;   add a7,a5,a4
-;   lw a0,0(t3)
+;   lw a0,0(a7)
 ;   ret
 
 function %f10() -> i32 {
@@ -109,8 +109,8 @@ block0:
 }
 
 ; block0:
-;   li t1,1234
+;   li t0,1234
-;   lw a0,0(t1)
+;   lw a0,0(t0)
 ;   ret
 
 function %f11(i64) -> i32 {
@@ -123,8 +123,8 @@ block0(v0: i64):
 
 ; block0:
 ;   lui a1,2048
-;   add a3,a0,a1
+;   add a2,a0,a1
-;   lw a0,0(a3)
+;   lw a0,0(a2)
 ;   ret
 
 function %f12(i64) -> i32 {
@@ -136,8 +136,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   addi a1,a0,-4
+;   addi a0,a0,-4
-;   lw a0,0(a1)
+;   lw a0,0(a0)
 ;   ret
 
 function %f13(i64) -> i32 {
@@ -151,8 +151,8 @@ block0(v0: i64):
 ; block0:
 ;   lui a1,244141
 ;   addi a1,a1,2560
-;   add a4,a0,a1
+;   add a3,a0,a1
-;   lw a0,0(a4)
+;   lw a0,0(a3)
 ;   ret
 
 function %f14(i32) -> i32 {
@@ -163,8 +163,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sext.w a1,a0
+;   sext.w a0,a0
-;   lw a0,0(a1)
+;   lw a0,0(a0)
 ;   ret
 
 function %f15(i32, i32) -> i32 {
@@ -177,10 +177,10 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sext.w a4,a0
+;   sext.w a3,a0
-;   sext.w a5,a1
+;   sext.w a4,a1
-;   add a4,a4,a5
+;   add a3,a3,a4
-;   lw a0,0(a4)
+;   lw a0,0(a3)
 ;   ret
 
 function %f18(i64, i64, i64) -> i32 {
@@ -192,10 +192,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lui a3,1048575
+;   lui a2,1048575
-;   addi a3,a3,4094
+;   addi a2,a2,4094
-;   uext.w a6,a3
+;   uext.w a5,a2
-;   lh a0,0(a6)
+;   lh a0,0(a5)
 ;   ret
 
 function %f19(i64, i64, i64) -> i32 {
@@ -207,10 +207,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lui a3,1
+;   lui a2,1
-;   addi a3,a3,2
+;   addi a2,a2,2
-;   uext.w a6,a3
+;   uext.w a5,a2
-;   lh a0,0(a6)
+;   lh a0,0(a5)
 ;   ret
 
 function %f20(i64, i64, i64) -> i32 {
@@ -222,10 +222,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lui a3,1048575
+;   lui a2,1048575
-;   addi a3,a3,4094
+;   addi a2,a2,4094
-;   sext.w a6,a3
+;   sext.w a5,a2
-;   lh a0,0(a6)
+;   lh a0,0(a5)
 ;   ret
 
 function %f21(i64, i64, i64) -> i32 {
@@ -237,10 +237,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lui a3,1
+;   lui a2,1
-;   addi a3,a3,2
+;   addi a2,a2,2
-;   sext.w a6,a3
+;   sext.w a5,a2
-;   lh a0,0(a6)
+;   lh a0,0(a5)
 ;   ret
 
 function %i128(i64) -> i128 {
@@ -251,13 +251,13 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ld a1,0(a0)
+;   ld t2,0(a0)
-;   mv a3,a1
+;   mv a2,t2
 ;   ld a1,8(a0)
-;   mv a5,a3
+;   mv a3,a2
-;   sd a5,0(a0)
+;   sd a3,0(a0)
 ;   sd a1,8(a0)
-;   mv a0,a3
+;   mv a0,a2
 ;   ret
 
 function %i128_imm_offset(i64) -> i128 {
@@ -268,13 +268,13 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ld a1,16(a0)
+;   ld t2,16(a0)
-;   mv a3,a1
+;   mv a2,t2
 ;   ld a1,24(a0)
-;   mv a5,a3
+;   mv a3,a2
-;   sd a5,16(a0)
+;   sd a3,16(a0)
 ;   sd a1,24(a0)
-;   mv a0,a3
+;   mv a0,a2
 ;   ret
 
 function %i128_imm_offset_large(i64) -> i128 {
@@ -285,13 +285,13 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ld a1,504(a0)
+;   ld t2,504(a0)
-;   mv a3,a1
+;   mv a2,t2
 ;   ld a1,512(a0)
-;   mv a5,a3
+;   mv a3,a2
-;   sd a5,504(a0)
+;   sd a3,504(a0)
 ;   sd a1,512(a0)
-;   mv a0,a3
+;   mv a0,a2
 ;   ret
 
 function %i128_imm_offset_negative_large(i64) -> i128 {
@@ -302,13 +302,13 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ld a1,-512(a0)
+;   ld t2,-512(a0)
-;   mv a3,a1
+;   mv a2,t2
 ;   ld a1,-504(a0)
-;   mv a5,a3
+;   mv a3,a2
-;   sd a5,-512(a0)
+;   sd a3,-512(a0)
 ;   sd a1,-504(a0)
-;   mv a0,a3
+;   mv a0,a2
 ;   ret
 
 function %i128_add_offset(i64) -> i128 {
@@ -320,11 +320,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   addi a3,a0,32
+;   addi a2,a0,32
-;   ld a0,0(a3)
+;   ld a0,0(a2)
-;   ld a1,8(a3)
+;   ld a1,8(a2)
-;   sd a0,0(a3)
+;   sd a0,0(a2)
-;   sd a1,8(a3)
+;   sd a1,8(a2)
 ;   ret
 
 function %i128_32bit_sextend_simple(i32) -> i128 {
@@ -336,11 +336,11 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sext.w a3,a0
+;   sext.w a2,a0
-;   ld a0,0(a3)
+;   ld a0,0(a2)
-;   ld a1,8(a3)
+;   ld a1,8(a2)
-;   sd a0,0(a3)
+;   sd a0,0(a2)
-;   sd a1,8(a3)
+;   sd a1,8(a2)
 ;   ret
 
 function %i128_32bit_sextend(i64, i32) -> i128 {
@@ -354,12 +354,12 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   sext.w a6,a1
+;   sext.w a4,a1
-;   add a6,a0,a6
+;   add a4,a0,a4
-;   addi a6,a6,24
+;   addi a4,a4,24
-;   ld a0,0(a6)
+;   ld a0,0(a4)
-;   ld a1,8(a6)
+;   ld a1,8(a4)
-;   sd a0,0(a6)
+;   sd a0,0(a4)
-;   sd a1,8(a6)
+;   sd a1,8(a4)
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/arithmetic.clif

@@ -61,11 +61,11 @@ block0(v0: i64, v1: i64):
 ; block0:
 ;   li a2,-1
 ;   li a3,1
-;   slli a5,a3,63
+;   slli a4,a3,63
-;   eq a7,a2,a1##ty=i64
+;   eq a6,a2,a1##ty=i64
-;   eq t4,a5,a0##ty=i64
+;   eq t3,a4,a0##ty=i64
-;   and t1,a7,t4
+;   and t0,a6,t3
-;   trap_if t1,int_ovf
+;   trap_if t0,int_ovf
 ;   trap_ifc int_divz##(zero eq a1)
 ;   div a0,a0,a1
 ;   ret
@@ -78,18 +78,18 @@ block0(v0: i64):
 }
 
 ; block0:
+;   li t2,2
+;   li a1,-1
+;   li a3,1
+;   slli a5,a3,63
+;   eq a7,a1,t2##ty=i64
+;   eq t4,a5,a0##ty=i64
+;   and t1,a7,t4
+;   trap_if t1,int_ovf
 ;   li a1,2
-;   li a2,-1
+;   trap_ifc int_divz##(zero eq a1)
-;   li a4,1
+;   li a4,2
-;   slli a6,a4,63
+;   div a0,a0,a4
-;   eq t3,a2,a1##ty=i64
-;   eq t0,a6,a0##ty=i64
-;   and t2,t3,t0
-;   trap_if t2,int_ovf
-;   li a2,2
-;   trap_ifc int_divz##(zero eq a2)
-;   li a5,2
-;   div a0,a0,a5
 ;   ret
 
 function %f8(i64, i64) -> i64 {
@@ -111,10 +111,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,2
+;   li t2,2
-;   trap_ifc int_divz##(zero eq a1)
+;   trap_ifc int_divz##(zero eq t2)
-;   li a3,2
+;   li a2,2
-;   divu a0,a0,a3
+;   divu a0,a0,a2
 ;   ret
 
 function %f10(i64, i64) -> i64 {
@@ -146,18 +146,18 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sext.w a2,a0
+;   sext.w a0,a0
-;   sext.w a3,a1
+;   sext.w a2,a1
-;   li a5,-1
+;   li a4,-1
-;   li a7,1
+;   li a6,1
-;   slli t4,a7,63
+;   slli t3,a6,63
-;   slli t1,a2,32
+;   slli t0,a0,32
-;   eq a0,a5,a3##ty=i32
+;   eq t2,a4,a2##ty=i32
-;   eq a4,t4,t1##ty=i32
+;   eq a1,t3,t0##ty=i32
-;   and a4,a0,a4
+;   and a3,t2,a1
-;   trap_if a4,int_ovf
+;   trap_if a3,int_ovf
-;   trap_ifc int_divz##(zero eq a3)
+;   trap_ifc int_divz##(zero eq a2)
-;   divw a0,a2,a3
+;   divw a0,a0,a2
 ;   ret
 
 function %f13(i32) -> i32 {
@@ -168,19 +168,19 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sext.w a0,a0
+;   sext.w t2,a0
-;   li a2,2
+;   li a1,2
-;   sext.w a4,a2
+;   sext.w a3,a1
-;   li a6,-1
+;   li a5,-1
-;   li t3,1
+;   li a7,1
-;   slli t0,t3,63
+;   slli t4,a7,63
-;   slli t2,a0,32
+;   slli t1,t2,32
-;   eq a1,a6,a4##ty=i32
+;   eq a0,a5,a3##ty=i32
-;   eq a3,t0,t2##ty=i32
+;   eq a2,t4,t1##ty=i32
-;   and a5,a1,a3
+;   and a4,a0,a2
-;   trap_if a5,int_ovf
+;   trap_if a4,int_ovf
-;   trap_ifc int_divz##(zero eq a4)
+;   trap_ifc int_divz##(zero eq a3)
-;   divw a0,a0,a4
+;   divw a0,t2,a3
 ;   ret
 
 function %f14(i32, i32) -> i32 {
@@ -190,10 +190,11 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   uext.w a1,a1
+;   mv a5,a0
-;   trap_ifc int_divz##(zero eq a1)
+;   uext.w a0,a1
-;   uext.w a4,a0
+;   trap_ifc int_divz##(zero eq a0)
-;   divuw a0,a4,a1
+;   uext.w a3,a5
+;   divuw a0,a3,a0
 ;   ret
 
 function %f15(i32) -> i32 {
@@ -204,11 +205,11 @@ block0(v0: i32):
 }
 
 ; block0:
-;   li a1,2
+;   li t2,2
-;   uext.w a2,a1
+;   uext.w a1,t2
-;   trap_ifc int_divz##(zero eq a2)
+;   trap_ifc int_divz##(zero eq a1)
-;   uext.w a5,a0
+;   uext.w a4,a0
-;   divuw a0,a5,a2
+;   divuw a0,a4,a1
 ;   ret
 
 function %f16(i32, i32) -> i32 {
@@ -340,8 +341,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   li a1,-1
+;   li t2,-1
-;   subw a0,a0,a1
+;   subw a0,a0,t2
 ;   ret
 
 function %f28(i64) -> i64 {
@@ -352,8 +353,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,-1
+;   li t2,-1
-;   sub a0,a0,a1
+;   sub a0,a0,t2
 ;   ret
 
 function %f29(i64) -> i64 {
@@ -364,8 +365,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a0,1
+;   li t2,1
-;   sub a0,zero,a0
+;   sub a0,zero,t2
 ;   ret
 
 function %add_i128(i128, i128) -> i128 {
@@ -376,9 +377,9 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   add a0,a0,a2
-;   sltu a6,a0,a2
+;   sltu a4,a0,a2
-;   add t3,a1,a3
+;   add a6,a1,a3
-;   add a1,t3,a6
+;   add a1,a6,a4
 ;   ret
 
 function %sub_i128(i128, i128) -> i128 {
@@ -388,12 +389,12 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   sub a4,a0,a2
+;   sub a2,a0,a2
-;   mv t4,a4
+;   mv a7,a2
-;   sltu a6,a0,t4
+;   sltu a4,a0,a7
-;   sub t3,a1,a3
+;   mv a0,a7
-;   sub a1,t3,a6
+;   sub a6,a1,a3
-;   mv a0,a4
+;   sub a1,a6,a4
 ;   ret
 
 function %add_mul_2(i32, i32, i32) -> i32 {
@@ -404,8 +405,8 @@ block0(v0: i32, v1: i32, v2: i32):
 }
 
 ; block0:
-;   mulw a3,a1,a2
+;   mulw a2,a1,a2
-;   addw a0,a3,a0
+;   addw a0,a2,a0
 ;   ret
 
 function %msub_i32(i32, i32, i32) -> i32 {
@@ -416,8 +417,8 @@ block0(v0: i32, v1: i32, v2: i32):
 }
 
 ; block0:
-;   mulw a3,a1,a2
+;   mulw a2,a1,a2
-;   subw a0,a0,a3
+;   subw a0,a0,a2
 ;   ret
 
 function %msub_i64(i64, i64, i64) -> i64 {
@@ -428,8 +429,8 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   mul a3,a1,a2
+;   mul a2,a1,a2
-;   sub a0,a0,a3
+;   sub a0,a0,a2
 ;   ret
 
 function %imul_sub_i32(i32, i32, i32) -> i32 {
@@ -440,8 +441,8 @@ block0(v0: i32, v1: i32, v2: i32):
 }
 
 ; block0:
-;   mulw a3,a1,a2
+;   mulw a2,a1,a2
-;   subw a0,a3,a0
+;   subw a0,a2,a0
 ;   ret
 
 function %imul_sub_i64(i64, i64, i64) -> i64 {
@@ -452,8 +453,8 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   mul a3,a1,a2
+;   mul a2,a1,a2
-;   sub a0,a3,a0
+;   sub a0,a2,a0
 ;   ret
 
 function %srem_const (i64) -> i64 {
@@ -464,10 +465,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,2
+;   li t2,2
-;   trap_ifc int_divz##(zero eq a1)
+;   trap_ifc int_divz##(zero eq t2)
-;   li a3,2
+;   li a2,2
-;   rem a0,a0,a3
+;   rem a0,a0,a2
 ;   ret
 
 function %urem_const (i64) -> i64 {
@@ -478,10 +479,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,2
+;   li t2,2
-;   trap_ifc int_divz##(zero eq a1)
+;   trap_ifc int_divz##(zero eq t2)
-;   li a3,2
+;   li a2,2
-;   remu a0,a0,a3
+;   remu a0,a0,a2
 ;   ret
 
 function %sdiv_minus_one(i64) -> i64 {
@@ -492,17 +493,17 @@ block0(v0: i64):
 }
 
 ; block0:
+;   li t2,-1
 ;   li a1,-1
-;   li a2,-1
+;   li a3,1
-;   li a4,1
+;   slli a5,a3,63
-;   slli a6,a4,63
+;   eq a7,a1,t2##ty=i64
-;   eq t3,a2,a1##ty=i64
+;   eq t4,a5,a0##ty=i64
-;   eq t0,a6,a0##ty=i64
+;   and t1,a7,t4
-;   and t2,t3,t0
+;   trap_if t1,int_ovf
-;   trap_if t2,int_ovf
+;   li a1,-1
-;   li a2,-1
+;   trap_ifc int_divz##(zero eq a1)
-;   trap_ifc int_divz##(zero eq a2)
+;   li a4,-1
-;   li a5,-1
+;   div a0,a0,a4
-;   div a0,a0,a5
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/atomic_load.clif

@@ -30,7 +30,7 @@ block0(v0: i64):
 }
 
 ; block0:
-;   atomic_load.i32 a1,(a0)
+;   atomic_load.i32 a0,(a0)
-;   uext.w a0,a1
+;   uext.w a0,a0
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/bitops.clif

@@ -9,8 +9,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   brev8 a4,a0##tmp=a3 tmp2=a1 step=a2 ty=i8
+;   mv a3,a0
-;   mv a0,a4
+;   brev8 a0,a3##tmp=t2 tmp2=a2 step=a1 ty=i8
 ;   ret
 
 function %a(i16) -> i16 {
@@ -20,10 +20,10 @@ block0(v0: i16):
 }
 
 ; block0:
-;   mv t3,a0
+;   mv a7,a0
-;   brev8 a3,t3##tmp=a0 tmp2=a1 step=a2 ty=i16
+;   brev8 a2,a7##tmp=t2 tmp2=a0 step=a1 ty=i16
-;   rev8 a5,a3##step=a7 tmp=a6
+;   rev8 a4,a2##step=a6 tmp=a5
-;   srli a0,a5,48
+;   srli a0,a4,48
 ;   ret
 
 function %a(i32) -> i32 {
@@ -33,10 +33,10 @@ block0(v0: i32):
 }
 
 ; block0:
-;   mv t3,a0
+;   mv a7,a0
-;   brev8 a3,t3##tmp=a0 tmp2=a1 step=a2 ty=i32
+;   brev8 a2,a7##tmp=t2 tmp2=a0 step=a1 ty=i32
-;   rev8 a5,a3##step=a7 tmp=a6
+;   rev8 a4,a2##step=a6 tmp=a5
-;   srli a0,a5,32
+;   srli a0,a4,32
 ;   ret
 
 function %a(i64) -> i64 {
@@ -46,8 +46,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   rev8 a3,a0##step=a2 tmp=a1
+;   mv a6,a0
-;   brev8 a0,a3##tmp=a4 tmp2=a5 step=a6 ty=i64
+;   rev8 t2,a6##step=a1 tmp=a0
+;   brev8 a0,t2##tmp=a3 tmp2=a4 step=a5 ty=i64
 ;   ret
 
 function %a(i128) -> i128 {
@@ -57,11 +58,13 @@ block0(v0: i128):
 }
 
 ; block0:
-;   rev8 a2,a0##step=a4 tmp=a3
+;   mv a3,a0
-;   brev8 t4,a2##tmp=a6 tmp2=a7 step=t3 ty=i64
+;   mv a7,a1
-;   rev8 t1,a1##step=a0 tmp=t2
+;   rev8 a0,a3##step=a2 tmp=a1
-;   brev8 a0,t1##tmp=a2 tmp2=a3 step=a4 ty=i64
+;   brev8 a1,a0##tmp=a4 tmp2=a5 step=a6 ty=i64
-;   mv a1,t4
+;   mv a3,a7
+;   rev8 t4,a3##step=t1 tmp=t0
+;   brev8 a0,t4##tmp=a4 tmp2=a3 step=a2 ty=i64
 ;   ret
 
 function %b(i8) -> i8 {
@@ -71,8 +74,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   clz a3,a0##ty=i8 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   clz a0,a2##ty=i8 tmp=t2 step=a1
 ;   ret
 
 function %b(i16) -> i16 {
@@ -82,8 +85,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   clz a3,a0##ty=i16 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   clz a0,a2##ty=i16 tmp=t2 step=a1
 ;   ret
 
 function %b(i32) -> i32 {
@@ -93,8 +96,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   clz a3,a0##ty=i32 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   clz a0,a2##ty=i32 tmp=t2 step=a1
 ;   ret
 
 function %b(i64) -> i64 {
@@ -104,8 +107,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   clz a3,a0##ty=i64 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   clz a0,a2##ty=i64 tmp=t2 step=a1
 ;   ret
 
 function %b(i128) -> i128 {
@@ -115,11 +118,12 @@ block0(v0: i128):
 }
 
 ; block0:
-;   clz a4,a1##ty=i64 tmp=a2 step=a3
+;   mv t0,a1
-;   clz t3,a0##ty=i64 tmp=a6 step=a7
+;   clz a2,t0##ty=i64 tmp=a3 step=a1
-;   li t0,64
+;   clz a6,a0##ty=i64 tmp=a4 step=a5
-;   select_reg t2,t3,zero##condition=(t0 eq a4)
+;   li t3,64
-;   add a0,a4,t2
+;   select_reg t0,a6,zero##condition=(t3 eq a2)
+;   add a0,a2,t0
 ;   li a1,0
 ;   ret
 
@@ -130,11 +134,11 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sext.b a1,a0
+;   sext.b t2,a0
-;   not a2,a0
+;   not a1,a0
-;   select_reg a4,a2,a0##condition=(a1 slt zero)
+;   select_reg a3,a1,a0##condition=(t2 slt zero)
-;   clz t3,a4##ty=i8 tmp=a6 step=a7
+;   clz a7,a3##ty=i8 tmp=a5 step=a6
-;   addi a0,t3,-1
+;   addi a0,a7,-1
 ;   ret
 
 function %c(i16) -> i16 {
@@ -144,11 +148,11 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sext.h a1,a0
+;   sext.h t2,a0
-;   not a2,a0
+;   not a1,a0
-;   select_reg a4,a2,a0##condition=(a1 slt zero)
+;   select_reg a3,a1,a0##condition=(t2 slt zero)
-;   clz t3,a4##ty=i16 tmp=a6 step=a7
+;   clz a7,a3##ty=i16 tmp=a5 step=a6
-;   addi a0,t3,-1
+;   addi a0,a7,-1
 ;   ret
 
 function %c(i32) -> i32 {
@@ -158,11 +162,11 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sext.w a1,a0
+;   sext.w t2,a0
-;   not a2,a0
+;   not a1,a0
-;   select_reg a4,a2,a0##condition=(a1 slt zero)
+;   select_reg a3,a1,a0##condition=(t2 slt zero)
-;   clz t3,a4##ty=i32 tmp=a6 step=a7
+;   clz a7,a3##ty=i32 tmp=a5 step=a6
-;   addi a0,t3,-1
+;   addi a0,a7,-1
 ;   ret
 
 function %c(i64) -> i64 {
@@ -172,10 +176,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   not a1,a0
+;   not t2,a0
-;   select_reg a2,a1,a0##condition=(a0 slt zero)
+;   select_reg a1,t2,a0##condition=(a0 slt zero)
-;   clz a6,a2##ty=i64 tmp=a4 step=a5
+;   clz a5,a1##ty=i64 tmp=a3 step=a4
-;   addi a0,a6,-1
+;   addi a0,a5,-1
 ;   ret
 
 function %c(i128) -> i128 {
@@ -186,16 +190,16 @@ block0(v0: i128):
 
 ; block0:
 ;   not a2,a0
-;   select_reg a4,a2,a0##condition=(a1 slt zero)
+;   select_reg a2,a2,a0##condition=(a1 slt zero)
-;   not a6,a1
+;   not a4,a1
-;   select_reg t3,a6,a1##condition=(a1 slt zero)
+;   select_reg a6,a4,a1##condition=(a1 slt zero)
-;   clz t2,t3##ty=i64 tmp=t0 step=t1
+;   clz t0,a6##ty=i64 tmp=t3 step=t4
-;   clz a3,a4##ty=i64 tmp=a1 step=a2
+;   clz a1,a2##ty=i64 tmp=t2 step=a0
-;   li a5,64
+;   li a3,64
-;   select_reg a7,a3,zero##condition=(a5 eq t2)
+;   select_reg a5,a1,zero##condition=(a3 eq t0)
-;   add t4,t2,a7
+;   add a7,t0,a5
-;   li t1,0
+;   li t4,0
-;   addi a0,t4,-1
+;   addi a0,a7,-1
 ;   li a1,0
 ;   ret
 
@@ -206,8 +210,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   ctz a3,a0##ty=i8 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   ctz a0,a2##ty=i8 tmp=t2 step=a1
 ;   ret
 
 function %d(i16) -> i16 {
@@ -217,8 +221,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   ctz a3,a0##ty=i16 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   ctz a0,a2##ty=i16 tmp=t2 step=a1
 ;   ret
 
 function %d(i32) -> i32 {
@@ -228,8 +232,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   ctz a3,a0##ty=i32 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   ctz a0,a2##ty=i32 tmp=t2 step=a1
 ;   ret
 
 function %d(i64) -> i64 {
@@ -239,8 +243,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ctz a3,a0##ty=i64 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   ctz a0,a2##ty=i64 tmp=t2 step=a1
 ;   ret
 
 function %d(i128) -> i128 {
@@ -250,11 +254,12 @@ block0(v0: i128):
 }
 
 ; block0:
-;   ctz a4,a0##ty=i64 tmp=a2 step=a3
+;   mv t0,a0
-;   ctz t3,a1##ty=i64 tmp=a6 step=a7
+;   ctz a2,t0##ty=i64 tmp=a0 step=a3
-;   li t0,64
+;   ctz a6,a1##ty=i64 tmp=a4 step=a5
-;   select_reg t2,t3,zero##condition=(t0 eq a4)
+;   li t3,64
-;   add a0,a4,t2
+;   select_reg t0,a6,zero##condition=(t3 eq a2)
+;   add a0,a2,t0
 ;   li a1,0
 ;   ret
 
@@ -265,9 +270,10 @@ block0(v0: i128):
 }
 
 ; block0:
-;   popcnt a4,a0##ty=i64 tmp=a2 step=a3
+;   mv t3,a0
-;   popcnt t3,a1##ty=i64 tmp=a6 step=a7
+;   popcnt a2,t3##ty=i64 tmp=a0 step=a3
-;   add a0,a4,t3
+;   popcnt a6,a1##ty=i64 tmp=a4 step=a5
+;   add a0,a2,a6
 ;   li a1,0
 ;   ret
 
@@ -278,8 +284,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   popcnt a3,a0##ty=i64 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   popcnt a0,a2##ty=i64 tmp=t2 step=a1
 ;   ret
 
 function %d(i32) -> i32 {
@@ -289,8 +295,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   popcnt a3,a0##ty=i32 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   popcnt a0,a2##ty=i32 tmp=t2 step=a1
 ;   ret
 
 function %d(i16) -> i16 {
@@ -300,8 +306,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   popcnt a3,a0##ty=i16 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   popcnt a0,a2##ty=i16 tmp=t2 step=a1
 ;   ret
 
 function %d(i8) -> i8 {
@@ -311,8 +317,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   popcnt a3,a0##ty=i8 tmp=a2 step=a1
+;   mv a2,a0
-;   mv a0,a3
+;   popcnt a0,a2##ty=i8 tmp=t2 step=a1
 ;   ret
 
 function %bnot_i32(i32) -> i32 {
@@ -344,8 +350,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   slli a1,a0,3
+;   slli a0,a0,3
-;   not a0,a1
+;   not a0,a0
 ;   ret
 
 function %bnot_i128(i128) -> i128 {
@@ -421,8 +427,8 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   slli a2,a1,3
+;   slli a1,a1,3
-;   and a0,a0,a2
+;   and a0,a0,a1
 ;   ret
 
 function %band_i64_constant_shift2(i64, i64) -> i64 {
@@ -434,8 +440,8 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   slli a2,a1,3
+;   slli a1,a1,3
-;   and a0,a2,a0
+;   and a0,a1,a0
 ;   ret
 
 function %bor_i32(i32, i32) -> i32 {
@@ -500,8 +506,8 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   slli a2,a1,3
+;   slli a1,a1,3
-;   or a0,a0,a2
+;   or a0,a0,a1
 ;   ret
 
 function %bor_i64_constant_shift2(i64, i64) -> i64 {
@@ -513,8 +519,8 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   slli a2,a1,3
+;   slli a1,a1,3
-;   or a0,a2,a0
+;   or a0,a1,a0
 ;   ret
 
 function %bxor_i32(i32, i32) -> i32 {
@@ -579,8 +585,8 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   slli a2,a1,3
+;   slli a1,a1,3
-;   xor a0,a0,a2
+;   xor a0,a0,a1
 ;   ret
 
 function %bxor_i64_constant_shift2(i64, i64) -> i64 {
@@ -592,8 +598,8 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   slli a2,a1,3
+;   slli a1,a1,3
-;   xor a0,a2,a0
+;   xor a0,a1,a0
 ;   ret
 
 function %band_not_i32(i32, i32) -> i32 {
@@ -625,10 +631,10 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   not a4,a2
+;   not a2,a2
-;   and a0,a0,a4
+;   and a0,a0,a2
-;   not t3,a3
+;   not a6,a3
-;   and a1,a1,t3
+;   and a1,a1,a6
 ;   ret
 
 function %band_not_i64_constant(i64) -> i64 {
@@ -639,9 +645,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,4
+;   li t2,4
-;   not a2,a1
+;   not a1,t2
-;   and a0,a0,a2
+;   and a0,a0,a1
 ;   ret
 
 function %band_not_i64_constant_shift(i64, i64) -> i64 {
@@ -653,9 +659,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   slli a3,a1,4
+;   slli a2,a1,4
-;   not a2,a3
+;   not a1,a2
-;   and a0,a0,a2
+;   and a0,a0,a1
 ;   ret
 
 function %bor_not_i32(i32, i32) -> i32 {
@@ -687,10 +693,10 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   not a4,a2
+;   not a2,a2
-;   or a0,a0,a4
+;   or a0,a0,a2
-;   not t3,a3
+;   not a6,a3
-;   or a1,a1,t3
+;   or a1,a1,a6
 ;   ret
 
 function %bor_not_i64_constant(i64) -> i64 {
@@ -701,9 +707,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,4
+;   li t2,4
-;   not a2,a1
+;   not a1,t2
-;   or a0,a0,a2
+;   or a0,a0,a1
 ;   ret
 
 function %bor_not_i64_constant_shift(i64, i64) -> i64 {
@@ -715,9 +721,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   slli a3,a1,4
+;   slli a2,a1,4
-;   not a2,a3
+;   not a1,a2
-;   or a0,a0,a2
+;   or a0,a0,a1
 ;   ret
 
 function %bxor_not_i32(i32, i32) -> i32 {
@@ -749,10 +755,10 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   not a4,a2
+;   not a2,a2
-;   xor a0,a0,a4
+;   xor a0,a0,a2
-;   not t3,a3
+;   not a6,a3
-;   xor a1,a1,t3
+;   xor a1,a1,a6
 ;   ret
 
 function %bxor_not_i64_constant(i64) -> i64 {
@@ -763,9 +769,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,4
+;   li t2,4
-;   not a2,a1
+;   not a1,t2
-;   xor a0,a0,a2
+;   xor a0,a0,a1
 ;   ret
 
 function %bxor_not_i64_constant_shift(i64, i64) -> i64 {
@@ -777,9 +783,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   slli a3,a1,4
+;   slli a2,a1,4
-;   not a2,a3
+;   not a1,a2
-;   xor a0,a0,a2
+;   xor a0,a0,a1
 ;   ret
 
 function %ishl_i128_i8(i128, i8) -> i128 {
@@ -789,17 +795,18 @@ block0(v0: i128, v1: i8):
 }
 
 ; block0:
-;   andi a3,a2,127
+;   mv a4,a1
-;   li a5,128
+;   andi a1,a2,127
-;   sub a5,a5,a3
+;   li a3,128
-;   sll t3,a0,a3
+;   sub a3,a3,a1
-;   srl t0,a0,a5
+;   sll a6,a0,a1
-;   select_reg t2,zero,t0##condition=(a3 eq zero)
+;   srl t3,a0,a3
-;   sll a1,a1,a3
+;   select_reg t0,zero,t3##condition=(a1 eq zero)
-;   or a4,t2,a1
+;   sll t2,a4,a1
-;   li a5,64
+;   or a2,t0,t2
-;   select_reg a0,zero,t3##condition=(a3 uge a5)
+;   li a3,64
-;   select_reg a1,t3,a4##condition=(a3 uge a5)
+;   select_reg a0,zero,a6##condition=(a1 uge a3)
+;   select_reg a1,a6,a2##condition=(a1 uge a3)
 ;   ret
 
 function %ishl_i128_i128(i128, i128) -> i128 {
@@ -809,17 +816,17 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   andi a4,a2,127
+;   andi a2,a2,127
-;   li a6,128
+;   li a4,128
-;   sub a6,a6,a4
+;   sub a4,a4,a2
-;   sll t4,a0,a4
+;   sll a7,a0,a2
-;   srl t1,a0,a6
+;   srl t4,a0,a4
-;   select_reg a0,zero,t1##condition=(a4 eq zero)
+;   select_reg t1,zero,t4##condition=(a2 eq zero)
-;   sll a2,a1,a4
+;   sll a0,a1,a2
-;   or a5,a0,a2
+;   or a3,t1,a0
-;   li a6,64
+;   li a4,64
-;   select_reg a0,zero,t4##condition=(a4 uge a6)
+;   select_reg a0,zero,a7##condition=(a2 uge a4)
-;   select_reg a1,t4,a5##condition=(a4 uge a6)
+;   select_reg a1,a7,a3##condition=(a2 uge a4)
 ;   ret
 
 function %ushr_i128_i8(i128, i8) -> i128 {
@@ -829,17 +836,19 @@ block0(v0: i128, v1: i8):
 }
 
 ; block0:
-;   andi a3,a2,127
+;   mv t1,a1
-;   li a5,128
+;   andi a1,a2,127
-;   sub a5,a5,a3
+;   li a3,128
-;   sll t3,a1,a5
+;   sub a3,a3,a1
-;   select_reg t0,zero,t3##condition=(a3 eq zero)
+;   mv a2,t1
-;   srl t2,a0,a3
+;   sll a6,a2,a3
-;   or a2,t0,t2
+;   select_reg t3,zero,a6##condition=(a1 eq zero)
-;   li a4,64
+;   srl t0,a0,a1
-;   srl a5,a1,a3
+;   or t2,t3,t0
-;   select_reg a0,a5,a2##condition=(a3 uge a4)
+;   li a3,64
-;   select_reg a1,zero,a5##condition=(a3 uge a4)
+;   srl a4,a2,a1
+;   select_reg a0,a4,t2##condition=(a1 uge a3)
+;   select_reg a1,zero,a4##condition=(a1 uge a3)
 ;   ret
 
 function %ushr_i128_i128(i128, i128) -> i128 {
@@ -849,17 +858,17 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   andi a4,a2,127
+;   andi a2,a2,127
-;   li a6,128
+;   li a4,128
-;   sub a6,a6,a4
+;   sub a4,a4,a2
-;   sll t4,a1,a6
+;   sll a7,a1,a4
-;   select_reg t1,zero,t4##condition=(a4 eq zero)
+;   select_reg t4,zero,a7##condition=(a2 eq zero)
-;   srl a0,a0,a4
+;   srl t1,a0,a2
-;   or a2,t1,a0
+;   or a0,t4,t1
-;   li a5,64
+;   li a3,64
-;   srl a6,a1,a4
+;   srl a4,a1,a2
-;   select_reg a0,a6,a2##condition=(a4 uge a5)
+;   select_reg a0,a4,a0##condition=(a2 uge a3)
-;   select_reg a1,zero,a6##condition=(a4 uge a5)
+;   select_reg a1,zero,a4##condition=(a2 uge a3)
 ;   ret
 
 function %sshr_i128_i8(i128, i8) -> i128 {
@@ -869,19 +878,20 @@ block0(v0: i128, v1: i8):
 }
 
 ; block0:
-;   andi a3,a2,127
+;   mv a3,a1
-;   li a5,128
+;   andi a1,a2,127
-;   sub a5,a5,a3
+;   li a4,128
-;   sll t3,a1,a5
+;   sub a4,a4,a1
-;   select_reg t0,zero,t3##condition=(a3 eq zero)
+;   sll a6,a3,a4
-;   srl t2,a0,a3
+;   select_reg t3,zero,a6##condition=(a1 eq zero)
-;   or a2,t0,t2
+;   srl t0,a0,a1
-;   li a4,64
+;   or t2,t3,t0
-;   sra a5,a1,a3
+;   li a2,64
-;   li a7,-1
+;   sra a4,a3,a1
-;   select_reg t4,a7,zero##condition=(a1 slt zero)
+;   li a5,-1
-;   select_reg a0,a5,a2##condition=(a3 uge a4)
+;   select_reg a7,a5,zero##condition=(a3 slt zero)
-;   select_reg a1,t4,a5##condition=(a3 uge a4)
+;   select_reg a0,a4,t2##condition=(a1 uge a2)
+;   select_reg a1,a7,a4##condition=(a1 uge a2)
 ;   ret
 
 function %sshr_i128_i128(i128, i128) -> i128 {
@@ -891,18 +901,18 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   andi a4,a2,127
+;   andi a2,a2,127
-;   li a6,128
+;   li a4,128
-;   sub a6,a6,a4
+;   sub a4,a4,a2
-;   sll t4,a1,a6
+;   sll a7,a1,a4
-;   select_reg t1,zero,t4##condition=(a4 eq zero)
+;   select_reg t4,zero,a7##condition=(a2 eq zero)
-;   srl a0,a0,a4
+;   srl t1,a0,a2
-;   or a2,t1,a0
+;   or a0,t4,t1
-;   li a5,64
+;   li a3,64
-;   sra a6,a1,a4
+;   sra a4,a1,a2
-;   li t3,-1
+;   li a6,-1
-;   select_reg t0,t3,zero##condition=(a1 slt zero)
+;   select_reg t3,a6,zero##condition=(a1 slt zero)
-;   select_reg a0,a6,a2##condition=(a4 uge a5)
+;   select_reg a0,a4,a0##condition=(a2 uge a3)
-;   select_reg a1,t0,a6##condition=(a4 uge a5)
+;   select_reg a1,t3,a4##condition=(a2 uge a3)
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/call.clif

@@ -36,8 +36,8 @@ block0(v0: i32):
 ;   mv fp,sp
 ; block0:
 ;   uext.w a0,a0
-;   load_sym a3,%g+0
+;   load_sym a2,%g+0
-;   callind a3
+;   callind a2
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -66,8 +66,8 @@ block0(v0: i32):
 ;   mv fp,sp
 ; block0:
 ;   sext.w a0,a0
-;   load_sym a3,%g+0
+;   load_sym a2,%g+0
-;   callind a3
+;   callind a2
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -109,8 +109,8 @@ block0(v0: i8):
 ;   li a7,42
 ;   sext.b t3,t3
 ;   sd t3,0(sp)
-;   load_sym t4,%g+0
+;   load_sym t3,%g+0
-;   callind t4
+;   callind t3
 ;   add sp,+16
 ;   virtual_sp_offset_adj -16
 ;   ld ra,8(sp)
@@ -125,26 +125,26 @@ block0(v0: i8):
 }
 
 ; block0:
-;   mv a7,a0
-;   mv a6,a1
-;   li a0,42
-;   li a1,42
 ;   li a2,42
-;   li a5,42
+;   mv t1,a2
-;   li t3,42
+;   li a2,42
-;   li t1,42
+;   mv a3,a2
-;   li a3,42
 ;   li a4,42
-;   mv t2,a7
+;   li a6,42
-;   mv t0,a6
+;   li t3,42
-;   sw a2,0(t0)
+;   li t0,42
-;   sw a5,8(t0)
+;   li t2,42
-;   sw t3,16(t0)
+;   li a2,42
-;   sw t1,24(t0)
+;   sw a4,0(a1)
-;   sw a3,32(t0)
+;   sw a6,8(a1)
-;   sw a4,40(t0)
+;   sw t3,16(a1)
-;   sext.b t2,t2
+;   sw t0,24(a1)
-;   sd t2,48(t0)
+;   sw t2,32(a1)
+;   sw a2,40(a1)
+;   sext.b t4,a0
+;   sd a0,48(a1)
+;   mv a0,t1
+;   mv a1,a3
 ;   ret
 
 function %f8() {
@@ -210,7 +210,6 @@ block0(v0: i128, v1: i64):
 }
 
 ; block0:
-;   mv a2,a0
 ;   mv a0,a1
 ;   ret
 
@@ -229,12 +228,12 @@ block0(v0: i64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   mv a6,a0
+;   mv a5,a0
 ;   li a0,42
-;   mv a1,a6
+;   mv a1,a5
 ;   li a2,42
-;   load_sym a6,%f11+0
+;   load_sym a5,%f11+0
-;   callind a6
+;   callind a5
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -248,6 +247,7 @@ block0(v0: i64, v1: i128):
 
 ; block0:
 ;   mv a0,a1
+;   mv a1,a2
 ;   ret
 
 function %f12_call(i64) -> i64 {
@@ -268,8 +268,8 @@ block0(v0: i64):
 ;   mv a1,a0
 ;   li a2,42
 ;   li a0,42
-;   load_sym a6,%f12+0
+;   load_sym a5,%f12+0
-;   callind a6
+;   callind a5
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -283,6 +283,7 @@ block0(v0: i64, v1: i128):
 
 ; block0:
 ;   mv a0,a1
+;   mv a1,a2
 ;   ret
 
 function %f13_call(i64) -> i64 {
@@ -303,8 +304,8 @@ block0(v0: i64):
 ;   mv a1,a0
 ;   li a2,42
 ;   li a0,42
-;   load_sym a6,%f13+0
+;   load_sym a5,%f13+0
-;   callind a6
+;   callind a5
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -320,8 +321,8 @@ block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   ld a1,16(fp)
 ;   mv a0,a7
+;   ld a1,16(fp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -370,8 +371,8 @@ block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   ld a1,16(fp)
 ;   mv a0,a7
+;   ld a1,16(fp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16

cranelift/filetests/filetests/isa/riscv64/condbr.clif

@@ -128,8 +128,8 @@ block2:
 }
 
 ; block0:
-;   eq a3,a0,a1##ty=i64
+;   eq a2,a0,a1##ty=i64
-;   bne a3,zero,taken(label1),not_taken(label2)
+;   bne a2,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   li a0,1
 ;   ret
@@ -149,8 +149,8 @@ block1:
 }
 
 ; block0:
-;   eq a2,a0,a1##ty=i64
+;   eq a1,a0,a1##ty=i64
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   bne a1,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:

cranelift/filetests/filetests/isa/riscv64/condops.clif

@@ -23,11 +23,10 @@ block0(v0: i8):
 }
 
 ; block0:
-;   mv a5,a0
+;   li t2,42
-;   li a0,42
+;   uext.b a1,a0
-;   uext.b a2,a5
+;   uext.b a3,t2
-;   uext.b a4,a0
+;   eq a0,a1,a3##ty=i8
-;   eq a0,a2,a4##ty=i8
 ;   ret
 
 function %h(i8, i8, i8) -> i8 {
@@ -37,11 +36,10 @@ block0(v0: i8, v1: i8, v2: i8):
 }
 
 ; block0:
-;   mv t3,a2
+;   and a1,a0,a1
-;   and a2,a0,a1
+;   not a3,a0
-;   not a4,a0
+;   and a5,a3,a2
-;   and a6,a4,t3
+;   or a0,a1,a5
-;   or a0,a2,a6
 ;   ret
 
 function %i(i8, i8, i8) -> i8 {

cranelift/filetests/filetests/isa/riscv64/constants.clif

@@ -233,11 +233,11 @@ block0:
 }
 
 ; block0:
-;   auipc t2,0
+;   auipc t1,0
-;   ld t2,12(t2)
+;   ld t1,12(t1)
 ;   j 12
 ;   .8byte 0x3ff0000000000000
-;   fmv.d.x fa0,t2
+;   fmv.d.x fa0,t1
 ;   ret
 
 function %f() -> f32 {
@@ -247,8 +247,8 @@ block0:
 }
 
 ; block0:
-;   lui t2,264704
+;   lui t1,264704
-;   fmv.w.x fa0,t2
+;   fmv.w.x fa0,t1
 ;   ret
 
 function %f() -> f64 {
@@ -258,11 +258,11 @@ block0:
 }
 
 ; block0:
-;   auipc t2,0
+;   auipc t1,0
-;   ld t2,12(t2)
+;   ld t1,12(t1)
 ;   j 12
 ;   .8byte 0x4049000000000000
-;   fmv.d.x fa0,t2
+;   fmv.d.x fa0,t1
 ;   ret
 
 function %f() -> f32 {
@@ -272,8 +272,8 @@ block0:
 }
 
 ; block0:
-;   lui t2,271488
+;   lui t1,271488
-;   fmv.w.x fa0,t2
+;   fmv.w.x fa0,t1
 ;   ret
 
 function %f() -> f64 {
@@ -283,8 +283,8 @@ block0:
 }
 
 ; block0:
-;   li t2,0
+;   li t1,0
-;   fmv.d.x fa0,t2
+;   fmv.d.x fa0,t1
 ;   ret
 
 function %f() -> f32 {
@@ -294,8 +294,8 @@ block0:
 }
 
 ; block0:
-;   li t2,0
+;   li t1,0
-;   fmv.w.x fa0,t2
+;   fmv.w.x fa0,t1
 ;   ret
 
 function %f() -> f64 {
@@ -305,11 +305,11 @@ block0:
 }
 
 ; block0:
-;   auipc t2,0
+;   auipc t1,0
-;   ld t2,12(t2)
+;   ld t1,12(t1)
 ;   j 12
 ;   .8byte 0xc030000000000000
-;   fmv.d.x fa0,t2
+;   fmv.d.x fa0,t1
 ;   ret
 
 function %f() -> f32 {
@@ -319,10 +319,10 @@ block0:
 }
 
 ; block0:
-;   auipc t2,0
+;   auipc t1,0
-;   lwu t2,12(t2)
+;   lwu t1,12(t1)
 ;   j 8
 ;   .4byte 0xc1800000
-;   fmv.w.x fa0,t2
+;   fmv.w.x fa0,t1
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/extend-op.clif

@@ -11,8 +11,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sext.b a1,a0
+;   sext.b a0,a0
-;   addi a0,a1,42
+;   addi a0,a0,42
 ;   ret
 
 function %f2(i8, i64) -> i64 {
@@ -44,8 +44,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   slt a1,a0,zero
+;   slt t2,a0,zero
-;   sext.b1 a1,a1
+;   sext.b1 a1,t2
 ;   ret
 
 function %i128_uextend_i32(i32) -> i128 {
@@ -66,9 +66,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sext.w a1,a0
+;   sext.w t2,a0
-;   slt a3,a1,zero
+;   slt a1,t2,zero
-;   sext.b1 a1,a3
+;   sext.b1 a1,a1
 ;   ret
 
 function %i128_uextend_i16(i16) -> i128 {
@@ -89,9 +89,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sext.h a1,a0
+;   sext.h t2,a0
-;   slt a3,a1,zero
+;   slt a1,t2,zero
-;   sext.b1 a1,a3
+;   sext.b1 a1,a1
 ;   ret
 
 function %i128_uextend_i8(i8) -> i128 {
@@ -112,8 +112,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sext.b a1,a0
+;   sext.b t2,a0
-;   slt a3,a1,zero
+;   slt a1,t2,zero
-;   sext.b1 a1,a3
+;   sext.b1 a1,a1
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif

@@ -49,7 +49,7 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvt_to_uint.i8 a0,fa0##in_ty=f32 tmp=ft4
+;   fcvt_to_uint.i8 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
 
 function u0:0(f64) -> i8 {
@@ -59,7 +59,7 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvt_to_uint.i8 a0,fa0##in_ty=f64 tmp=ft4
+;   fcvt_to_uint.i8 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
 
 function u0:0(f32) -> i16 {
@@ -69,7 +69,7 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvt_to_uint.i16 a0,fa0##in_ty=f32 tmp=ft4
+;   fcvt_to_uint.i16 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
 
 function u0:0(f64) -> i16 {
@@ -79,6 +79,6 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvt_to_uint.i16 a0,fa0##in_ty=f64 tmp=ft4
+;   fcvt_to_uint.i16 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/float.clif

@@ -89,8 +89,8 @@ block0(v0: f32, v1: f32):
 }
 
 ; block0:
-;   fmin.s ft4,fa0,fa1##tmp=a2 ty=f32
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft4
+;   fmin.s fa0,ft5,fa1##tmp=a1 ty=f32
 ;   ret
 
 function %f10(f64, f64) -> f64 {
@@ -100,8 +100,8 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   fmin.d ft4,fa0,fa1##tmp=a2 ty=f64
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft4
+;   fmin.d fa0,ft5,fa1##tmp=a1 ty=f64
 ;   ret
 
 function %f11(f32, f32) -> f32 {
@@ -111,8 +111,8 @@ block0(v0: f32, v1: f32):
 }
 
 ; block0:
-;   fmax.s ft4,fa0,fa1##tmp=a2 ty=f32
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft4
+;   fmax.s fa0,ft5,fa1##tmp=a1 ty=f32
 ;   ret
 
 function %f12(f64, f64) -> f64 {
@@ -122,8 +122,8 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   fmax.d ft4,fa0,fa1##tmp=a2 ty=f64
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft4
+;   fmax.d fa0,ft5,fa1##tmp=a1 ty=f64
 ;   ret
 
 function %f13(f32) -> f32 {
@@ -213,8 +213,8 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ceil ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f32
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft3
+;   ceil fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32
 ;   ret
 
 function %f22(f64) -> f64 {
@@ -224,8 +224,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   ceil ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f64
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft3
+;   ceil fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64
 ;   ret
 
 function %f23(f32) -> f32 {
@@ -235,8 +235,8 @@ block0(v0: f32):
 }
 
 ; block0:
-;   floor ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f32
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft3
+;   floor fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32
 ;   ret
 
 function %f24(f64) -> f64 {
@@ -246,8 +246,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   floor ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f64
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft3
+;   floor fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64
 ;   ret
 
 function %f25(f32) -> f32 {
@@ -257,8 +257,8 @@ block0(v0: f32):
 }
 
 ; block0:
-;   trunc ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f32
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft3
+;   trunc fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32
 ;   ret
 
 function %f26(f64) -> f64 {
@@ -268,8 +268,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   trunc ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f64
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft3
+;   trunc fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64
 ;   ret
 
 function %f27(f32) -> f32 {
@@ -279,8 +279,8 @@ block0(v0: f32):
 }
 
 ; block0:
-;   nearest ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f32
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft3
+;   nearest fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32
 ;   ret
 
 function %f28(f64) -> f64 {
@@ -290,8 +290,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   nearest ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f64
+;   fmv.d ft5,fa0
-;   fmv.d fa0,ft3
+;   nearest fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64
 ;   ret
 
 function %f29(f32, f32, f32) -> f32 {
@@ -341,7 +341,7 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvt_to_uint.i32 a0,fa0##in_ty=f32 tmp=ft4
+;   fcvt_to_uint.i32 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
 
 function %f34(f32) -> i32 {
@@ -351,7 +351,7 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvt_to_sint.i32 a0,fa0##in_ty=f32 tmp=ft4
+;   fcvt_to_sint.i32 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
 
 function %f35(f32) -> i64 {
@@ -361,7 +361,7 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvt_to_uint.i64 a0,fa0##in_ty=f32 tmp=ft4
+;   fcvt_to_uint.i64 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
 
 function %f36(f32) -> i64 {
@@ -371,7 +371,7 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvt_to_sint.i64 a0,fa0##in_ty=f32 tmp=ft4
+;   fcvt_to_sint.i64 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
 
 function %f37(f64) -> i32 {
@@ -381,7 +381,7 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvt_to_uint.i32 a0,fa0##in_ty=f64 tmp=ft4
+;   fcvt_to_uint.i32 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
 
 function %f38(f64) -> i32 {
@@ -391,7 +391,7 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvt_to_sint.i32 a0,fa0##in_ty=f64 tmp=ft4
+;   fcvt_to_sint.i32 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
 
 function %f39(f64) -> i64 {
@@ -401,7 +401,7 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvt_to_uint.i64 a0,fa0##in_ty=f64 tmp=ft4
+;   fcvt_to_uint.i64 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
 
 function %f40(f64) -> i64 {
@@ -411,7 +411,7 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvt_to_sint.i64 a0,fa0##in_ty=f64 tmp=ft4
+;   fcvt_to_sint.i64 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
 
 function %f41(i32) -> f32 {
@@ -501,7 +501,7 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvt_to_uint_sat.i32 a0,fa0##in_ty=f32 tmp=ft4
+;   fcvt_to_uint_sat.i32 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
 
 function %f50(f32) -> i32 {
@@ -511,7 +511,7 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvt_to_sint_sat.i32 a0,fa0##in_ty=f32 tmp=ft4
+;   fcvt_to_sint_sat.i32 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
 
 function %f51(f32) -> i64 {
@@ -521,7 +521,7 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvt_to_uint_sat.i64 a0,fa0##in_ty=f32 tmp=ft4
+;   fcvt_to_uint_sat.i64 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
 
 function %f52(f32) -> i64 {
@@ -531,7 +531,7 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvt_to_sint_sat.i64 a0,fa0##in_ty=f32 tmp=ft4
+;   fcvt_to_sint_sat.i64 a0,fa0##in_ty=f32 tmp=ft3
 ;   ret
 
 function %f53(f64) -> i32 {
@@ -541,7 +541,7 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvt_to_uint_sat.i32 a0,fa0##in_ty=f64 tmp=ft4
+;   fcvt_to_uint_sat.i32 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
 
 function %f54(f64) -> i32 {
@@ -551,7 +551,7 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvt_to_sint_sat.i32 a0,fa0##in_ty=f64 tmp=ft4
+;   fcvt_to_sint_sat.i32 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
 
 function %f55(f64) -> i64 {
@@ -561,7 +561,7 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvt_to_uint_sat.i64 a0,fa0##in_ty=f64 tmp=ft4
+;   fcvt_to_uint_sat.i64 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
 
 function %f56(f64) -> i64 {
@@ -571,6 +571,6 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvt_to_sint_sat.i64 a0,fa0##in_ty=f64 tmp=ft4
+;   fcvt_to_sint_sat.i64 a0,fa0##in_ty=f64 tmp=ft3
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/heap-addr.clif

@@ -13,16 +13,16 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   uext.w t3,a1
+;   uext.w a7,a1
-;   ld t4,0(a0)
+;   ld t3,0(a0)
-;   addi t4,t4,0
+;   addi t3,t3,0
-;   ule t0,t3,t4##ty=i64
+;   ule t4,a7,t3##ty=i64
-;   bne t0,zero,taken(label1),not_taken(label2)
+;   bne t4,zero,taken(label1),not_taken(label2)
 ; block1:
-;   add t0,a0,t3
+;   add t4,a0,a7
-;   ugt t3,t3,t4##ty=i64
+;   ugt a7,a7,t3##ty=i64
-;   li t1,0
+;   li t0,0
-;   selectif_spectre_guard a0,t1,t0##test=t3
+;   selectif_spectre_guard a0,t0,t4##test=a7
 ;   ret
 ; block2:
 ;   udf##trap_code=heap_oob
@@ -37,16 +37,16 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   uext.w t3,a1
+;   uext.w a7,a1
-;   lui a7,16
+;   lui a6,16
-;   ule t4,t3,a7##ty=i64
+;   ule t3,a7,a6##ty=i64
-;   bne t4,zero,taken(label1),not_taken(label2)
+;   bne t3,zero,taken(label1),not_taken(label2)
 ; block1:
-;   add t4,a0,t3
+;   add t3,a0,a7
-;   lui a7,16
+;   lui a6,16
-;   ugt t0,t3,a7##ty=i64
+;   ugt t4,a7,a6##ty=i64
-;   li t1,0
+;   li t0,0
-;   selectif_spectre_guard a0,t1,t4##test=t0
+;   selectif_spectre_guard a0,t0,t3##test=t4
 ;   ret
 ; block2:
 ;   udf##trap_code=heap_oob

cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif

@@ -9,9 +9,9 @@ block0(v0: i128):
 }
 
 ; block0:
-;   or a2,a0,a1
+;   or a0,a0,a1
-;   li a4,-1
+;   li a2,-1
-;   select_reg a1,zero,a4##condition=(zero eq a2)
+;   select_reg a1,zero,a2##condition=(zero eq a0)
 ;   mv a0,a1
 ;   ret
 
@@ -22,9 +22,9 @@ block0(v0: i128):
 }
 
 ; block0:
-;   or a1,a0,a1
+;   or a0,a0,a1
-;   li a3,-1
+;   li a2,-1
-;   select_reg a0,zero,a3##condition=(zero eq a1)
+;   select_reg a0,zero,a2##condition=(zero eq a0)
 ;   ret
 
 function %bmask_i128_i32(i128) -> i32 {
@@ -34,9 +34,9 @@ block0(v0: i128):
 }
 
 ; block0:
-;   or a1,a0,a1
+;   or a0,a0,a1
-;   li a3,-1
+;   li a2,-1
-;   select_reg a0,zero,a3##condition=(zero eq a1)
+;   select_reg a0,zero,a2##condition=(zero eq a0)
 ;   ret
 
 function %bmask_i128_i16(i128) -> i16 {
@@ -46,9 +46,9 @@ block0(v0: i128):
 }
 
 ; block0:
-;   or a1,a0,a1
+;   or a0,a0,a1
-;   li a3,-1
+;   li a2,-1
-;   select_reg a0,zero,a3##condition=(zero eq a1)
+;   select_reg a0,zero,a2##condition=(zero eq a0)
 ;   ret
 
 function %bmask_i128_i8(i128) -> i8 {
@@ -58,9 +58,9 @@ block0(v0: i128):
 }
 
 ; block0:
-;   or a1,a0,a1
+;   or a0,a0,a1
-;   li a3,-1
+;   li a2,-1
-;   select_reg a0,zero,a3##condition=(zero eq a1)
+;   select_reg a0,zero,a2##condition=(zero eq a0)
 ;   ret
 
 function %bmask_i64_i128(i64) -> i128 {
@@ -70,8 +70,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,-1
+;   li t2,-1
-;   select_reg a1,zero,a1##condition=(zero eq a0)
+;   select_reg a1,zero,t2##condition=(zero eq a0)
 ;   mv a0,a1
 ;   ret
 
@@ -82,9 +82,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   addiw a1,a0,0
+;   addiw t2,a0,0
-;   li a3,-1
+;   li a1,-1
-;   select_reg a1,zero,a3##condition=(zero eq a1)
+;   select_reg a1,zero,a1##condition=(zero eq t2)
 ;   mv a0,a1
 ;   ret
 
@@ -95,11 +95,11 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lui a1,16
+;   lui t2,16
-;   addi a1,a1,4095
+;   addi t2,t2,4095
-;   and a4,a0,a1
+;   and a2,a0,t2
-;   li a6,-1
+;   li a4,-1
-;   select_reg a1,zero,a6##condition=(zero eq a4)
+;   select_reg a1,zero,a4##condition=(zero eq a2)
 ;   mv a0,a1
 ;   ret
 
@@ -110,9 +110,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   andi a1,a0,255
+;   andi t2,a0,255
-;   li a3,-1
+;   li a1,-1
-;   select_reg a1,zero,a3##condition=(zero eq a1)
+;   select_reg a1,zero,a1##condition=(zero eq t2)
 ;   mv a0,a1
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif

@@ -11,12 +11,12 @@ block0:
 }
 
 ; block0:
-;   lui t1,14
+;   lui t0,14
-;   addi t1,t1,3532
+;   addi t0,t0,3532
-;   lui a1,14
+;   lui a0,14
-;   addi a1,a1,3532
+;   addi a0,a0,3532
-;   uext.h a4,t1
+;   uext.h a3,t0
-;   uext.h a6,a1
+;   uext.h a5,a0
-;   ne a0,a4,a6##ty=i16
+;   ne a0,a3,a5##ty=i16
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/narrow-arithmetic.clif

@@ -40,8 +40,8 @@ block0(v0: i32, v1: i8):
 }
 
 ; block0:
-;   sext.b a2,a1
+;   sext.b a1,a1
-;   addw a0,a0,a2
+;   addw a0,a0,a1
 ;   ret
 
 function %add64_32(i64, i32) -> i64 {
@@ -52,7 +52,7 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   sext.w a2,a1
+;   sext.w a1,a1
-;   add a0,a0,a2
+;   add a0,a0,a1
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/prologue.clif

@@ -92,6 +92,7 @@ block0(v0: f64):
 ;   fsd fs11,-88(sp)
 ;   add sp,-96
 ; block0:
+;   fadd.d ft3,fa0,fa0
 ;   fadd.d ft4,fa0,fa0
 ;   fadd.d ft5,fa0,fa0
 ;   fadd.d ft6,fa0,fa0
@@ -110,7 +111,7 @@ block0(v0: f64):
 ;   fadd.d ft0,fa0,fa0
 ;   fadd.d ft1,fa0,fa0
 ;   fadd.d ft2,fa0,fa0
-;   fadd.d ft3,fa0,fa0
+;   fadd.d fs3,fa0,fa0
 ;   fadd.d fs4,fa0,fa0
 ;   fadd.d fs5,fa0,fa0
 ;   fadd.d fs6,fa0,fa0
@@ -122,38 +123,37 @@ block0(v0: f64):
 ;   fadd.d fs0,fa0,fa0
 ;   fadd.d fs1,fa0,fa0
 ;   fadd.d fs2,fa0,fa0
-;   fadd.d fs3,fa0,fa0
+;   fadd.d ft3,fa0,ft3
-;   fadd.d ft4,fa0,ft4
-;   fadd.d ft5,ft5,ft6
-;   fadd.d ft6,ft7,fa1
-;   fadd.d ft7,fa2,fa3
-;   fadd.d fa0,fa4,fa5
-;   fadd.d fa1,fa6,fa7
-;   fadd.d fa2,ft8,ft9
-;   fadd.d fa3,ft10,ft11
-;   fadd.d fa4,ft0,ft1
-;   fadd.d fa5,ft2,ft3
-;   fadd.d fa6,fs4,fs5
-;   fadd.d fa7,fs6,fs7
-;   fadd.d ft8,fs8,fs9
-;   fadd.d ft9,fs10,fs11
-;   fadd.d ft10,fs0,fs1
-;   fadd.d ft11,fs2,fs3
 ;   fadd.d ft4,ft4,ft5
 ;   fadd.d ft5,ft6,ft7
-;   fadd.d ft6,fa0,fa1
+;   fadd.d ft6,fa1,fa2
-;   fadd.d ft7,fa2,fa3
+;   fadd.d ft7,fa3,fa4
-;   fadd.d fa0,fa4,fa5
+;   fadd.d fa0,fa5,fa6
-;   fadd.d fa1,fa6,fa7
+;   fadd.d fa1,fa7,ft8
-;   fadd.d fa2,ft8,ft9
+;   fadd.d fa2,ft9,ft10
-;   fadd.d fa3,ft10,ft11
+;   fadd.d fa3,ft11,ft0
-;   fadd.d ft4,ft4,ft5
+;   fadd.d fa4,ft1,ft2
-;   fadd.d ft5,ft6,ft7
+;   fadd.d fa5,fs3,fs4
-;   fadd.d ft6,fa0,fa1
+;   fadd.d fa6,fs5,fs6
-;   fadd.d ft7,fa2,fa3
+;   fadd.d fa7,fs7,fs8
-;   fadd.d ft4,ft4,ft5
+;   fadd.d ft8,fs9,fs10
-;   fadd.d ft5,ft6,ft7
+;   fadd.d ft9,fs11,fs0
-;   fadd.d fa0,ft4,ft5
+;   fadd.d ft10,fs1,fs2
+;   fadd.d ft3,ft3,ft4
+;   fadd.d ft4,ft5,ft6
+;   fadd.d ft5,ft7,fa0
+;   fadd.d ft6,fa1,fa2
+;   fadd.d ft7,fa3,fa4
+;   fadd.d fa0,fa5,fa6
+;   fadd.d fa1,fa7,ft8
+;   fadd.d fa2,ft9,ft10
+;   fadd.d ft3,ft3,ft4
+;   fadd.d ft4,ft5,ft6
+;   fadd.d ft5,ft7,fa0
+;   fadd.d ft6,fa1,fa2
+;   fadd.d ft3,ft3,ft4
+;   fadd.d ft4,ft5,ft6
+;   fadd.d fa0,ft3,ft4
 ;   add sp,+96
 ;   fld fs0,-8(sp)
 ;   fld fs2,-16(sp)
@@ -221,15 +221,16 @@ block0(v0: i64):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s6,-8(sp)
+;   sd s5,-8(sp)
-;   sd s7,-16(sp)
+;   sd s6,-16(sp)
-;   sd s8,-24(sp)
+;   sd s7,-24(sp)
-;   sd s9,-32(sp)
+;   sd s8,-32(sp)
-;   sd s10,-40(sp)
+;   sd s9,-40(sp)
-;   sd s11,-48(sp)
+;   sd s10,-48(sp)
 ;   add sp,-48
 ; block0:
-;   add t4,a0,a0
+;   add t3,a0,a0
+;   add t4,a0,t3
 ;   add t0,a0,t4
 ;   add t1,a0,t0
 ;   add t2,a0,t1
@@ -240,38 +241,37 @@ block0(v0: i64):
 ;   add a5,a0,a4
 ;   add a6,a0,a5
 ;   add a7,a0,a6
-;   add t3,a0,a7
+;   add s5,a0,a7
-;   add s6,a0,t3
+;   add s6,a0,s5
 ;   add s7,a0,s6
 ;   add s8,a0,s7
 ;   add s9,a0,s8
 ;   add s10,a0,s9
-;   add s11,a0,s10
+;   add t3,a0,t3
-;   add t4,a0,t4
-;   add t0,t0,t1
-;   add t1,t2,a1
-;   add t2,a2,a3
-;   add a0,a4,a5
-;   add a1,a6,a7
-;   add a2,t3,s6
-;   add a3,s7,s8
-;   add a4,s9,s10
-;   add t4,s11,t4
-;   add t0,t0,t1
-;   add t1,t2,a0
-;   add t2,a1,a2
-;   add a0,a3,a4
 ;   add t4,t4,t0
 ;   add t0,t1,t2
-;   add t4,a0,t4
+;   add t1,a1,a2
-;   add a0,t0,t4
+;   add t2,a3,a4
+;   add a0,a5,a6
+;   add a1,a7,s5
+;   add a2,s6,s7
+;   add a3,s8,s9
+;   add t3,s10,t3
+;   add t4,t4,t0
+;   add t0,t1,t2
+;   add t1,a0,a1
+;   add t2,a2,a3
+;   add t3,t3,t4
+;   add t4,t0,t1
+;   add t3,t2,t3
+;   add a0,t4,t3
 ;   add sp,+48
-;   ld s6,-8(sp)
+;   ld s5,-8(sp)
-;   ld s7,-16(sp)
+;   ld s6,-16(sp)
-;   ld s8,-24(sp)
+;   ld s7,-24(sp)
-;   ld s9,-32(sp)
+;   ld s8,-32(sp)
-;   ld s10,-40(sp)
+;   ld s9,-40(sp)
-;   ld s11,-48(sp)
+;   ld s10,-48(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16

cranelift/filetests/filetests/isa/riscv64/reftypes.clif

@@ -65,38 +65,38 @@ block3(v7: r64, v8: r64):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   sd s10,-8(sp)
+;   sd s7,-8(sp)
 ;   add sp,-48
 ; block0:
 ;   sd a0,8(nominal_sp)
 ;   sd a1,16(nominal_sp)
-;   mv s10,a2
+;   mv s7,a2
-;   load_sym a4,%f+0
+;   load_sym a1,%f+0
-;   callind a4
+;   callind a1
-;   load_addr a3,nsp+0
+;   load_addr a1,nsp+0
-;   ld t2,8(nominal_sp)
+;   ld t4,8(nominal_sp)
-;   sd t2,0(a3)
+;   sd t4,0(a1)
-;   andi a4,a0,255
+;   andi a1,a0,255
-;   beq a4,zero,taken(label1),not_taken(label3)
+;   beq a1,zero,taken(label1),not_taken(label3)
 ; block1:
 ;   j label2
 ; block2:
-;   mv a1,t2
+;   mv a1,t4
 ;   ld a0,16(nominal_sp)
 ;   j label5
 ; block3:
 ;   j label4
 ; block4:
-;   mv a0,t2
+;   mv a0,t4
 ;   ld a1,16(nominal_sp)
 ;   j label5
 ; block5:
-;   load_addr a5,nsp+0
+;   load_addr a2,nsp+0
-;   ld a5,0(a5)
+;   ld a2,0(a2)
-;   mv a2,s10
+;   mv a3,s7
-;   sd a5,0(a2)
+;   sd a2,0(a3)
 ;   add sp,+48
-;   ld s10,-8(sp)
+;   ld s7,-8(sp)
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16

cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif

@@ -13,20 +13,20 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   andi a4,a2,127
+;   andi a2,a2,127
-;   li a6,128
+;   li a4,128
-;   sub a6,a6,a4
+;   sub a4,a4,a2
-;   srl t4,a0,a4
+;   srl a7,a0,a2
-;   sll t1,a1,a6
+;   sll t4,a1,a4
-;   select_reg a2,zero,t1##condition=(a4 eq zero)
+;   select_reg t1,zero,t4##condition=(a2 eq zero)
-;   or a2,t4,a2
+;   or a3,a7,t1
-;   srl a5,a1,a4
+;   srl a5,a1,a2
-;   sll a6,a0,a6
+;   sll a4,a0,a4
-;   select_reg t3,zero,a6##condition=(a4 eq zero)
+;   select_reg a6,zero,a4##condition=(a2 eq zero)
-;   or t0,a5,t3
+;   or t3,a5,a6
-;   li t2,64
+;   li t0,64
-;   select_reg a0,t0,a2##condition=(a4 uge t2)
+;   select_reg a0,t3,a3##condition=(a2 uge t0)
-;   select_reg a1,a2,t0##condition=(a4 uge t2)
+;   select_reg a1,a3,t3##condition=(a2 uge t0)
 ;   ret
 
 function %f0(i64, i64) -> i64 {
@@ -36,13 +36,15 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   andi a1,a1,63
+;   mv a6,a0
-;   li a3,64
+;   andi a0,a1,63
-;   sub a3,a3,a1
+;   li a2,64
-;   srl a6,a0,a1
+;   sub a2,a2,a0
-;   sll t3,a0,a3
+;   mv t4,a6
-;   select_reg t0,zero,t3##condition=(a1 eq zero)
+;   srl a5,t4,a0
-;   or a0,a6,t0
+;   sll a7,t4,a2
+;   select_reg t4,zero,a7##condition=(a0 eq zero)
+;   or a0,a5,t4
 ;   ret
 
 function %f1(i32, i32) -> i32 {
@@ -52,14 +54,14 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   uext.w a2,a0
+;   uext.w a0,a0
-;   andi a3,a1,31
+;   andi a2,a1,31
-;   li a5,32
+;   li a4,32
-;   sub a5,a5,a3
+;   sub a4,a4,a2
-;   srl t3,a2,a3
+;   srl a7,a0,a2
-;   sll t0,a2,a5
+;   sll t4,a0,a4
-;   select_reg t2,zero,t0##condition=(a3 eq zero)
+;   select_reg t1,zero,t4##condition=(a2 eq zero)
-;   or a0,t3,t2
+;   or a0,a7,t1
 ;   ret
 
 function %f2(i16, i16) -> i16 {
@@ -69,14 +71,14 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   uext.h a2,a0
+;   uext.h a0,a0
-;   andi a3,a1,15
+;   andi a2,a1,15
-;   li a5,16
+;   li a4,16
-;   sub a5,a5,a3
+;   sub a4,a4,a2
-;   srl t3,a2,a3
+;   srl a7,a0,a2
-;   sll t0,a2,a5
+;   sll t4,a0,a4
-;   select_reg t2,zero,t0##condition=(a3 eq zero)
+;   select_reg t1,zero,t4##condition=(a2 eq zero)
-;   or a0,t3,t2
+;   or a0,a7,t1
 ;   ret
 
 function %f3(i8, i8) -> i8 {
@@ -86,14 +88,14 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   uext.b a2,a0
+;   uext.b a0,a0
-;   andi a3,a1,7
+;   andi a2,a1,7
-;   li a5,8
+;   li a4,8
-;   sub a5,a5,a3
+;   sub a4,a4,a2
-;   srl t3,a2,a3
+;   srl a7,a0,a2
-;   sll t0,a2,a5
+;   sll t4,a0,a4
-;   select_reg t2,zero,t0##condition=(a3 eq zero)
+;   select_reg t1,zero,t4##condition=(a2 eq zero)
-;   or a0,t3,t2
+;   or a0,a7,t1
 ;   ret
 
 function %i128_rotl(i128, i128) -> i128 {
@@ -103,20 +105,20 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   andi a4,a2,127
+;   andi a2,a2,127
-;   li a6,128
+;   li a4,128
-;   sub a6,a6,a4
+;   sub a4,a4,a2
-;   sll t4,a0,a4
+;   sll a7,a0,a2
-;   srl t1,a1,a6
+;   srl t4,a1,a4
-;   select_reg a2,zero,t1##condition=(a4 eq zero)
+;   select_reg t1,zero,t4##condition=(a2 eq zero)
-;   or a2,t4,a2
+;   or a3,a7,t1
-;   sll a5,a1,a4
+;   sll a5,a1,a2
-;   srl a6,a0,a6
+;   srl a4,a0,a4
-;   select_reg t3,zero,a6##condition=(a4 eq zero)
+;   select_reg a6,zero,a4##condition=(a2 eq zero)
-;   or t0,a5,t3
+;   or t3,a5,a6
-;   li t2,64
+;   li t0,64
-;   select_reg a0,t0,a2##condition=(a4 uge t2)
+;   select_reg a0,t3,a3##condition=(a2 uge t0)
-;   select_reg a1,a2,t0##condition=(a4 uge t2)
+;   select_reg a1,a3,t3##condition=(a2 uge t0)
 ;   ret
 
 function %f4(i64, i64) -> i64 {
@@ -126,13 +128,15 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   andi a1,a1,63
+;   mv a6,a0
-;   li a3,64
+;   andi a0,a1,63
-;   sub a3,a3,a1
+;   li a2,64
-;   sll a6,a0,a1
+;   sub a2,a2,a0
-;   srl t3,a0,a3
+;   mv t4,a6
-;   select_reg t0,zero,t3##condition=(a1 eq zero)
+;   sll a5,t4,a0
-;   or a0,a6,t0
+;   srl a7,t4,a2
+;   select_reg t4,zero,a7##condition=(a0 eq zero)
+;   or a0,a5,t4
 ;   ret
 
 function %f5(i32, i32) -> i32 {
@@ -142,14 +146,14 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   uext.w a2,a0
+;   uext.w a0,a0
-;   andi a3,a1,31
+;   andi a2,a1,31
-;   li a5,32
+;   li a4,32
-;   sub a5,a5,a3
+;   sub a4,a4,a2
-;   sll t3,a2,a3
+;   sll a7,a0,a2
-;   srl t0,a2,a5
+;   srl t4,a0,a4
-;   select_reg t2,zero,t0##condition=(a3 eq zero)
+;   select_reg t1,zero,t4##condition=(a2 eq zero)
-;   or a0,t3,t2
+;   or a0,a7,t1
 ;   ret
 
 function %f6(i16, i16) -> i16 {
@@ -159,14 +163,14 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   uext.h a2,a0
+;   uext.h a0,a0
-;   andi a3,a1,15
+;   andi a2,a1,15
-;   li a5,16
+;   li a4,16
-;   sub a5,a5,a3
+;   sub a4,a4,a2
-;   sll t3,a2,a3
+;   sll a7,a0,a2
-;   srl t0,a2,a5
+;   srl t4,a0,a4
-;   select_reg t2,zero,t0##condition=(a3 eq zero)
+;   select_reg t1,zero,t4##condition=(a2 eq zero)
-;   or a0,t3,t2
+;   or a0,a7,t1
 ;   ret
 
 function %f7(i8, i8) -> i8 {
@@ -176,14 +180,14 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   uext.b a2,a0
+;   uext.b a0,a0
-;   andi a3,a1,7
+;   andi a2,a1,7
-;   li a5,8
+;   li a4,8
-;   sub a5,a5,a3
+;   sub a4,a4,a2
-;   sll t3,a2,a3
+;   sll a7,a0,a2
-;   srl t0,a2,a5
+;   srl t4,a0,a4
-;   select_reg t2,zero,t0##condition=(a3 eq zero)
+;   select_reg t1,zero,t4##condition=(a2 eq zero)
-;   or a0,t3,t2
+;   or a0,a7,t1
 ;   ret
 
 function %f8(i64, i64) -> i64 {
@@ -213,10 +217,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   mv a5,a1
+;   uext.h a0,a0
-;   uext.h a1,a0
+;   andi a2,a1,15
-;   andi a3,a5,15
+;   srlw a0,a0,a2
-;   srlw a0,a1,a3
 ;   ret
 
 function %f11(i8, i8) -> i8 {
@@ -226,10 +229,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   mv a5,a1
+;   uext.b a0,a0
-;   uext.b a1,a0
+;   andi a2,a1,7
-;   andi a3,a5,7
+;   srlw a0,a0,a2
-;   srlw a0,a1,a3
 ;   ret
 
 function %f12(i64, i64) -> i64 {
@@ -301,10 +303,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   mv a5,a1
+;   sext.h a0,a0
-;   sext.h a1,a0
+;   andi a2,a1,15
-;   andi a3,a5,15
+;   sra a0,a0,a2
-;   sra a0,a1,a3
 ;   ret
 
 function %f19(i8, i8) -> i8 {
@@ -314,10 +315,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   mv a5,a1
+;   sext.b a0,a0
-;   sext.b a1,a0
+;   andi a2,a1,7
-;   andi a3,a5,7
+;   sra a0,a0,a2
-;   sra a0,a1,a3
 ;   ret
 
 function %f20(i64) -> i64 {
@@ -328,14 +328,14 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,17
+;   li t2,17
-;   andi a2,a1,63
+;   andi a1,t2,63
-;   li a4,64
+;   li a3,64
-;   sub a4,a4,a2
+;   sub a3,a3,a1
-;   srl a7,a0,a2
+;   srl a6,a0,a1
-;   sll t4,a0,a4
+;   sll t3,a0,a3
-;   select_reg t1,zero,t4##condition=(a2 eq zero)
+;   select_reg t0,zero,t3##condition=(a1 eq zero)
-;   or a0,a7,t1
+;   or a0,a6,t0
 ;   ret
 
 function %f21(i64) -> i64 {
@@ -346,14 +346,14 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,17
+;   li t2,17
-;   andi a2,a1,63
+;   andi a1,t2,63
-;   li a4,64
+;   li a3,64
-;   sub a4,a4,a2
+;   sub a3,a3,a1
-;   sll a7,a0,a2
+;   sll a6,a0,a1
-;   srl t4,a0,a4
+;   srl t3,a0,a3
-;   select_reg t1,zero,t4##condition=(a2 eq zero)
+;   select_reg t0,zero,t3##condition=(a1 eq zero)
-;   or a0,a7,t1
+;   or a0,a6,t0
 ;   ret
 
 function %f22(i32) -> i32 {
@@ -364,16 +364,15 @@ block0(v0: i32):
 }
 
 ; block0:
-;   mv t4,a0
+;   li t2,17
-;   li a0,17
+;   uext.w a1,a0
-;   uext.w a2,t4
+;   andi a3,t2,31
-;   andi a4,a0,31
+;   li a5,32
-;   li a6,32
+;   sub a5,a5,a3
-;   sub a6,a6,a4
+;   sll t3,a1,a3
-;   sll t4,a2,a4
+;   srl t0,a1,a5
-;   srl t1,a2,a6
+;   select_reg t2,zero,t0##condition=(a3 eq zero)
-;   select_reg a0,zero,t1##condition=(a4 eq zero)
+;   or a0,t3,t2
-;   or a0,t4,a0
 ;   ret
 
 function %f23(i16) -> i16 {
@@ -384,16 +383,15 @@ block0(v0: i16):
 }
 
 ; block0:
-;   mv t4,a0
+;   li t2,10
-;   li a0,10
+;   uext.h a1,a0
-;   uext.h a2,t4
+;   andi a3,t2,15
-;   andi a4,a0,15
+;   li a5,16
-;   li a6,16
+;   sub a5,a5,a3
-;   sub a6,a6,a4
+;   sll t3,a1,a3
-;   sll t4,a2,a4
+;   srl t0,a1,a5
-;   srl t1,a2,a6
+;   select_reg t2,zero,t0##condition=(a3 eq zero)
-;   select_reg a0,zero,t1##condition=(a4 eq zero)
+;   or a0,t3,t2
-;   or a0,t4,a0
 ;   ret
 
 function %f24(i8) -> i8 {
@@ -404,16 +402,15 @@ block0(v0: i8):
 }
 
 ; block0:
-;   mv t4,a0
+;   li t2,3
-;   li a0,3
+;   uext.b a1,a0
-;   uext.b a2,t4
+;   andi a3,t2,7
-;   andi a4,a0,7
+;   li a5,8
-;   li a6,8
+;   sub a5,a5,a3
-;   sub a6,a6,a4
+;   sll t3,a1,a3
-;   sll t4,a2,a4
+;   srl t0,a1,a5
-;   srl t1,a2,a6
+;   select_reg t2,zero,t0##condition=(a3 eq zero)
-;   select_reg a0,zero,t1##condition=(a4 eq zero)
+;   or a0,t3,t2
-;   or a0,t4,a0
 ;   ret
 
 function %f25(i64) -> i64 {

cranelift/filetests/filetests/isa/riscv64/stack.clif

@@ -62,8 +62,8 @@ block0:
 ;   mv fp,sp
 ;   add sp,-16
 ; block0:
-;   load_addr t2,nsp+0
+;   load_addr t1,nsp+0
-;   ld a0,0(t2)
+;   ld a0,0(t1)
 ;   add sp,+16
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
@@ -88,8 +88,8 @@ block0:
 ;   call %Probestack
 ;   add sp,-100016
 ; block0:
-;   load_addr t2,nsp+0
+;   load_addr t1,nsp+0
-;   ld a0,0(t2)
+;   ld a0,0(t1)
 ;   add sp,+100016
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
@@ -313,152 +313,152 @@ block0(v0: i8):
 ;   add sp,-1280
 ; block0:
 ;   sd a0,1000(nominal_sp)
-;   li t0,2
+;   li t3,2
-;   addi a1,t0,1
+;   addi t1,t3,1
-;   sd a1,1176(nominal_sp)
+;   sd t1,1176(nominal_sp)
-;   li t0,4
+;   li t3,4
-;   addi a2,t0,3
+;   addi t2,t3,3
-;   sd a2,1168(nominal_sp)
+;   sd t2,1168(nominal_sp)
-;   li t0,6
+;   li t3,6
-;   addi a3,t0,5
+;   addi a1,t3,5
-;   sd a3,1160(nominal_sp)
+;   sd a1,1160(nominal_sp)
-;   li t0,8
+;   li t3,8
-;   addi a4,t0,7
+;   addi a2,t3,7
-;   sd a4,1152(nominal_sp)
+;   sd a2,1152(nominal_sp)
-;   li t0,10
+;   li t3,10
-;   addi a5,t0,9
+;   addi a3,t3,9
-;   sd a5,1144(nominal_sp)
+;   sd a3,1144(nominal_sp)
-;   li t0,12
+;   li t3,12
-;   addi a6,t0,11
+;   addi a4,t3,11
-;   sd a6,1136(nominal_sp)
+;   sd a4,1136(nominal_sp)
-;   li t0,14
+;   li t3,14
-;   addi a7,t0,13
+;   addi a5,t3,13
-;   sd a7,1128(nominal_sp)
+;   sd a5,1128(nominal_sp)
-;   li t0,16
+;   li t3,16
-;   addi t3,t0,15
+;   addi a6,t3,15
-;   sd t3,1120(nominal_sp)
+;   sd a6,1120(nominal_sp)
-;   li t0,18
+;   li t3,18
-;   addi t4,t0,17
+;   addi a7,t3,17
-;   sd t4,1112(nominal_sp)
+;   sd a7,1112(nominal_sp)
-;   li t0,20
+;   li t3,20
-;   addi t0,t0,19
+;   addi t3,t3,19
-;   sd t0,1104(nominal_sp)
+;   sd t3,1104(nominal_sp)
-;   li t0,22
+;   li t3,22
-;   addi t1,t0,21
+;   addi t4,t3,21
-;   sd t1,1096(nominal_sp)
+;   sd t4,1096(nominal_sp)
-;   li t0,24
+;   li t3,24
-;   addi s8,t0,23
+;   addi s6,t3,23
-;   sd s8,1088(nominal_sp)
+;   sd s6,1088(nominal_sp)
-;   li t0,26
+;   li t3,26
-;   addi s9,t0,25
+;   addi s7,t3,25
-;   sd s9,1080(nominal_sp)
+;   sd s7,1080(nominal_sp)
-;   li t0,28
+;   li t3,28
-;   addi s10,t0,27
+;   addi s8,t3,27
-;   sd s10,1072(nominal_sp)
+;   sd s8,1072(nominal_sp)
-;   li t0,30
+;   li t3,30
-;   addi s11,t0,29
+;   addi s9,t3,29
-;   sd s11,1064(nominal_sp)
+;   sd s9,1064(nominal_sp)
-;   li t0,32
+;   li t3,32
-;   addi s1,t0,31
+;   addi s10,t3,31
-;   sd s1,1056(nominal_sp)
+;   sd s10,1056(nominal_sp)
-;   li t0,34
+;   li t3,34
-;   addi s2,t0,33
+;   addi s11,t3,33
-;   sd s2,1048(nominal_sp)
+;   sd s11,1048(nominal_sp)
-;   li t0,36
+;   li t3,36
-;   addi s3,t0,35
+;   addi s1,t3,35
-;   sd s3,1040(nominal_sp)
+;   sd s1,1040(nominal_sp)
-;   li t0,38
+;   li t3,38
-;   addi s4,t0,37
+;   addi s2,t3,37
-;   sd s4,1032(nominal_sp)
+;   sd s2,1032(nominal_sp)
-;   li t0,30
+;   li t3,30
-;   addi s5,t0,39
+;   addi s3,t3,39
-;   sd s5,1024(nominal_sp)
+;   sd s3,1024(nominal_sp)
-;   li t0,32
+;   li t3,32
-;   addi s6,t0,31
+;   addi s4,t3,31
-;   sd s6,1016(nominal_sp)
+;   sd s4,1016(nominal_sp)
-;   li t0,34
+;   li t3,34
-;   addi s7,t0,33
+;   addi s5,t3,33
-;   sd s7,1008(nominal_sp)
+;   sd s5,1008(nominal_sp)
-;   li t0,36
+;   li t3,36
-;   addi s7,t0,35
+;   addi s5,t3,35
-;   li t0,38
+;   li t3,38
-;   addi a0,t0,37
+;   addi a0,t3,37
-;   li t0,30
+;   li t3,30
-;   addi t2,t0,39
+;   addi t0,t3,39
-;   li t0,32
+;   li t3,32
-;   addi a1,t0,31
+;   addi t1,t3,31
-;   li t0,34
+;   li t3,34
-;   addi a2,t0,33
+;   addi t2,t3,33
-;   li t0,36
+;   li t3,36
-;   addi a3,t0,35
+;   addi a1,t3,35
-;   li t0,38
+;   li t3,38
-;   addi a4,t0,37
+;   addi a2,t3,37
-;   li t0,30
+;   li t3,30
-;   addi a5,t0,39
+;   addi a3,t3,39
-;   li t0,32
+;   li t3,32
-;   addi a6,t0,31
+;   addi a4,t3,31
-;   li t0,34
+;   li t3,34
-;   addi a7,t0,33
+;   addi a5,t3,33
-;   li t0,36
+;   li t3,36
-;   addi t3,t0,35
+;   addi a6,t3,35
-;   li t0,38
+;   li t3,38
-;   addi t4,t0,37
+;   addi a7,t3,37
-;   ld t0,1176(nominal_sp)
+;   ld t3,1176(nominal_sp)
-;   addi t0,t0,39
+;   addi t3,t3,39
-;   ld t1,1160(nominal_sp)
+;   ld t4,1160(nominal_sp)
-;   ld s4,1168(nominal_sp)
+;   ld s2,1168(nominal_sp)
-;   add t1,s4,t1
+;   add t4,s2,t4
-;   ld s11,1144(nominal_sp)
+;   ld s9,1144(nominal_sp)
-;   ld s9,1152(nominal_sp)
+;   ld s7,1152(nominal_sp)
-;   add s8,s9,s11
+;   add s6,s7,s9
-;   ld s5,1128(nominal_sp)
+;   ld s3,1128(nominal_sp)
-;   ld s3,1136(nominal_sp)
+;   ld s1,1136(nominal_sp)
-;   add s9,s3,s5
+;   add s7,s1,s3
-;   ld s10,1112(nominal_sp)
+;   ld s8,1112(nominal_sp)
-;   ld s11,1120(nominal_sp)
+;   ld s9,1120(nominal_sp)
+;   add s8,s9,s8
+;   ld s2,1096(nominal_sp)
+;   ld s11,1104(nominal_sp)
+;   add s9,s11,s2
+;   ld s10,1080(nominal_sp)
+;   ld s11,1088(nominal_sp)
 ;   add s10,s11,s10
-;   ld s4,1096(nominal_sp)
+;   ld s1,1064(nominal_sp)
-;   ld s2,1104(nominal_sp)
+;   ld s11,1072(nominal_sp)
-;   add s11,s2,s4
+;   add s11,s11,s1
-;   ld s1,1080(nominal_sp)
+;   ld s1,1048(nominal_sp)
-;   ld s2,1088(nominal_sp)
+;   ld s4,1056(nominal_sp)
-;   add s1,s2,s1
+;   add s1,s4,s1
-;   ld s3,1064(nominal_sp)
+;   ld s2,1032(nominal_sp)
-;   ld s2,1072(nominal_sp)
+;   ld s3,1040(nominal_sp)
-;   add s2,s2,s3
+;   add s2,s3,s2
-;   ld s3,1048(nominal_sp)
+;   ld s4,1016(nominal_sp)
-;   ld s6,1056(nominal_sp)
+;   ld s3,1024(nominal_sp)
-;   add s3,s6,s3
+;   add s3,s3,s4
-;   ld s4,1032(nominal_sp)
+;   ld s4,1008(nominal_sp)
-;   ld s5,1040(nominal_sp)
+;   add s5,s4,s5
-;   add s4,s5,s4
+;   add t0,a0,t0
-;   ld s6,1016(nominal_sp)
+;   add t1,t1,t2
-;   ld s5,1024(nominal_sp)
+;   add t2,a1,a2
-;   add s5,s5,s6
+;   add a0,a3,a4
-;   ld s6,1008(nominal_sp)
+;   add a1,a5,a6
-;   add s7,s6,s7
+;   add a2,a7,t3
-;   add t2,a0,t2
+;   add t4,t4,s6
-;   add a0,a1,a2
+;   add a3,s7,s8
-;   add a1,a3,a4
+;   add a4,s9,s10
-;   add a2,a5,a6
+;   add a5,s11,s1
-;   add a3,a7,t3
+;   add a6,s2,s3
-;   add a4,t4,t0
+;   add t0,s5,t0
-;   add t1,t1,s8
+;   add t1,t1,t2
-;   add a5,s9,s10
+;   add t2,a0,a1
-;   add a6,s11,s1
+;   add t4,a2,t4
-;   add a7,s2,s3
+;   add a0,a3,a4
-;   add t3,s4,s5
+;   add a1,a5,a6
-;   add t2,s7,t2
+;   add t0,t0,t1
-;   add a0,a0,a1
+;   add t4,t2,t4
-;   add a1,a2,a3
+;   add t1,a0,a1
-;   add t1,a4,t1
+;   add t4,t0,t4
-;   add a2,a5,a6
+;   add a1,t1,t4
-;   add a3,a7,t3
-;   add t2,t2,a0
-;   add t1,a1,t1
-;   add a0,a2,a3
-;   add t1,t2,t1
-;   add a1,a0,t1
 ;   ld a0,1000(nominal_sp)
 ;   add sp,+1280
 ;   ld s1,-8(sp)
@@ -568,9 +568,9 @@ block0:
 ;   mv fp,sp
 ;   add sp,-16
 ; block0:
-;   load_addr a1,nsp+0
+;   load_addr t2,nsp+0
-;   ld a0,0(a1)
+;   ld a0,0(t2)
-;   ld a1,8(a1)
+;   ld a1,8(t2)
 ;   add sp,+16
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
@@ -592,9 +592,9 @@ block0:
 ;   mv fp,sp
 ;   add sp,-32
 ; block0:
-;   load_addr a1,nsp+32
+;   load_addr t2,nsp+32
-;   ld a0,0(a1)
+;   ld a0,0(t2)
-;   ld a1,8(a1)
+;   ld a1,8(t2)
 ;   add sp,+32
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
@@ -619,9 +619,9 @@ block0:
 ;   call %Probestack
 ;   add sp,-100016
 ; block0:
-;   load_addr a1,nsp+0
+;   load_addr t2,nsp+0
-;   ld a0,0(a1)
+;   ld a0,0(t2)
-;   ld a1,8(a1)
+;   ld a1,8(t2)
 ;   add sp,+100016
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)

cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif

@@ -9,13 +9,12 @@ block0(v0: i32):
 }
 
 ; block0:
-;   mv a6,a0
+;   li t2,127
-;   li a0,127
+;   uext.w a1,a0
-;   uext.w a2,a6
+;   uext.w a3,t2
-;   uext.w a4,a0
+;   add a0,a1,a3
-;   add a0,a2,a4
+;   srli a7,a0,32
-;   srli t3,a0,32
+;   trap_if a7,user0
-;   trap_if t3,user0
 ;   ret
 
 function %f1(i32) -> i32 {
@@ -26,12 +25,12 @@ block0(v0: i32):
 }
 
 ; block0:
-;   li a1,127
+;   li t2,127
-;   uext.w a2,a1
+;   uext.w a1,t2
-;   uext.w a4,a0
+;   uext.w a3,a0
-;   add a0,a2,a4
+;   add a0,a1,a3
-;   srli t3,a0,32
+;   srli a7,a0,32
-;   trap_if t3,user0
+;   trap_if a7,user0
 ;   ret
 
 function %f2(i32, i32) -> i32 {
@@ -41,12 +40,11 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   mv a6,a1
+;   uext.w a0,a0
-;   uext.w a1,a0
+;   uext.w a2,a1
-;   uext.w a3,a6
+;   add a0,a0,a2
-;   add a0,a1,a3
+;   srli a6,a0,32
-;   srli a7,a0,32
+;   trap_if a6,user0
-;   trap_if a7,user0
 ;   ret
 
 function %f3(i64) -> i64 {
@@ -57,13 +55,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,127
+;   mv a4,a0
-;   add a2,a0,a1
+;   li t2,127
-;   mv a5,a2
+;   add a0,a4,t2
-;   ult a4,a5,a0##ty=i64
+;   ult a3,a0,a4##ty=i64
-;   mv a2,a5
+;   trap_if a3,user0
-;   trap_if a4,user0
-;   mv a0,a2
 ;   ret
 
 function %f3(i64) -> i64 {
@@ -74,10 +70,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   li a1,127
+;   li t2,127
-;   add a0,a1,a0
+;   add a0,t2,a0
-;   ult a4,a0,a1##ty=i64
+;   ult a3,a0,t2##ty=i64
-;   trap_if a4,user0
+;   trap_if a3,user0
 ;   ret
 
 function %f4(i64, i64) -> i64 {
@@ -88,10 +84,9 @@ block0(v0: i64, v1: i64):
 
 ; block0:
 ;   add a1,a0,a1
-;   mv a4,a1
+;   mv a3,a1
-;   ult a3,a4,a0##ty=i64
+;   ult a2,a3,a0##ty=i64
-;   mv a1,a4
+;   mv a0,a3
-;   trap_if a3,user0
+;   trap_if a2,user0
-;   mv a0,a1
 ;   ret
 

cranelift/filetests/filetests/isa/s390x/arithmetic.clif

@@ -10,8 +10,8 @@ block0(v0: i128, v1: i128):
 ; block0:
 ;   vl %v0, 0(%r3)
 ;   vl %v1, 0(%r4)
-;   vaq %v7, %v0, %v1
+;   vaq %v6, %v0, %v1
-;   vst %v7, 0(%r2)
+;   vst %v6, 0(%r2)
 ;   br %r14
 
 function %iadd_i64(i64, i64) -> i64 {
@@ -341,8 +341,8 @@ block0(v0: i128, v1: i128):
 ; block0:
 ;   vl %v0, 0(%r3)
 ;   vl %v1, 0(%r4)
-;   vsq %v7, %v0, %v1
+;   vsq %v6, %v0, %v1
-;   vst %v7, 0(%r2)
+;   vst %v6, 0(%r2)
 ;   br %r14
 
 function %isub_i64(i64, i64) -> i64 {
@@ -570,12 +570,12 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r3)
-;   vgbm %v5, 0
+;   vgbm %v4, 0
-;   vsq %v7, %v5, %v0
+;   vsq %v6, %v4, %v0
-;   vrepg %v17, %v0, 0
+;   vrepg %v16, %v0, 0
-;   vchg %v19, %v5, %v17
+;   vchg %v18, %v4, %v16
-;   vsel %v21, %v7, %v0, %v19
+;   vsel %v20, %v6, %v0, %v18
-;   vst %v21, 0(%r2)
+;   vst %v20, 0(%r2)
 ;   br %r14
 
 function %iabs_i64(i64) -> i64 {
@@ -616,8 +616,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lhr %r5, %r2
+;   lhr %r4, %r2
-;   lpr %r2, %r5
+;   lpr %r2, %r4
 ;   br %r14
 
 function %iabs_i8(i8) -> i8 {
@@ -627,8 +627,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lbr %r5, %r2
+;   lbr %r4, %r2
-;   lpr %r2, %r5
+;   lpr %r2, %r4
 ;   br %r14
 
 function %ineg_i128(i128) -> i128 {
@@ -639,9 +639,9 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r3)
-;   vgbm %v5, 0
+;   vgbm %v4, 0
-;   vsq %v7, %v5, %v0
+;   vsq %v6, %v4, %v0
-;   vst %v7, 0(%r2)
+;   vst %v6, 0(%r2)
 ;   br %r14
 
 function %ineg_i64(i64) -> i64 {
@@ -701,26 +701,26 @@ block0(v0: i128, v1: i128):
   return v2
 }
 
-;   stmg %r6, %r15, 48(%r15)
+;   stmg %r7, %r15, 56(%r15)
 ; block0:
-;   lgr %r6, %r2
+;   lgr %r14, %r2
 ;   vl %v0, 0(%r3)
 ;   vl %v1, 0(%r4)
-;   lgdr %r5, %f0
+;   lgdr %r4, %f0
-;   vlgvg %r4, %v0, 1
+;   vlgvg %r5, %v0, 1
-;   lgdr %r8, %f1
+;   lgdr %r7, %f1
-;   vlgvg %r10, %v1, 1
+;   vlgvg %r9, %v1, 1
-;   lgr %r3, %r4
+;   lgr %r3, %r5
-;   mlgr %r2, %r10
+;   mlgr %r2, %r9
-;   lgr %r9, %r2
+;   lgr %r8, %r2
-;   msgr %r4, %r8
+;   msgrkc %r2, %r5, %r7
-;   msgrkc %r2, %r5, %r10
+;   msgrkc %r5, %r4, %r9
-;   agr %r4, %r9
+;   agrk %r4, %r2, %r8
-;   agr %r2, %r4
+;   agr %r5, %r4
-;   vlvgp %v6, %r2, %r3
+;   vlvgp %v5, %r5, %r3
-;   lgr %r2, %r6
+;   lgr %r2, %r14
-;   vst %v6, 0(%r2)
+;   vst %v5, 0(%r2)
-;   lmg %r6, %r15, 48(%r15)
+;   lmg %r7, %r15, 56(%r15)
 ;   br %r14
 
 function %imul_i64(i64, i64) -> i64 {
@@ -936,10 +936,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   lgr %r4, %r2
+;   lgr %r5, %r3
-;   lgr %r2, %r3
+;   lgr %r3, %r2
-;   lgr %r3, %r4
+;   mlgr %r2, %r5
-;   mlgr %r2, %r2
 ;   br %r14
 
 function %umulhi_i32(i32, i32) -> i32 {
@@ -949,10 +948,10 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   llgfr %r2, %r2
+;   llgfr %r5, %r2
-;   llgfr %r4, %r3
+;   llgfr %r3, %r3
-;   msgr %r2, %r4
+;   msgr %r5, %r3
-;   srlg %r2, %r2, 32
+;   srlg %r2, %r5, 32
 ;   br %r14
 
 function %umulhi_i16(i16, i16) -> i16 {
@@ -962,10 +961,10 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   llhr %r2, %r2
+;   llhr %r5, %r2
-;   llhr %r4, %r3
+;   llhr %r3, %r3
-;   msr %r2, %r4
+;   msr %r5, %r3
-;   srlk %r2, %r2, 16
+;   srlk %r2, %r5, 16
 ;   br %r14
 
 function %umulhi_i8(i8, i8) -> i8 {
@@ -975,10 +974,10 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   llcr %r2, %r2
+;   llcr %r5, %r2
-;   llcr %r4, %r3
+;   llcr %r3, %r3
-;   msr %r2, %r4
+;   msr %r5, %r3
-;   srlk %r2, %r2, 8
+;   srlk %r2, %r5, 8
 ;   br %r14
 
 function %smulhi_i64(i64, i64) -> i64 {
@@ -998,10 +997,10 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   lgfr %r2, %r2
+;   lgfr %r5, %r2
-;   lgfr %r4, %r3
+;   lgfr %r3, %r3
-;   msgr %r2, %r4
+;   msgr %r5, %r3
-;   srag %r2, %r2, 32
+;   srag %r2, %r5, 32
 ;   br %r14
 
 function %smulhi_i16(i16, i16) -> i16 {
@@ -1011,10 +1010,10 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   lhr %r2, %r2
+;   lhr %r5, %r2
-;   lhr %r4, %r3
+;   lhr %r3, %r3
-;   msr %r2, %r4
+;   msr %r5, %r3
-;   srak %r2, %r2, 16
+;   srak %r2, %r5, 16
 ;   br %r14
 
 function %smulhi_i8(i8, i8) -> i8 {
@@ -1024,10 +1023,10 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lbr %r2, %r2
+;   lbr %r5, %r2
-;   lbr %r4, %r3
+;   lbr %r3, %r3
-;   msr %r2, %r4
+;   msr %r5, %r3
-;   srak %r2, %r2, 8
+;   srak %r2, %r5, 8
 ;   br %r14
 
 function %sdiv_i64(i64, i64) -> i64 {
@@ -1039,12 +1038,11 @@ block0(v0: i64, v1: i64):
 ; block0:
 ;   llihf %r4, 2147483647
 ;   iilf %r4, 4294967295
-;   xgr %r4, %r2
+;   xgrk %r5, %r4, %r2
-;   lgr %r5, %r2
+;   ngrk %r4, %r5, %r3
-;   ngr %r4, %r3
 ;   cgite %r4, -1
 ;   lgr %r4, %r3
-;   lgr %r3, %r5
+;   lgr %r3, %r2
 ;   dsgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
@@ -1058,8 +1056,8 @@ block0(v0: i64):
 
 ; block0:
 ;   lgr %r3, %r2
-;   lghi %r5, 2
+;   lghi %r4, 2
-;   dsgr %r2, %r5
+;   dsgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -1069,16 +1067,18 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+;   stmg %r7, %r15, 56(%r15)
 ; block0:
-;   lgr %r5, %r3
+;   lgr %r7, %r3
 ;   lgfr %r3, %r2
 ;   iilf %r4, 2147483647
-;   xrk %r2, %r4, %r3
+;   xrk %r5, %r4, %r3
-;   lgr %r4, %r5
+;   lgr %r4, %r7
-;   nrk %r5, %r2, %r4
+;   nr %r5, %r4
 ;   cite %r5, -1
 ;   dsgfr %r2, %r4
 ;   lgr %r2, %r3
+;   lmg %r7, %r15, 56(%r15)
 ;   br %r14
 
 function %sdiv_i32_imm(i32) -> i32 {
@@ -1090,8 +1090,8 @@ block0(v0: i32):
 
 ; block0:
 ;   lgfr %r3, %r2
-;   lhi %r4, 2
+;   lhi %r2, 2
-;   dsgfr %r2, %r4
+;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -1102,14 +1102,14 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   lghr %r2, %r2
+;   lghr %r5, %r2
-;   lgr %r5, %r2
+;   lgr %r2, %r5
 ;   lhr %r4, %r3
-;   lhi %r2, 32767
+;   lhi %r5, 32767
-;   lgr %r3, %r5
+;   lgr %r3, %r2
-;   xrk %r5, %r2, %r3
+;   xr %r5, %r3
-;   nrk %r2, %r5, %r4
+;   nr %r5, %r4
-;   cite %r2, -1
+;   cite %r5, -1
 ;   dsgfr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
@@ -1123,8 +1123,8 @@ block0(v0: i16):
 
 ; block0:
 ;   lghr %r3, %r2
-;   lhi %r4, 2
+;   lhi %r2, 2
-;   dsgfr %r2, %r4
+;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -1135,14 +1135,14 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lgbr %r2, %r2
+;   lgbr %r5, %r2
-;   lgr %r5, %r2
+;   lgr %r2, %r5
 ;   lbr %r4, %r3
-;   lhi %r2, 127
+;   lhi %r5, 127
-;   lgr %r3, %r5
+;   lgr %r3, %r2
-;   xrk %r5, %r2, %r3
+;   xr %r5, %r3
-;   nrk %r2, %r5, %r4
+;   nr %r5, %r4
-;   cite %r2, -1
+;   cite %r5, -1
 ;   dsgfr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
@@ -1156,8 +1156,8 @@ block0(v0: i8):
 
 ; block0:
 ;   lgbr %r3, %r2
-;   lhi %r4, 2
+;   lhi %r2, 2
-;   dsgfr %r2, %r4
+;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -1168,10 +1168,10 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   lgr %r5, %r3
+;   lgr %r4, %r3
 ;   lgr %r3, %r2
 ;   lghi %r2, 0
-;   dlgr %r2, %r5
+;   dlgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -1197,10 +1197,10 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   lgr %r5, %r3
+;   lgr %r4, %r3
 ;   lgr %r3, %r2
 ;   lhi %r2, 0
-;   dlr %r2, %r5
+;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -1225,16 +1225,18 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
-;   lhi %r3, 0
+;   lhi %r5, 0
-;   lgr %r5, %r3
+;   lgr %r8, %r5
 ;   llhr %r3, %r2
-;   lgr %r2, %r4
+;   lgr %r5, %r4
-;   llhr %r4, %r2
+;   llhr %r5, %r5
-;   lgr %r2, %r5
+;   lgr %r2, %r8
-;   dlr %r2, %r4
+;   dlr %r2, %r5
 ;   lgr %r2, %r3
+;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
 
 function %udiv_i16_imm(i16) -> i16 {
@@ -1245,12 +1247,12 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lhi %r5, 0
+;   lhi %r4, 0
-;   lgr %r4, %r5
+;   lgr %r5, %r4
 ;   llhr %r3, %r2
-;   lhi %r5, 2
+;   lhi %r4, 2
-;   lgr %r2, %r4
+;   lgr %r2, %r5
-;   dlr %r2, %r5
+;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -1260,16 +1262,18 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
-;   lhi %r3, 0
+;   lhi %r5, 0
-;   lgr %r5, %r3
+;   lgr %r8, %r5
 ;   llcr %r3, %r2
-;   lgr %r2, %r4
+;   lgr %r5, %r4
-;   llcr %r4, %r2
+;   llcr %r5, %r5
-;   lgr %r2, %r5
+;   lgr %r2, %r8
-;   dlr %r2, %r4
+;   dlr %r2, %r5
 ;   lgr %r2, %r3
+;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
 
 function %udiv_i8_imm(i8) -> i8 {
@@ -1280,12 +1284,12 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lhi %r5, 0
+;   lhi %r4, 0
-;   lgr %r4, %r5
+;   lgr %r5, %r4
 ;   llcr %r3, %r2
-;   lhi %r5, 2
+;   lhi %r4, 2
-;   lgr %r2, %r4
+;   lgr %r2, %r5
-;   dlr %r2, %r5
+;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -1310,9 +1314,10 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   lgr %r4, %r3
+;   lgr %r5, %r3
 ;   lgfr %r3, %r2
-;   dsgfr %r2, %r4
+;   lgr %r2, %r5
+;   dsgfr %r2, %r2
 ;   br %r14
 
 function %srem_i16(i16, i16) -> i16 {
@@ -1348,10 +1353,10 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   lgr %r5, %r3
+;   lgr %r4, %r3
 ;   lgr %r3, %r2
 ;   lghi %r2, 0
-;   dlgr %r2, %r5
+;   dlgr %r2, %r4
 ;   br %r14
 
 function %urem_i32(i32, i32) -> i32 {
@@ -1361,10 +1366,10 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   lgr %r5, %r3
+;   lgr %r4, %r3
 ;   lgr %r3, %r2
 ;   lhi %r2, 0
-;   dlr %r2, %r5
+;   dlr %r2, %r4
 ;   br %r14
 
 function %urem_i16(i16, i16) -> i16 {
@@ -1373,15 +1378,17 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
-;   lhi %r3, 0
+;   lhi %r5, 0
-;   lgr %r5, %r3
+;   lgr %r8, %r5
 ;   llhr %r3, %r2
-;   lgr %r2, %r4
+;   lgr %r5, %r4
-;   llhr %r4, %r2
+;   llhr %r5, %r5
-;   lgr %r2, %r5
+;   lgr %r2, %r8
-;   dlr %r2, %r4
+;   dlr %r2, %r5
+;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
 
 function %urem_i8(i8, i8) -> i8 {
@@ -1390,14 +1397,16 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
-;   lhi %r3, 0
+;   lhi %r5, 0
-;   lgr %r5, %r3
+;   lgr %r8, %r5
 ;   llcr %r3, %r2
-;   lgr %r2, %r4
+;   lgr %r5, %r4
-;   llcr %r4, %r2
+;   llcr %r5, %r5
-;   lgr %r2, %r5
+;   lgr %r2, %r8
-;   dlr %r2, %r4
+;   dlr %r2, %r5
+;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif

@@ -37,20 +37,17 @@ block0(v0: i64, v1: i16, v2: i16, v3: i64):
   return v4
 }
 
-;   stmg %r9, %r15, 72(%r15)
+;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   lgr %r9, %r4
+;   sllk %r11, %r5, 3
-;   sllk %r4, %r5, 3
+;   nill %r5, 65532
-;   lgr %r2, %r5
+;   lrvr %r2, %r3
-;   nill %r2, 65532
+;   lrvr %r3, %r4
-;   lrvr %r5, %r3
+;   l %r0, 0(%r5)
-;   lgr %r3, %r9
+;   0: rll %r1, %r0, 16(%r11) ; rxsbg %r1, %r2, 176, 64, 48 ; jglh 1f ; risbgn %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r11) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   lrvr %r3, %r3
+;   rll %r5, %r0, 0(%r11)
-;   l %r0, 0(%r2)
+;   lrvr %r2, %r5
-;   0: rll %r1, %r0, 16(%r4) ; rxsbg %r1, %r5, 176, 64, 48 ; jglh 1f ; risbgn %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r2) ; jglh 0b ; 1:
+;   lmg %r11, %r15, 88(%r15)
-;   rll %r2, %r0, 0(%r4)
-;   lrvr %r2, %r2
-;   lmg %r9, %r15, 72(%r15)
 ;   br %r14
 
 function %atomic_cas_i8(i64, i8, i8, i64) -> i8 {
@@ -59,16 +56,15 @@ block0(v0: i64, v1: i8, v2: i8, v3: i64):
   return v4
 }
 
-;   stmg %r11, %r15, 88(%r15)
+;   stmg %r10, %r15, 80(%r15)
 ; block0:
-;   lgr %r11, %r4
+;   lgr %r10, %r3
-;   sllk %r4, %r5, 3
+;   sllk %r3, %r5, 3
-;   lgr %r2, %r5
+;   nill %r5, 65532
-;   nill %r2, 65532
+;   lcr %r2, %r3
-;   lcr %r5, %r4
+;   l %r0, 0(%r5)
-;   l %r0, 0(%r2)
+;   0: rll %r1, %r0, 0(%r3) ; rxsbg %r1, %r10, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r3, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r11, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r2) ; jglh 0b ; 1:
+;   rll %r2, %r0, 8(%r3)
-;   rll %r2, %r0, 8(%r4)
+;   lmg %r10, %r15, 80(%r15)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/atomic_cas.clif

@@ -31,17 +31,13 @@ block0(v0: i64, v1: i16, v2: i16, v3: i64):
   return v4
 }
 
-;   stmg %r6, %r15, 48(%r15)
 ; block0:
-;   lgr %r6, %r4
+;   lgr %r2, %r3
-;   sllk %r4, %r5, 3
+;   sllk %r3, %r5, 3
-;   lgr %r2, %r5
+;   nill %r5, 65532
-;   nill %r2, 65532
+;   l %r0, 0(%r5)
-;   l %r0, 0(%r2)
+;   0: rll %r1, %r0, 0(%r3) ; rxsbg %r1, %r2, 160, 48, 16 ; jglh 1f ; risbgn %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   lgr %r5, %r6
+;   rll %r2, %r0, 16(%r3)
-;   0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r3, 160, 48, 16 ; jglh 1f ; risbgn %r1, %r5, 32, 48, 16 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r2) ; jglh 0b ; 1:
-;   rll %r2, %r0, 16(%r4)
-;   lmg %r6, %r15, 48(%r15)
 ;   br %r14
 
 function %atomic_cas_i8(i64, i8, i8, i64) -> i8 {
@@ -50,16 +46,15 @@ block0(v0: i64, v1: i8, v2: i8, v3: i64):
   return v4
 }
 
-;   stmg %r11, %r15, 88(%r15)
+;   stmg %r10, %r15, 80(%r15)
 ; block0:
-;   lgr %r11, %r4
+;   lgr %r10, %r3
-;   sllk %r4, %r5, 3
+;   sllk %r3, %r5, 3
-;   lgr %r2, %r5
+;   nill %r5, 65532
-;   nill %r2, 65532
+;   lcr %r2, %r3
-;   lcr %r5, %r4
+;   l %r0, 0(%r5)
-;   l %r0, 0(%r2)
+;   0: rll %r1, %r0, 0(%r3) ; rxsbg %r1, %r10, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r3, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r11, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r2) ; jglh 0b ; 1:
+;   rll %r2, %r0, 8(%r3)
-;   rll %r2, %r0, 8(%r4)
+;   lmg %r10, %r15, 80(%r15)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif

@@ -46,16 +46,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 {
@@ -65,9 +63,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lrvgr %r4, %r4
+;   lrvgr %r2, %r4
 ;   lg %r0, 0(%r3)
-;   0: nngrk %r1, %r0, %r4 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
+;   0: nngrk %r1, %r0, %r2 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
 
@@ -78,9 +76,9 @@ block0(v0: i64, v1: i64, v2: i32):
 }
 
 ; block0:
-;   lrvr %r4, %r4
+;   lrvr %r2, %r4
 ;   l %r0, 0(%r3)
-;   0: nnrk %r1, %r0, %r4 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
+;   0: nnrk %r1, %r0, %r2 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
 
@@ -91,14 +89,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   lrvr %r4, %r4
+;   lrvr %r3, %r5
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r4, 48, 64, 48 ; xilf %r1, 65535 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r3, 48, 64, 48 ; xilf %r1, 65535 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 {
@@ -107,15 +106,13 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif

@@ -12,9 +12,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lrvgr %r4, %r4
+;   lrvgr %r2, %r4
 ;   lg %r0, 0(%r3)
-;   0: csg %r0, %r4, 0(%r3) ; jglh 0b ; 1:
+;   0: csg %r0, %r2, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
 
@@ -25,9 +25,9 @@ block0(v0: i64, v1: i64, v2: i32):
 }
 
 ; block0:
-;   lrvr %r4, %r4
+;   lrvr %r2, %r4
 ;   l %r0, 0(%r3)
-;   0: cs %r0, %r4, 0(%r3) ; jglh 0b ; 1:
+;   0: cs %r0, %r2, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
 
@@ -38,14 +38,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   lrvr %r4, %r4
+;   lrvr %r3, %r5
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; risbgn %r1, %r4, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; risbgn %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_xchg_i8(i64, i64, i8) -> i8 {
@@ -54,16 +55,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_add_i64(i64, i64, i64) -> i64 {
@@ -97,14 +96,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; ar %r1, %r4 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; ar %r1, %r3 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_add_i8(i64, i64, i8) -> i8 {
@@ -113,17 +113,15 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; ar %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; ar %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_sub_i64(i64, i64, i64) -> i64 {
@@ -157,14 +155,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; sr %r1, %r4 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; sr %r1, %r3 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_sub_i8(i64, i64, i8) -> i8 {
@@ -173,17 +172,15 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; sr %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; sr %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_and_i64(i64, i64, i64) -> i64 {
@@ -193,9 +190,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lrvgr %r4, %r4
+;   lrvgr %r2, %r4
-;   lang %r5, %r4, 0(%r3)
+;   lang %r4, %r2, 0(%r3)
-;   lrvgr %r2, %r5
+;   lrvgr %r2, %r4
 ;   br %r14
 
 function %atomic_rmw_and_i32(i64, i64, i32) -> i32 {
@@ -205,9 +202,9 @@ block0(v0: i64, v1: i64, v2: i32):
 }
 
 ; block0:
-;   lrvr %r4, %r4
+;   lrvr %r2, %r4
-;   lan %r5, %r4, 0(%r3)
+;   lan %r4, %r2, 0(%r3)
-;   lrvr %r2, %r5
+;   lrvr %r2, %r4
 ;   br %r14
 
 function %atomic_rmw_and_i16(i64, i64, i16) -> i16 {
@@ -217,14 +214,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   lrvr %r4, %r4
+;   lrvr %r3, %r5
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r4, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_and_i8(i64, i64, i8) -> i8 {
@@ -233,16 +231,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_or_i64(i64, i64, i64) -> i64 {
@@ -252,9 +248,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lrvgr %r4, %r4
+;   lrvgr %r2, %r4
-;   laog %r5, %r4, 0(%r3)
+;   laog %r4, %r2, 0(%r3)
-;   lrvgr %r2, %r5
+;   lrvgr %r2, %r4
 ;   br %r14
 
 function %atomic_rmw_or_i32(i64, i64, i32) -> i32 {
@@ -264,9 +260,9 @@ block0(v0: i64, v1: i64, v2: i32):
 }
 
 ; block0:
-;   lrvr %r4, %r4
+;   lrvr %r2, %r4
-;   lao %r5, %r4, 0(%r3)
+;   lao %r4, %r2, 0(%r3)
-;   lrvr %r2, %r5
+;   lrvr %r2, %r4
 ;   br %r14
 
 function %atomic_rmw_or_i16(i64, i64, i16) -> i16 {
@@ -276,14 +272,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   lrvr %r4, %r4
+;   lrvr %r3, %r5
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; rosbg %r1, %r4, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; rosbg %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_or_i8(i64, i64, i8) -> i8 {
@@ -292,16 +289,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_xor_i64(i64, i64, i64) -> i64 {
@@ -311,9 +306,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lrvgr %r4, %r4
+;   lrvgr %r2, %r4
-;   laxg %r5, %r4, 0(%r3)
+;   laxg %r4, %r2, 0(%r3)
-;   lrvgr %r2, %r5
+;   lrvgr %r2, %r4
 ;   br %r14
 
 function %atomic_rmw_xor_i32(i64, i64, i32) -> i32 {
@@ -323,9 +318,9 @@ block0(v0: i64, v1: i64, v2: i32):
 }
 
 ; block0:
-;   lrvr %r4, %r4
+;   lrvr %r2, %r4
-;   lax %r5, %r4, 0(%r3)
+;   lax %r4, %r2, 0(%r3)
-;   lrvr %r2, %r5
+;   lrvr %r2, %r4
 ;   br %r14
 
 function %atomic_rmw_xor_i16(i64, i64, i16) -> i16 {
@@ -335,14 +330,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   lrvr %r4, %r4
+;   lrvr %r3, %r5
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; rxsbg %r1, %r4, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; rxsbg %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_xor_i8(i64, i64, i8) -> i8 {
@@ -351,16 +347,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 {
@@ -370,9 +364,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lrvgr %r4, %r4
+;   lrvgr %r2, %r4
 ;   lg %r0, 0(%r3)
-;   0: ngrk %r1, %r0, %r4 ; xilf %r1, 4294967295 ; xihf %r1, 4294967295 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
+;   0: ngrk %r1, %r0, %r2 ; xilf %r1, 4294967295 ; xihf %r1, 4294967295 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvgr %r2, %r0
 ;   br %r14
 
@@ -383,9 +377,9 @@ block0(v0: i64, v1: i64, v2: i32):
 }
 
 ; block0:
-;   lrvr %r4, %r4
+;   lrvr %r2, %r4
 ;   l %r0, 0(%r3)
-;   0: nrk %r1, %r0, %r4 ; xilf %r1, 4294967295 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
+;   0: nrk %r1, %r0, %r2 ; xilf %r1, 4294967295 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1:
 ;   lrvr %r2, %r0
 ;   br %r14
 
@@ -396,14 +390,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   lrvr %r4, %r4
+;   lrvr %r3, %r5
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r4, 48, 64, 48 ; xilf %r1, 65535 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r3, 48, 64, 48 ; xilf %r1, 65535 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 {
@@ -412,16 +407,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_smin_i64(i64, i64, i64) -> i64 {
@@ -455,14 +448,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; cr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_smin_i8(i64, i64, i8) -> i8 {
@@ -471,17 +465,15 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; cr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_smax_i64(i64, i64, i64) -> i64 {
@@ -515,14 +507,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; cr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_smax_i8(i64, i64, i8) -> i8 {
@@ -531,17 +524,15 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; cr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_umin_i64(i64, i64, i64) -> i64 {
@@ -575,14 +566,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; clr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_umin_i8(i64, i64, i8) -> i8 {
@@ -591,17 +583,15 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; clr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_umax_i64(i64, i64, i64) -> i64 {
@@ -635,14 +625,15 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; clr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
-;   rll %r3, %r0, 0(%r2)
+;   rll %r2, %r0, 0(%r2)
-;   lrvr %r2, %r3
+;   lrvr %r2, %r2
 ;   br %r14
 
 function %atomic_rmw_umax_i8(i64, i64, i8) -> i8 {
@@ -651,16 +642,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; clr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif

@@ -50,16 +50,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_add_i64(i64, i64) -> i64 {
@@ -89,12 +87,13 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 0(%r2) ; ar %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; ar %r1, %r3 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
 
@@ -104,17 +103,15 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; ar %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; ar %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_sub_i64(i64, i64) -> i64 {
@@ -124,8 +121,8 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   lcgr %r3, %r3
+;   lcgr %r5, %r3
-;   laag %r2, %r3, 0(%r2)
+;   laag %r2, %r5, 0(%r2)
 ;   br %r14
 
 function %atomic_rmw_sub_i32(i64, i32) -> i32 {
@@ -135,8 +132,8 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   lcr %r3, %r3
+;   lcr %r5, %r3
-;   laa %r2, %r3, 0(%r2)
+;   laa %r2, %r5, 0(%r2)
 ;   br %r14
 
 function %atomic_rmw_sub_i16(i64, i64, i16) -> i16 {
@@ -146,12 +143,13 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 0(%r2) ; sr %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; sr %r1, %r3 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
 
@@ -161,17 +159,15 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; sr %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; sr %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_and_i64(i64, i64) -> i64 {
@@ -215,16 +211,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_or_i64(i64, i64) -> i64 {
@@ -268,16 +262,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_xor_i64(i64, i64) -> i64 {
@@ -321,16 +313,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 {
@@ -378,16 +368,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   lcr %r2, %r11
+;   lcr %r3, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_smin_i64(i64, i64, i64) -> i64 {
@@ -421,12 +409,13 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 0(%r2) ; cr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
 
@@ -436,17 +425,15 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; cr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_smax_i64(i64, i64, i64) -> i64 {
@@ -480,12 +467,13 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 0(%r2) ; cr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
 
@@ -495,17 +483,15 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; cr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_umin_i64(i64, i64, i64) -> i64 {
@@ -539,12 +525,13 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 0(%r2) ; clr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
 
@@ -554,17 +541,15 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; clr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 
 function %atomic_rmw_umax_i64(i64, i64, i64) -> i64 {
@@ -598,12 +583,13 @@ block0(v0: i64, v1: i64, v2: i16):
 }
 
 ; block0:
+;   lgr %r5, %r4
 ;   sllk %r2, %r3, 3
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   nill %r5, 65532
+;   nill %r4, 65532
-;   sllk %r4, %r4, 16
+;   sllk %r3, %r5, 16
-;   l %r0, 0(%r5)
+;   l %r0, 0(%r4)
-;   0: rll %r1, %r0, 0(%r2) ; clr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1:
 ;   rll %r2, %r0, 16(%r2)
 ;   br %r14
 
@@ -613,16 +599,14 @@ block0(v0: i64, v1: i64, v2: i8):
   return v3
 }
 
-;   stmg %r11, %r15, 88(%r15)
 ; block0:
-;   sllk %r11, %r3, 3
+;   sllk %r2, %r3, 3
 ;   lgr %r5, %r3
 ;   nill %r5, 65532
-;   sllk %r4, %r4, 24
+;   sllk %r3, %r4, 24
-;   lcr %r2, %r11
+;   lcr %r4, %r2
 ;   l %r0, 0(%r5)
-;   0: rll %r1, %r0, 0(%r11) ; clr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
+;   0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1:
-;   rll %r2, %r0, 8(%r11)
+;   rll %r2, %r0, 8(%r2)
-;   lmg %r11, %r15, 88(%r15)
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/bitops-arch13.clif

@@ -22,8 +22,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   llgfr %r5, %r2
+;   llgfr %r4, %r2
-;   popcnt %r2, %r5, 8
+;   popcnt %r2, %r4, 8
 ;   br %r14
 
 function %popcnt_i16(i16) -> i16 {
@@ -33,8 +33,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   llghr %r5, %r2
+;   llghr %r4, %r2
-;   popcnt %r2, %r5, 8
+;   popcnt %r2, %r4, 8
 ;   br %r14
 
 function %popcnt_i8(i8) -> i8 {

cranelift/filetests/filetests/isa/s390x/bitops.clif

@@ -9,24 +9,24 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r3)
-;   vrepib %v5, 170
+;   vrepib %v4, 170
-;   vrepib %v7, 1
+;   vrepib %v6, 1
-;   vsl %v17, %v0, %v7
+;   vsl %v16, %v0, %v6
-;   vsrl %v19, %v0, %v7
+;   vsrl %v18, %v0, %v6
-;   vsel %v21, %v17, %v19, %v5
+;   vsel %v20, %v16, %v18, %v4
-;   vrepib %v23, 204
+;   vrepib %v22, 204
-;   vrepib %v25, 2
+;   vrepib %v24, 2
-;   vsl %v27, %v21, %v25
+;   vsl %v26, %v20, %v24
-;   vsrl %v29, %v21, %v25
+;   vsrl %v28, %v20, %v24
-;   vsel %v31, %v27, %v29, %v23
+;   vsel %v30, %v26, %v28, %v22
-;   vrepib %v1, 240
+;   vrepib %v0, 240
-;   vrepib %v3, 4
+;   vrepib %v2, 4
-;   vsl %v5, %v31, %v3
+;   vsl %v4, %v30, %v2
-;   vsrl %v7, %v31, %v3
+;   vsrl %v6, %v30, %v2
-;   vsel %v17, %v5, %v7, %v1
+;   vsel %v16, %v4, %v6, %v0
-;   bras %r1, 20 ; data.u128 0x0f0e0d0c0b0a09080706050403020100 ; vl %v19, 0(%r1)
+;   bras %r1, 20 ; data.u128 0x0f0e0d0c0b0a09080706050403020100 ; vl %v18, 0(%r1)
-;   vperm %v21, %v17, %v17, %v19
+;   vperm %v20, %v16, %v16, %v18
-;   vst %v21, 0(%r2)
+;   vst %v20, 0(%r2)
 ;   br %r14
 
 function %bitrev_i64(i64) -> i64 {
@@ -36,34 +36,36 @@ block0(v0: i64):
 }
 
 ; block0:
-;   llihf %r3, 2863311530
+;   lgr %r4, %r2
-;   iilf %r3, 2863311530
+;   llihf %r2, 2863311530
-;   sllg %r5, %r2, 1
+;   iilf %r2, 2863311530
-;   srlg %r4, %r2, 1
+;   lgr %r3, %r4
-;   ngr %r5, %r3
+;   sllg %r4, %r3, 1
-;   xilf %r3, 4294967295
+;   srlg %r3, %r3, 1
-;   xihf %r3, 4294967295
+;   ngr %r4, %r2
-;   ngrk %r3, %r4, %r3
+;   xilf %r2, 4294967295
-;   ogrk %r2, %r5, %r3
+;   xihf %r2, 4294967295
-;   llihf %r5, 3435973836
+;   ngrk %r2, %r3, %r2
-;   iilf %r5, 3435973836
+;   ogrk %r5, %r4, %r2
-;   sllg %r3, %r2, 2
+;   llihf %r4, 3435973836
-;   srlg %r2, %r2, 2
+;   iilf %r4, 3435973836
-;   ngr %r3, %r5
+;   sllg %r2, %r5, 2
-;   xilf %r5, 4294967295
+;   srlg %r5, %r5, 2
-;   xihf %r5, 4294967295
+;   ngr %r2, %r4
-;   ngrk %r5, %r2, %r5
+;   xilf %r4, 4294967295
-;   ogrk %r4, %r3, %r5
+;   xihf %r4, 4294967295
-;   llihf %r3, 4042322160
+;   ngrk %r4, %r5, %r4
-;   iilf %r3, 4042322160
+;   ogrk %r3, %r2, %r4
-;   sllg %r5, %r4, 4
+;   llihf %r2, 4042322160
-;   srlg %r4, %r4, 4
+;   iilf %r2, 4042322160
-;   ngr %r5, %r3
+;   sllg %r4, %r3, 4
-;   xilf %r3, 4294967295
+;   srlg %r3, %r3, 4
-;   xihf %r3, 4294967295
+;   ngr %r4, %r2
-;   ngrk %r3, %r4, %r3
+;   xilf %r2, 4294967295
-;   ogr %r5, %r3
+;   xihf %r2, 4294967295
-;   lrvgr %r2, %r5
+;   ngrk %r2, %r3, %r2
+;   ogr %r4, %r2
+;   lrvgr %r2, %r4
 ;   br %r14
 
 function %bitrev_i32(i32) -> i32 {
@@ -73,28 +75,28 @@ block0(v0: i32):
 }
 
 ; block0:
-;   iilf %r5, 2863311530
+;   iilf %r4, 2863311530
 ;   sllk %r3, %r2, 1
-;   srlk %r2, %r2, 1
+;   srlk %r5, %r2, 1
-;   nr %r3, %r5
+;   nrk %r2, %r3, %r4
-;   xilf %r5, 4294967295
+;   xilf %r4, 4294967295
-;   nrk %r4, %r2, %r5
+;   nrk %r3, %r5, %r4
-;   ork %r5, %r3, %r4
+;   ork %r4, %r2, %r3
-;   iilf %r3, 3435973836
+;   iilf %r2, 3435973836
-;   sllk %r2, %r5, 2
+;   sllk %r5, %r4, 2
-;   srlk %r4, %r5, 2
+;   srlk %r3, %r4, 2
-;   nrk %r5, %r2, %r3
+;   nrk %r4, %r5, %r2
-;   xilf %r3, 4294967295
+;   xilf %r2, 4294967295
-;   nrk %r2, %r4, %r3
+;   nrk %r5, %r3, %r2
-;   ork %r3, %r5, %r2
+;   ork %r2, %r4, %r5
-;   iilf %r5, 4042322160
+;   iilf %r4, 4042322160
-;   sllk %r4, %r3, 4
+;   sllk %r3, %r2, 4
-;   srlk %r2, %r3, 4
+;   srlk %r5, %r2, 4
-;   nrk %r3, %r4, %r5
+;   nrk %r2, %r3, %r4
-;   xilf %r5, 4294967295
+;   xilf %r4, 4294967295
-;   nrk %r4, %r2, %r5
+;   nrk %r3, %r5, %r4
-;   ork %r5, %r3, %r4
+;   ork %r4, %r2, %r3
-;   lrvr %r2, %r5
+;   lrvr %r2, %r4
 ;   br %r14
 
 function %bitrev_i16(i16) -> i16 {
@@ -104,29 +106,29 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lhi %r5, -21846
+;   lhi %r4, -21846
 ;   sllk %r3, %r2, 1
-;   srlk %r2, %r2, 1
+;   srlk %r5, %r2, 1
-;   nr %r3, %r5
+;   nrk %r2, %r3, %r4
-;   xilf %r5, 4294967295
+;   xilf %r4, 4294967295
-;   nrk %r4, %r2, %r5
+;   nrk %r3, %r5, %r4
-;   ork %r5, %r3, %r4
+;   ork %r4, %r2, %r3
-;   lhi %r3, -13108
+;   lhi %r2, -13108
-;   sllk %r2, %r5, 2
+;   sllk %r5, %r4, 2
-;   srlk %r4, %r5, 2
+;   srlk %r3, %r4, 2
-;   nrk %r5, %r2, %r3
+;   nrk %r4, %r5, %r2
-;   xilf %r3, 4294967295
+;   xilf %r2, 4294967295
-;   nrk %r2, %r4, %r3
+;   nrk %r5, %r3, %r2
-;   ork %r3, %r5, %r2
+;   ork %r2, %r4, %r5
-;   lhi %r5, -3856
+;   lhi %r4, -3856
-;   sllk %r4, %r3, 4
+;   sllk %r3, %r2, 4
-;   srlk %r2, %r3, 4
+;   srlk %r5, %r2, 4
-;   nrk %r3, %r4, %r5
+;   nrk %r2, %r3, %r4
-;   xilf %r5, 4294967295
+;   xilf %r4, 4294967295
-;   nrk %r4, %r2, %r5
+;   nrk %r3, %r5, %r4
-;   ork %r5, %r3, %r4
+;   ork %r4, %r2, %r3
-;   lrvr %r3, %r5
+;   lrvr %r2, %r4
-;   srlk %r2, %r3, 16
+;   srlk %r2, %r2, 16
 ;   br %r14
 
 function %bitrev_i8(i8) -> i8 {
@@ -136,27 +138,27 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lhi %r5, -21846
+;   lhi %r4, -21846
 ;   sllk %r3, %r2, 1
-;   srlk %r2, %r2, 1
+;   srlk %r5, %r2, 1
-;   nr %r3, %r5
+;   nrk %r2, %r3, %r4
-;   xilf %r5, 4294967295
+;   xilf %r4, 4294967295
-;   nrk %r4, %r2, %r5
+;   nrk %r3, %r5, %r4
-;   ork %r5, %r3, %r4
+;   ork %r4, %r2, %r3
-;   lhi %r3, -13108
+;   lhi %r2, -13108
-;   sllk %r2, %r5, 2
+;   sllk %r5, %r4, 2
-;   srlk %r4, %r5, 2
+;   srlk %r3, %r4, 2
-;   nrk %r5, %r2, %r3
+;   nrk %r4, %r5, %r2
-;   xilf %r3, 4294967295
+;   xilf %r2, 4294967295
-;   nrk %r2, %r4, %r3
+;   nrk %r5, %r3, %r2
-;   ork %r3, %r5, %r2
+;   ork %r2, %r4, %r5
-;   lhi %r5, -3856
+;   lhi %r4, -3856
-;   sllk %r4, %r3, 4
+;   sllk %r3, %r2, 4
-;   srlk %r2, %r3, 4
+;   srlk %r5, %r2, 4
-;   nrk %r3, %r4, %r5
+;   nrk %r2, %r3, %r4
-;   xilf %r5, 4294967295
+;   xilf %r4, 4294967295
-;   nrk %r4, %r2, %r5
+;   nrk %r3, %r5, %r4
-;   ork %r2, %r3, %r4
+;   or %r2, %r3
 ;   br %r14
 
 function %clz_i128(i128) -> i128 {
@@ -167,15 +169,15 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r3)
-;   vclzg %v5, %v0
+;   vclzg %v4, %v0
-;   vgbm %v7, 0
+;   vgbm %v6, 0
-;   vpdi %v17, %v7, %v5, 0
+;   vpdi %v16, %v6, %v4, 0
-;   vpdi %v19, %v7, %v5, 1
+;   vpdi %v18, %v6, %v4, 1
-;   vag %v21, %v17, %v19
+;   vag %v20, %v16, %v18
-;   vrepig %v23, 64
+;   vrepig %v22, 64
-;   vceqg %v25, %v17, %v23
+;   vceqg %v24, %v16, %v22
-;   vsel %v27, %v21, %v17, %v25
+;   vsel %v26, %v20, %v16, %v24
-;   vst %v27, 0(%r2)
+;   vst %v26, 0(%r2)
 ;   br %r14
 
 function %clz_i64(i64) -> i64 {
@@ -195,8 +197,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   llgfr %r5, %r2
+;   llgfr %r4, %r2
-;   flogr %r2, %r5
+;   flogr %r2, %r4
 ;   ahi %r2, -32
 ;   br %r14
 
@@ -207,8 +209,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   llghr %r5, %r2
+;   llghr %r4, %r2
-;   flogr %r2, %r5
+;   flogr %r2, %r4
 ;   ahi %r2, -48
 ;   br %r14
 
@@ -219,8 +221,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   llgcr %r5, %r2
+;   llgcr %r4, %r2
-;   flogr %r2, %r5
+;   flogr %r2, %r4
 ;   ahi %r2, -56
 ;   br %r14
 
@@ -232,20 +234,20 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r3)
-;   vrepib %v5, 255
+;   vrepib %v4, 255
-;   vsrab %v7, %v0, %v5
+;   vsrab %v6, %v0, %v4
-;   vsra %v17, %v7, %v5
+;   vsra %v16, %v6, %v4
-;   vx %v19, %v0, %v17
+;   vx %v18, %v0, %v16
-;   vclzg %v21, %v19
+;   vclzg %v20, %v18
-;   vgbm %v23, 0
+;   vgbm %v22, 0
-;   vpdi %v25, %v23, %v21, 0
+;   vpdi %v24, %v22, %v20, 0
-;   vpdi %v27, %v23, %v21, 1
+;   vpdi %v26, %v22, %v20, 1
-;   vag %v29, %v25, %v27
+;   vag %v28, %v24, %v26
-;   vrepig %v31, 64
+;   vrepig %v30, 64
-;   vceqg %v1, %v25, %v31
+;   vceqg %v0, %v24, %v30
-;   vsel %v3, %v29, %v25, %v1
+;   vsel %v2, %v28, %v24, %v0
-;   vaq %v5, %v3, %v5
+;   vaq %v4, %v2, %v4
-;   vst %v5, 0(%r2)
+;   vst %v4, 0(%r2)
 ;   br %r14
 
 function %cls_i64(i64) -> i64 {
@@ -255,9 +257,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   srag %r5, %r2, 63
+;   srag %r4, %r2, 63
-;   xgrk %r3, %r2, %r5
+;   xgr %r2, %r4
-;   flogr %r2, %r3
+;   flogr %r2, %r2
 ;   aghi %r2, -1
 ;   br %r14
 
@@ -268,10 +270,10 @@ block0(v0: i32):
 }
 
 ; block0:
-;   lgfr %r5, %r2
+;   lgfr %r4, %r2
-;   srag %r3, %r5, 63
+;   srag %r2, %r4, 63
-;   xgr %r5, %r3
+;   xgr %r4, %r2
-;   flogr %r2, %r5
+;   flogr %r2, %r4
 ;   ahi %r2, -33
 ;   br %r14
 
@@ -282,10 +284,10 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lghr %r5, %r2
+;   lghr %r4, %r2
-;   srag %r3, %r5, 63
+;   srag %r2, %r4, 63
-;   xgr %r5, %r3
+;   xgr %r4, %r2
-;   flogr %r2, %r5
+;   flogr %r2, %r4
 ;   ahi %r2, -49
 ;   br %r14
 
@@ -296,10 +298,10 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lgbr %r5, %r2
+;   lgbr %r4, %r2
-;   srag %r3, %r5, 63
+;   srag %r2, %r4, 63
-;   xgr %r5, %r3
+;   xgr %r4, %r2
-;   flogr %r2, %r5
+;   flogr %r2, %r4
 ;   ahi %r2, -57
 ;   br %r14
 
@@ -311,15 +313,15 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r3)
-;   vctzg %v5, %v0
+;   vctzg %v4, %v0
-;   vgbm %v7, 0
+;   vgbm %v6, 0
-;   vpdi %v17, %v7, %v5, 0
+;   vpdi %v16, %v6, %v4, 0
-;   vpdi %v19, %v7, %v5, 1
+;   vpdi %v18, %v6, %v4, 1
-;   vag %v21, %v17, %v19
+;   vag %v20, %v16, %v18
-;   vrepig %v23, 64
+;   vrepig %v22, 64
-;   vceqg %v25, %v19, %v23
+;   vceqg %v24, %v18, %v22
-;   vsel %v27, %v21, %v19, %v25
+;   vsel %v26, %v20, %v18, %v24
-;   vst %v27, 0(%r2)
+;   vst %v26, 0(%r2)
 ;   br %r14
 
 function %ctz_i64(i64) -> i64 {
@@ -329,13 +331,13 @@ block0(v0: i64):
 }
 
 ; block0:
-;   lcgr %r5, %r2
+;   lcgr %r4, %r2
-;   ngrk %r3, %r2, %r5
+;   ngr %r2, %r4
-;   flogr %r2, %r3
+;   flogr %r2, %r2
-;   lgr %r4, %r2
+;   lgr %r3, %r2
-;   locghie %r4, -1
+;   locghie %r3, -1
-;   lghi %r2, 63
+;   lghi %r5, 63
-;   sgr %r2, %r4
+;   sgrk %r2, %r5, %r3
 ;   br %r14
 
 function %ctz_i32(i32) -> i32 {
@@ -345,13 +347,13 @@ block0(v0: i32):
 }
 
 ; block0:
-;   lgr %r5, %r2
+;   lgr %r4, %r2
-;   oihl %r5, 1
+;   oihl %r4, 1
-;   lcgr %r3, %r5
+;   lcgr %r2, %r4
-;   ngr %r5, %r3
+;   ngr %r4, %r2
-;   flogr %r2, %r5
+;   flogr %r2, %r4
-;   lhi %r3, 63
+;   lhi %r5, 63
-;   srk %r2, %r3, %r2
+;   srk %r2, %r5, %r2
 ;   br %r14
 
 function %ctz_i16(i16) -> i16 {
@@ -361,13 +363,13 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lgr %r5, %r2
+;   lgr %r4, %r2
-;   oilh %r5, 1
+;   oilh %r4, 1
-;   lcgr %r3, %r5
+;   lcgr %r2, %r4
-;   ngr %r5, %r3
+;   ngr %r4, %r2
-;   flogr %r2, %r5
+;   flogr %r2, %r4
-;   lhi %r3, 63
+;   lhi %r5, 63
-;   srk %r2, %r3, %r2
+;   srk %r2, %r5, %r2
 ;   br %r14
 
 function %ctz_i8(i8) -> i8 {
@@ -377,13 +379,13 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lgr %r5, %r2
+;   lgr %r4, %r2
-;   oill %r5, 256
+;   oill %r4, 256
-;   lcgr %r3, %r5
+;   lcgr %r2, %r4
-;   ngr %r5, %r3
+;   ngr %r4, %r2
-;   flogr %r2, %r5
+;   flogr %r2, %r4
-;   lhi %r3, 63
+;   lhi %r5, 63
-;   srk %r2, %r3, %r2
+;   srk %r2, %r5, %r2
 ;   br %r14
 
 function %popcnt_i128(i128) -> i128 {
@@ -394,12 +396,12 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r3)
-;   vpopctg %v5, %v0
+;   vpopctg %v4, %v0
-;   vgbm %v7, 0
+;   vgbm %v6, 0
-;   vpdi %v17, %v7, %v5, 0
+;   vpdi %v16, %v6, %v4, 0
-;   vpdi %v19, %v7, %v5, 1
+;   vpdi %v18, %v6, %v4, 1
-;   vag %v21, %v17, %v19
+;   vag %v20, %v16, %v18
-;   vst %v21, 0(%r2)
+;   vst %v20, 0(%r2)
 ;   br %r14
 
 function %popcnt_i64(i64) -> i64 {
@@ -409,14 +411,14 @@ block0(v0: i64):
 }
 
 ; block0:
-;   popcnt %r5, %r2
+;   popcnt %r4, %r2
-;   sllg %r3, %r5, 32
+;   sllg %r2, %r4, 32
-;   agr %r5, %r3
+;   agr %r4, %r2
-;   sllg %r3, %r5, 16
+;   sllg %r2, %r4, 16
-;   agr %r5, %r3
+;   agr %r4, %r2
-;   sllg %r3, %r5, 8
+;   sllg %r2, %r4, 8
-;   agr %r5, %r3
+;   agr %r4, %r2
-;   srlg %r2, %r5, 56
+;   srlg %r2, %r4, 56
 ;   br %r14
 
 function %popcnt_i32(i32) -> i32 {
@@ -426,12 +428,12 @@ block0(v0: i32):
 }
 
 ; block0:
-;   popcnt %r5, %r2
+;   popcnt %r4, %r2
-;   sllk %r3, %r5, 16
+;   sllk %r2, %r4, 16
-;   ar %r5, %r3
+;   ar %r4, %r2
-;   sllk %r3, %r5, 8
+;   sllk %r2, %r4, 8
-;   ar %r5, %r3
+;   ar %r4, %r2
-;   srlk %r2, %r5, 24
+;   srlk %r2, %r4, 24
 ;   br %r14
 
 function %popcnt_i16(i16) -> i16 {
@@ -441,9 +443,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   popcnt %r5, %r2
+;   popcnt %r4, %r2
-;   srlk %r3, %r5, 8
+;   srlk %r2, %r4, 8
-;   ark %r2, %r5, %r3
+;   ark %r2, %r4, %r2
 ;   nill %r2, 255
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/bitwise-arch13.clif

@@ -174,8 +174,8 @@ block0(v0: i64, v1: i64, v2: i64):
 
 ; block0:
 ;   ngr %r3, %r2
-;   ncgrk %r5, %r4, %r2
+;   ncgrk %r4, %r4, %r2
-;   ogrk %r2, %r5, %r3
+;   ogrk %r2, %r4, %r3
 ;   br %r14
 
 function %bitselect_i32(i32, i32, i32) -> i32 {
@@ -186,8 +186,8 @@ block0(v0: i32, v1: i32, v2: i32):
 
 ; block0:
 ;   nr %r3, %r2
-;   ncrk %r5, %r4, %r2
+;   ncrk %r4, %r4, %r2
-;   ork %r2, %r5, %r3
+;   ork %r2, %r4, %r3
 ;   br %r14
 
 function %bitselect_i16(i16, i16, i16) -> i16 {
@@ -198,8 +198,8 @@ block0(v0: i16, v1: i16, v2: i16):
 
 ; block0:
 ;   nr %r3, %r2
-;   ncrk %r5, %r4, %r2
+;   ncrk %r4, %r4, %r2
-;   ork %r2, %r5, %r3
+;   ork %r2, %r4, %r3
 ;   br %r14
 
 function %bitselect_i8(i8, i8, i8) -> i8 {
@@ -210,7 +210,7 @@ block0(v0: i8, v1: i8, v2: i8):
 
 ; block0:
 ;   nr %r3, %r2
-;   ncrk %r5, %r4, %r2
+;   ncrk %r4, %r4, %r2
-;   ork %r2, %r5, %r3
+;   ork %r2, %r4, %r3
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/bitwise.clif

@@ -13,8 +13,8 @@ block0(v0: i128, v1: i128):
 ; block0:
 ;   vl %v0, 0(%r3)
 ;   vl %v1, 0(%r4)
-;   vn %v7, %v0, %v1
+;   vn %v6, %v0, %v1
-;   vst %v7, 0(%r2)
+;   vst %v6, 0(%r2)
 ;   br %r14
 
 function %band_i64(i64, i64) -> i64 {
@@ -123,8 +123,8 @@ block0(v0: i128, v1: i128):
 ; block0:
 ;   vl %v0, 0(%r3)
 ;   vl %v1, 0(%r4)
-;   vo %v7, %v0, %v1
+;   vo %v6, %v0, %v1
-;   vst %v7, 0(%r2)
+;   vst %v6, 0(%r2)
 ;   br %r14
 
 function %bor_i64(i64, i64) -> i64 {
@@ -233,8 +233,8 @@ block0(v0: i128, v1: i128):
 ; block0:
 ;   vl %v0, 0(%r3)
 ;   vl %v1, 0(%r4)
-;   vx %v7, %v0, %v1
+;   vx %v6, %v0, %v1
-;   vst %v7, 0(%r2)
+;   vst %v6, 0(%r2)
 ;   br %r14
 
 function %bxor_i64(i64, i64) -> i64 {
@@ -343,8 +343,8 @@ block0(v0: i128, v1: i128):
 ; block0:
 ;   vl %v0, 0(%r3)
 ;   vl %v1, 0(%r4)
-;   vnc %v7, %v0, %v1
+;   vnc %v6, %v0, %v1
-;   vst %v7, 0(%r2)
+;   vst %v6, 0(%r2)
 ;   br %r14
 
 function %band_not_i64(i64, i64) -> i64 {
@@ -366,8 +366,9 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   xilf %r3, 4294967295
+;   lgr %r5, %r3
-;   nr %r2, %r3
+;   xilf %r5, 4294967295
+;   nr %r2, %r5
 ;   br %r14
 
 function %band_not_i16(i16, i16) -> i16 {
@@ -377,8 +378,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   xilf %r3, 4294967295
+;   lgr %r5, %r3
-;   nr %r2, %r3
+;   xilf %r5, 4294967295
+;   nr %r2, %r5
 ;   br %r14
 
 function %band_not_i8(i8, i8) -> i8 {
@@ -388,8 +390,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   xilf %r3, 4294967295
+;   lgr %r5, %r3
-;   nr %r2, %r3
+;   xilf %r5, 4294967295
+;   nr %r2, %r5
 ;   br %r14
 
 function %bor_not_i128(i128, i128) -> i128 {
@@ -401,8 +404,8 @@ block0(v0: i128, v1: i128):
 ; block0:
 ;   vl %v0, 0(%r3)
 ;   vl %v1, 0(%r4)
-;   voc %v7, %v0, %v1
+;   voc %v6, %v0, %v1
-;   vst %v7, 0(%r2)
+;   vst %v6, 0(%r2)
 ;   br %r14
 
 function %bor_not_i64(i64, i64) -> i64 {
@@ -424,8 +427,9 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   xilf %r3, 4294967295
+;   lgr %r5, %r3
-;   or %r2, %r3
+;   xilf %r5, 4294967295
+;   or %r2, %r5
 ;   br %r14
 
 function %bor_not_i16(i16, i16) -> i16 {
@@ -435,8 +439,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   xilf %r3, 4294967295
+;   lgr %r5, %r3
-;   or %r2, %r3
+;   xilf %r5, 4294967295
+;   or %r2, %r5
 ;   br %r14
 
 function %bor_not_i8(i8, i8) -> i8 {
@@ -446,8 +451,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   xilf %r3, 4294967295
+;   lgr %r5, %r3
-;   or %r2, %r3
+;   xilf %r5, 4294967295
+;   or %r2, %r5
 ;   br %r14
 
 function %bxor_not_i128(i128, i128) -> i128 {
@@ -459,8 +465,8 @@ block0(v0: i128, v1: i128):
 ; block0:
 ;   vl %v0, 0(%r3)
 ;   vl %v1, 0(%r4)
-;   vnx %v7, %v0, %v1
+;   vnx %v6, %v0, %v1
-;   vst %v7, 0(%r2)
+;   vst %v6, 0(%r2)
 ;   br %r14
 
 function %bxor_not_i64(i64, i64) -> i64 {
@@ -516,8 +522,8 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r3)
-;   vno %v5, %v0, %v0
+;   vno %v4, %v0, %v0
-;   vst %v5, 0(%r2)
+;   vst %v4, 0(%r2)
 ;   br %r14
 
 function %bnot_i64(i64) -> i64 {
@@ -571,8 +577,8 @@ block0(v0: i128, v1: i128, v2: i128):
 ;   vl %v0, 0(%r3)
 ;   vl %v1, 0(%r4)
 ;   vl %v2, 0(%r5)
-;   vsel %v17, %v1, %v2, %v0
+;   vsel %v16, %v1, %v2, %v0
-;   vst %v17, 0(%r2)
+;   vst %v16, 0(%r2)
 ;   br %r14
 
 function %bitselect_i64(i64, i64, i64) -> i64 {
@@ -583,10 +589,11 @@ block0(v0: i64, v1: i64, v2: i64):
 
 ; block0:
 ;   ngr %r3, %r2
-;   xilf %r2, 4294967295
+;   lgr %r5, %r2
-;   xihf %r2, 4294967295
+;   xilf %r5, 4294967295
-;   ngrk %r5, %r4, %r2
+;   xihf %r5, 4294967295
-;   ogrk %r2, %r5, %r3
+;   ngr %r4, %r5
+;   ogrk %r2, %r4, %r3
 ;   br %r14
 
 function %bitselect_i32(i32, i32, i32) -> i32 {
@@ -599,8 +606,8 @@ block0(v0: i32, v1: i32, v2: i32):
 ;   nr %r3, %r2
 ;   lgr %r5, %r2
 ;   xilf %r5, 4294967295
-;   nr %r4, %r5
+;   nrk %r2, %r4, %r5
-;   ork %r2, %r4, %r3
+;   or %r2, %r3
 ;   br %r14
 
 function %bitselect_i16(i16, i16, i16) -> i16 {
@@ -613,8 +620,8 @@ block0(v0: i16, v1: i16, v2: i16):
 ;   nr %r3, %r2
 ;   lgr %r5, %r2
 ;   xilf %r5, 4294967295
-;   nr %r4, %r5
+;   nrk %r2, %r4, %r5
-;   ork %r2, %r4, %r3
+;   or %r2, %r3
 ;   br %r14
 
 function %bitselect_i8(i8, i8, i8) -> i8 {
@@ -627,7 +634,7 @@ block0(v0: i8, v1: i8, v2: i8):
 ;   nr %r3, %r2
 ;   lgr %r5, %r2
 ;   xilf %r5, 4294967295
-;   nr %r4, %r5
+;   nrk %r2, %r4, %r5
-;   ork %r2, %r4, %r3
+;   or %r2, %r3
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/bswap.clif

@@ -28,7 +28,7 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lrvr %r5, %r2
+;   lrvr %r4, %r2
-;   srlk %r2, %r5, 16
+;   srlk %r2, %r4, 16
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/call.clif

@@ -17,8 +17,8 @@ block0(v0: i64):
 ;   aghi %r15, -160
 ;   virtual_sp_offset_adjust 160
 ; block0:
-;   bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1)
+;   bras %r1, 12 ; data %g + 0 ; lg %r5, 0(%r1)
-;   basr %r14, %r3
+;   basr %r14, %r5
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
 
@@ -35,8 +35,8 @@ block0(v0: i32):
 ;   virtual_sp_offset_adjust 160
 ; block0:
 ;   llgfr %r2, %r2
-;   bras %r1, 12 ; data %g + 0 ; lg %r4, 0(%r1)
+;   bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1)
-;   basr %r14, %r4
+;   basr %r14, %r3
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
 
@@ -46,8 +46,7 @@ block0(v0: i32):
 }
 
 ; block0:
-;   lgr %r5, %r2
+;   llgfr %r2, %r2
-;   llgfr %r2, %r5
 ;   br %r14
 
 function %call_uext(i32) -> i64 {
@@ -63,8 +62,8 @@ block0(v0: i32):
 ;   virtual_sp_offset_adjust 160
 ; block0:
 ;   lgfr %r2, %r2
-;   bras %r1, 12 ; data %g + 0 ; lg %r4, 0(%r1)
+;   bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1)
-;   basr %r14, %r4
+;   basr %r14, %r3
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
 
@@ -74,8 +73,7 @@ block0(v0: i32):
 }
 
 ; block0:
-;   lgr %r5, %r2
+;   lgfr %r2, %r2
-;   lgfr %r2, %r5
 ;   br %r14
 
 function %call_colocated(i64) -> i64 {
@@ -107,8 +105,8 @@ block0(v0: i32):
 ;   virtual_sp_offset_adjust 160
 ; block0:
 ;   llgfr %r2, %r2
-;   bras %r1, 12 ; data %g + 0 ; lg %r4, 0(%r1)
+;   bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1)
-;   basr %r14, %r4
+;   basr %r14, %r3
 ;   lmg %r14, %r15, 272(%r15)
 ;   br %r14
 
@@ -151,38 +149,31 @@ block0(v0: i64, v1: i32, v2: i32, v3: i32, v4: i16, v5: i16, v6: i16, v7: i8, v8
 }
 
 ;   stmg %r6, %r15, 48(%r15)
-;   aghi %r15, -16
 ; block0:
-;   stg %r2, 0(%r15)
+;   lg %r11, 160(%r15)
-;   lgr %r10, %r6
+;   lg %r12, 168(%r15)
-;   lg %r11, 176(%r15)
+;   llgc %r13, 183(%r15)
-;   lg %r12, 184(%r15)
+;   lg %r14, 184(%r15)
-;   llgc %r13, 199(%r15)
+;   lg %r8, 192(%r15)
-;   lg %r6, 200(%r15)
+;   llgfr %r3, %r3
-;   lg %r2, 208(%r15)
+;   llgfr %r4, %r4
-;   stg %r2, 8(%r15)
-;   llgfr %r2, %r3
-;   llgfr %r9, %r4
 ;   llgfr %r7, %r5
-;   lgr %r4, %r10
+;   llghr %r6, %r6
-;   llghr %r8, %r4
 ;   llghr %r5, %r11
-;   llghr %r10, %r12
+;   llghr %r12, %r12
-;   llgcr %r4, %r13
+;   llgcr %r13, %r13
-;   llgcr %r13, %r6
+;   llgcr %r14, %r14
-;   lg %r3, 8(%r15)
+;   llgcr %r8, %r8
-;   llgcr %r3, %r3
+;   agrk %r3, %r2, %r3
-;   lg %r11, 0(%r15)
+;   agr %r4, %r7
-;   agrk %r2, %r11, %r2
+;   agrk %r5, %r6, %r5
-;   agrk %r6, %r9, %r7
+;   agrk %r2, %r12, %r13
-;   agrk %r5, %r8, %r5
+;   agrk %r12, %r14, %r8
-;   agrk %r4, %r10, %r4
+;   agr %r3, %r4
-;   agrk %r3, %r13, %r3
+;   agrk %r4, %r5, %r2
-;   agr %r2, %r6
+;   agrk %r3, %r12, %r3
-;   agrk %r4, %r5, %r4
+;   agrk %r2, %r4, %r3
-;   agrk %r5, %r3, %r2
+;   lmg %r6, %r15, 48(%r15)
-;   agrk %r2, %r4, %r5
-;   lmg %r6, %r15, 64(%r15)
 ;   br %r14
 
 function %incoming_args_i128(i128, i128, i128, i128, i128, i128, i128, i128) -> i128 {
@@ -202,25 +193,24 @@ block0(v0: i128, v1: i128, v2: i128, v3: i128, v4: i128, v5: i128, v6: i128, v7:
 ;   vl %v1, 0(%r4)
 ;   vl %v2, 0(%r5)
 ;   vl %v3, 0(%r6)
-;   lg %r4, 160(%r15)
+;   lg %r3, 160(%r15)
-;   vl %v4, 0(%r4)
+;   vl %v4, 0(%r3)
 ;   lg %r3, 168(%r15)
 ;   vl %v5, 0(%r3)
-;   lg %r3, 176(%r15)
+;   lg %r5, 176(%r15)
-;   vl %v6, 0(%r3)
+;   vl %v6, 0(%r5)
-;   lg %r5, 184(%r15)
+;   lg %r4, 184(%r15)
-;   vl %v7, 0(%r5)
+;   vl %v7, 0(%r4)
-;   vaq %v17, %v0, %v1
+;   vaq %v16, %v0, %v1
-;   vaq %v18, %v2, %v3
+;   vaq %v17, %v2, %v3
-;   vaq %v19, %v4, %v5
+;   vaq %v18, %v4, %v5
-;   vaq %v20, %v6, %v7
+;   vaq %v19, %v6, %v7
-;   vaq %v17, %v17, %v18
+;   vaq %v16, %v16, %v17
-;   vaq %v18, %v19, %v20
+;   vaq %v17, %v18, %v19
-;   vaq %v17, %v17, %v18
+;   vaq %v16, %v16, %v17
-;   vst %v17, 0(%r2)
+;   vst %v16, 0(%r2)
 ;   br %r14
 
-
 function %call_sret() -> i64 {
     fn0 = colocated %g(i64 sret)
 

cranelift/filetests/filetests/isa/s390x/concat-split.clif

@@ -8,8 +8,8 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   vlvgp %v5, %r4, %r3
+;   vlvgp %v4, %r4, %r3
-;   vst %v5, 0(%r2)
+;   vst %v4, 0(%r2)
 ;   br %r14
 
 function %isplit_i128(i128) -> i64, i64 {

cranelift/filetests/filetests/isa/s390x/condops.clif

@@ -10,8 +10,8 @@ block0(v0: i8, v1: i64, v2: i64):
 }
 
 ; block0:
-;   llcr %r5, %r2
+;   llcr %r2, %r2
-;   clfi %r5, 42
+;   clfi %r2, 42
 ;   lgr %r2, %r4
 ;   locgre %r2, %r3
 ;   br %r14
@@ -23,8 +23,8 @@ block0(v0: i8, v1: i8, v2: i8):
 }
 
 ; block0:
-;   lbr %r5, %r2
+;   lbr %r2, %r2
-;   chi %r5, 0
+;   chi %r2, 0
 ;   lgr %r2, %r4
 ;   locrlh %r2, %r3
 ;   br %r14
@@ -53,8 +53,8 @@ block0(v0: i32, v1: i8x16, v2: i8x16):
 
 ; block0:
 ;   clfi %r2, 42
-;   vlr %v6, %v25
+;   vlr %v6, %v24
-;   jne 10 ; vlr %v6, %v24
+;   vlr %v24, %v25
-;   vlr %v24, %v6
+;   jne 10 ; vlr %v24, %v6
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/conversions.clif

@@ -8,9 +8,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   vgbm %v5, 0
+;   vgbm %v4, 0
-;   vlvgg %v5, %r3, 1
+;   vlvgg %v4, %r3, 1
-;   vst %v5, 0(%r2)
+;   vst %v4, 0(%r2)
 ;   br %r14
 
 function %uextend_i32_i128(i32) -> i128 {
@@ -20,9 +20,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   vgbm %v5, 0
+;   vgbm %v4, 0
-;   vlvgf %v5, %r3, 3
+;   vlvgf %v4, %r3, 3
-;   vst %v5, 0(%r2)
+;   vst %v4, 0(%r2)
 ;   br %r14
 
 function %uextend_i32_i64(i32) -> i64 {
@@ -42,9 +42,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   vgbm %v5, 0
+;   vgbm %v4, 0
-;   vlvgh %v5, %r3, 7
+;   vlvgh %v4, %r3, 7
-;   vst %v5, 0(%r2)
+;   vst %v4, 0(%r2)
 ;   br %r14
 
 function %uextend_i16_i64(i16) -> i64 {
@@ -74,9 +74,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   vgbm %v5, 0
+;   vgbm %v4, 0
-;   vlvgb %v5, %r3, 15
+;   vlvgb %v4, %r3, 15
-;   vst %v5, 0(%r2)
+;   vst %v4, 0(%r2)
 ;   br %r14
 
 function %uextend_i8_i64(i8) -> i64 {
@@ -116,9 +116,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   srag %r4, %r3, 63
+;   srag %r5, %r3, 63
-;   vlvgp %v6, %r4, %r3
+;   vlvgp %v5, %r5, %r3
-;   vst %v6, 0(%r2)
+;   vst %v5, 0(%r2)
 ;   br %r14
 
 function %sextend_i32_i128(i32) -> i128 {
@@ -128,10 +128,10 @@ block0(v0: i32):
 }
 
 ; block0:
-;   lgfr %r3, %r3
+;   lgfr %r5, %r3
-;   srag %r4, %r3, 63
+;   srag %r3, %r5, 63
-;   vlvgp %v16, %r4, %r3
+;   vlvgp %v7, %r3, %r5
-;   vst %v16, 0(%r2)
+;   vst %v7, 0(%r2)
 ;   br %r14
 
 function %sextend_i32_i64(i32) -> i64 {
@@ -151,10 +151,10 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lghr %r3, %r3
+;   lghr %r5, %r3
-;   srag %r4, %r3, 63
+;   srag %r3, %r5, 63
-;   vlvgp %v16, %r4, %r3
+;   vlvgp %v7, %r3, %r5
-;   vst %v16, 0(%r2)
+;   vst %v7, 0(%r2)
 ;   br %r14
 
 function %sextend_i16_i64(i16) -> i64 {
@@ -184,10 +184,10 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lgbr %r3, %r3
+;   lgbr %r5, %r3
-;   srag %r4, %r3, 63
+;   srag %r3, %r5, 63
-;   vlvgp %v16, %r4, %r3
+;   vlvgp %v7, %r3, %r5
-;   vst %v16, 0(%r2)
+;   vst %v7, 0(%r2)
 ;   br %r14
 
 function %sextend_i8_i64(i8) -> i64 {
@@ -332,12 +332,12 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r3)
-;   vgbm %v5, 0
+;   vgbm %v4, 0
-;   vceqgs %v7, %v0, %v5
+;   vceqgs %v6, %v0, %v4
-;   lghi %r4, 0
+;   lghi %r3, 0
-;   locghine %r4, -1
+;   locghine %r3, -1
-;   vlvgp %v21, %r4, %r4
+;   vlvgp %v20, %r3, %r3
-;   vst %v21, 0(%r2)
+;   vst %v20, 0(%r2)
 ;   br %r14
 
 function %bmask_i128_i64(i128) -> i64 {
@@ -348,8 +348,8 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r2)
-;   vgbm %v3, 0
+;   vgbm %v2, 0
-;   vceqgs %v5, %v0, %v3
+;   vceqgs %v4, %v0, %v2
 ;   lghi %r2, 0
 ;   locghine %r2, -1
 ;   br %r14
@@ -362,8 +362,8 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r2)
-;   vgbm %v3, 0
+;   vgbm %v2, 0
-;   vceqgs %v5, %v0, %v3
+;   vceqgs %v4, %v0, %v2
 ;   lhi %r2, 0
 ;   lochine %r2, -1
 ;   br %r14
@@ -376,8 +376,8 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r2)
-;   vgbm %v3, 0
+;   vgbm %v2, 0
-;   vceqgs %v5, %v0, %v3
+;   vceqgs %v4, %v0, %v2
 ;   lhi %r2, 0
 ;   lochine %r2, -1
 ;   br %r14
@@ -390,8 +390,8 @@ block0(v0: i128):
 
 ; block0:
 ;   vl %v0, 0(%r2)
-;   vgbm %v3, 0
+;   vgbm %v2, 0
-;   vceqgs %v5, %v0, %v3
+;   vceqgs %v4, %v0, %v2
 ;   lhi %r2, 0
 ;   lochine %r2, -1
 ;   br %r14
@@ -404,10 +404,10 @@ block0(v0: i64, v1: i64):
 
 ; block0:
 ;   cghi %r4, 0
-;   lghi %r5, 0
+;   lghi %r4, 0
-;   locghilh %r5, -1
+;   locghilh %r4, -1
-;   vlvgp %v18, %r5, %r5
+;   vlvgp %v17, %r4, %r4
-;   vst %v18, 0(%r2)
+;   vst %v17, 0(%r2)
 ;   br %r14
 
 function %bmask_i64_i64(i64, i64) -> i64 {
@@ -466,10 +466,10 @@ block0(v0: i32, v1: i32):
 
 ; block0:
 ;   chi %r4, 0
-;   lghi %r5, 0
+;   lghi %r4, 0
-;   locghilh %r5, -1
+;   locghilh %r4, -1
-;   vlvgp %v18, %r5, %r5
+;   vlvgp %v17, %r4, %r4
-;   vst %v18, 0(%r2)
+;   vst %v17, 0(%r2)
 ;   br %r14
 
 function %bmask_i32_i64(i32, i32) -> i64 {
@@ -531,8 +531,8 @@ block0(v0: i16, v1: i16):
 ;   chi %r3, 0
 ;   lghi %r3, 0
 ;   locghilh %r3, -1
-;   vlvgp %v20, %r3, %r3
+;   vlvgp %v19, %r3, %r3
-;   vst %v20, 0(%r2)
+;   vst %v19, 0(%r2)
 ;   br %r14
 
 function %bmask_i16_i64(i16, i16) -> i64 {
@@ -542,8 +542,8 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   lhr %r2, %r3
+;   lhr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lghi %r2, 0
 ;   locghilh %r2, -1
 ;   br %r14
@@ -555,8 +555,8 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   lhr %r2, %r3
+;   lhr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
@@ -568,8 +568,8 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   lhr %r2, %r3
+;   lhr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
@@ -581,8 +581,8 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   lhr %r2, %r3
+;   lhr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
@@ -598,8 +598,8 @@ block0(v0: i8, v1: i8):
 ;   chi %r3, 0
 ;   lghi %r3, 0
 ;   locghilh %r3, -1
-;   vlvgp %v20, %r3, %r3
+;   vlvgp %v19, %r3, %r3
-;   vst %v20, 0(%r2)
+;   vst %v19, 0(%r2)
 ;   br %r14
 
 function %bmask_i8_i64(i8, i8) -> i64 {
@@ -609,8 +609,8 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lbr %r2, %r3
+;   lbr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lghi %r2, 0
 ;   locghilh %r2, -1
 ;   br %r14
@@ -622,8 +622,8 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lbr %r2, %r3
+;   lbr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
@@ -635,8 +635,8 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lbr %r2, %r3
+;   lbr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
@@ -648,8 +648,8 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lbr %r2, %r3
+;   lbr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
@@ -665,8 +665,8 @@ block0(v0: i8, v1: i8):
 ;   chi %r3, 0
 ;   lghi %r3, 0
 ;   locghilh %r3, -1
-;   vlvgp %v20, %r3, %r3
+;   vlvgp %v19, %r3, %r3
-;   vst %v20, 0(%r2)
+;   vst %v19, 0(%r2)
 ;   br %r14
 
 function %bmask_i8_i64(i8, i8) -> i64 {
@@ -676,8 +676,8 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lbr %r2, %r3
+;   lbr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lghi %r2, 0
 ;   locghilh %r2, -1
 ;   br %r14
@@ -689,8 +689,8 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lbr %r2, %r3
+;   lbr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
@@ -702,8 +702,8 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lbr %r2, %r3
+;   lbr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14
@@ -715,8 +715,8 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lbr %r2, %r3
+;   lbr %r5, %r3
-;   chi %r2, 0
+;   chi %r5, 0
 ;   lhi %r2, 0
 ;   lochilh %r2, -1
 ;   br %r14

cranelift/filetests/filetests/isa/s390x/div-traps.clif

@@ -17,11 +17,13 @@ block0(v0: i64, v1: i64):
 ;   llihf %r4, 2147483647
 ;   iilf %r4, 4294967295
 ;   xgr %r4, %r2
-;   ngrk %r5, %r4, %r3
+;   lgr %r5, %r2
-;   cgite %r5, -1
+;   ngr %r4, %r3
-;   lgr %r5, %r3
+;   lgr %r2, %r3
-;   lgr %r3, %r2
+;   cgite %r4, -1
-;   dsgr %r2, %r5
+;   lgr %r4, %r2
+;   lgr %r3, %r5
+;   dsgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -34,8 +36,8 @@ block0(v0: i64):
 
 ; block0:
 ;   lgr %r3, %r2
-;   lghi %r5, 2
+;   lghi %r4, 2
-;   dsgr %r2, %r5
+;   dsgr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -45,19 +47,21 @@ block0(v0: i32, v1: i32):
   return v2
 }
 
+;   stmg %r7, %r15, 56(%r15)
 ; block0:
-;   lgfr %r2, %r2
+;   lgfr %r5, %r2
+;   lgr %r7, %r5
 ;   cite %r3, 0
 ;   iilf %r5, 2147483647
-;   lgr %r4, %r2
+;   lgr %r4, %r7
-;   xr %r5, %r4
+;   xrk %r2, %r5, %r4
-;   nr %r5, %r3
+;   nrk %r4, %r2, %r3
-;   lgr %r4, %r3
+;   lgr %r5, %r3
-;   cite %r5, -1
+;   cite %r4, -1
-;   lgr %r3, %r2
+;   lgr %r3, %r7
-;   lgr %r2, %r4
+;   dsgfr %r2, %r5
-;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
+;   lmg %r7, %r15, 56(%r15)
 ;   br %r14
 
 function %sdiv_i32_imm(i32) -> i32 {
@@ -69,8 +73,8 @@ block0(v0: i32):
 
 ; block0:
 ;   lgfr %r3, %r2
-;   lhi %r4, 2
+;   lhi %r2, 2
-;   dsgfr %r2, %r4
+;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -81,14 +85,14 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   lghr %r2, %r2
+;   lghr %r5, %r2
 ;   lhr %r4, %r3
 ;   cite %r4, 0
-;   lhi %r5, 32767
+;   lhi %r2, 32767
-;   lgr %r3, %r2
+;   lgr %r3, %r5
-;   xr %r5, %r3
+;   xrk %r5, %r2, %r3
-;   nr %r5, %r4
+;   nrk %r2, %r5, %r4
-;   cite %r5, -1
+;   cite %r2, -1
 ;   dsgfr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
@@ -102,8 +106,8 @@ block0(v0: i16):
 
 ; block0:
 ;   lghr %r3, %r2
-;   lhi %r4, 2
+;   lhi %r2, 2
-;   dsgfr %r2, %r4
+;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -114,14 +118,14 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lgbr %r2, %r2
+;   lgbr %r5, %r2
 ;   lbr %r4, %r3
 ;   cite %r4, 0
-;   lhi %r5, 127
+;   lhi %r2, 127
-;   lgr %r3, %r2
+;   lgr %r3, %r5
-;   xr %r5, %r3
+;   xrk %r5, %r2, %r3
-;   nr %r5, %r4
+;   nrk %r2, %r5, %r4
-;   cite %r5, -1
+;   cite %r2, -1
 ;   dsgfr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
@@ -135,8 +139,8 @@ block0(v0: i8):
 
 ; block0:
 ;   lgbr %r3, %r2
-;   lhi %r4, 2
+;   lhi %r2, 2
-;   dsgfr %r2, %r4
+;   dsgfr %r2, %r2
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -147,13 +151,13 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   lgr %r4, %r2
+;   lgr %r5, %r2
 ;   lghi %r2, 0
 ;   cgite %r3, 0
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   lgr %r3, %r4
+;   lgr %r3, %r5
-;   lgr %r4, %r5
+;   lgr %r5, %r4
-;   dlgr %r2, %r4
+;   dlgr %r2, %r5
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -179,13 +183,13 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   lgr %r4, %r2
+;   lgr %r5, %r2
 ;   lhi %r2, 0
 ;   cite %r3, 0
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   lgr %r3, %r4
+;   lgr %r3, %r5
-;   lgr %r4, %r5
+;   lgr %r5, %r4
-;   dlr %r2, %r4
+;   dlr %r2, %r5
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -210,17 +214,19 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
-;   lhi %r3, 0
+;   lhi %r5, 0
-;   lgr %r5, %r3
+;   lgr %r8, %r5
 ;   llhr %r3, %r2
-;   lgr %r2, %r4
+;   lgr %r5, %r4
-;   llhr %r4, %r2
+;   llhr %r5, %r5
-;   cite %r4, 0
+;   cite %r5, 0
-;   lgr %r2, %r5
+;   lgr %r2, %r8
-;   dlr %r2, %r4
+;   dlr %r2, %r5
 ;   lgr %r2, %r3
+;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
 
 function %udiv_i16_imm(i16) -> i16 {
@@ -231,12 +237,12 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lhi %r5, 0
+;   lhi %r4, 0
-;   lgr %r4, %r5
+;   lgr %r5, %r4
 ;   llhr %r3, %r2
-;   lhi %r5, 2
+;   lhi %r4, 2
-;   lgr %r2, %r4
+;   lgr %r2, %r5
-;   dlr %r2, %r5
+;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -246,17 +252,19 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
-;   lhi %r3, 0
+;   lhi %r5, 0
-;   lgr %r5, %r3
+;   lgr %r8, %r5
 ;   llcr %r3, %r2
-;   lgr %r2, %r4
+;   lgr %r5, %r4
-;   llcr %r4, %r2
+;   llcr %r5, %r5
-;   cite %r4, 0
+;   cite %r5, 0
-;   lgr %r2, %r5
+;   lgr %r2, %r8
-;   dlr %r2, %r4
+;   dlr %r2, %r5
 ;   lgr %r2, %r3
+;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
 
 function %udiv_i8_imm(i8) -> i8 {
@@ -267,12 +275,12 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lhi %r5, 0
+;   lhi %r4, 0
-;   lgr %r4, %r5
+;   lgr %r5, %r4
 ;   llcr %r3, %r2
-;   lhi %r5, 2
+;   lhi %r4, 2
-;   lgr %r2, %r4
+;   lgr %r2, %r5
-;   dlr %r2, %r5
+;   dlr %r2, %r4
 ;   lgr %r2, %r3
 ;   br %r14
 
@@ -285,10 +293,10 @@ block0(v0: i64, v1: i64):
 ; block0:
 ;   cgite %r3, 0
 ;   cghi %r3, -1
-;   lgr %r5, %r3
+;   lgr %r4, %r3
 ;   lgr %r3, %r2
 ;   locghie %r3, 0
-;   dsgr %r2, %r5
+;   dsgr %r2, %r4
 ;   br %r14
 
 function %srem_i32(i32, i32) -> i32 {
@@ -298,10 +306,11 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   lgr %r4, %r3
+;   lgr %r5, %r3
 ;   lgfr %r3, %r2
-;   cite %r4, 0
+;   lgr %r2, %r5
-;   dsgfr %r2, %r4
+;   cite %r2, 0
+;   dsgfr %r2, %r2
 ;   br %r14
 
 function %srem_i16(i16, i16) -> i16 {
@@ -311,11 +320,11 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   lghr %r2, %r2
+;   lghr %r5, %r2
-;   lgr %r5, %r2
+;   lgr %r2, %r5
 ;   lhr %r4, %r3
 ;   cite %r4, 0
-;   lgr %r3, %r5
+;   lgr %r3, %r2
 ;   dsgfr %r2, %r4
 ;   br %r14
 
@@ -326,11 +335,11 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   lgbr %r2, %r2
+;   lgbr %r5, %r2
-;   lgr %r5, %r2
+;   lgr %r2, %r5
 ;   lbr %r4, %r3
 ;   cite %r4, 0
-;   lgr %r3, %r5
+;   lgr %r3, %r2
 ;   dsgfr %r2, %r4
 ;   br %r14
 
@@ -341,13 +350,13 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   lgr %r4, %r2
+;   lgr %r5, %r2
 ;   lghi %r2, 0
 ;   cgite %r3, 0
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   lgr %r3, %r4
+;   lgr %r3, %r5
-;   lgr %r4, %r5
+;   lgr %r5, %r4
-;   dlgr %r2, %r4
+;   dlgr %r2, %r5
 ;   br %r14
 
 function %urem_i32(i32, i32) -> i32 {
@@ -357,13 +366,13 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   lgr %r4, %r2
+;   lgr %r5, %r2
 ;   lhi %r2, 0
 ;   cite %r3, 0
-;   lgr %r5, %r3
+;   lgr %r4, %r3
-;   lgr %r3, %r4
+;   lgr %r3, %r5
-;   lgr %r4, %r5
+;   lgr %r5, %r4
-;   dlr %r2, %r4
+;   dlr %r2, %r5
 ;   br %r14
 
 function %urem_i16(i16, i16) -> i16 {
@@ -372,16 +381,18 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
+;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
-;   lhi %r3, 0
+;   lhi %r5, 0
-;   lgr %r5, %r3
+;   lgr %r8, %r5
 ;   llhr %r3, %r2
-;   lgr %r2, %r4
+;   lgr %r5, %r4
-;   llhr %r4, %r2
+;   llhr %r5, %r5
-;   cite %r4, 0
+;   cite %r5, 0
-;   lgr %r2, %r5
+;   lgr %r2, %r8
-;   dlr %r2, %r4
+;   dlr %r2, %r5
+;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
 
 function %urem_i8(i8, i8) -> i8 {
@@ -390,15 +401,17 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
+;   stmg %r8, %r15, 64(%r15)
 ; block0:
 ;   lgr %r4, %r3
-;   lhi %r3, 0
+;   lhi %r5, 0
-;   lgr %r5, %r3
+;   lgr %r8, %r5
 ;   llcr %r3, %r2
-;   lgr %r2, %r4
+;   lgr %r5, %r4
-;   llcr %r4, %r2
+;   llcr %r5, %r5
-;   cite %r4, 0
+;   cite %r5, 0
-;   lgr %r2, %r5
+;   lgr %r2, %r8
-;   dlr %r2, %r4
+;   dlr %r2, %r5
+;   lmg %r8, %r15, 64(%r15)
 ;   br %r14
 

cranelift/filetests/filetests/isa/s390x/floating-point-arch13.clif

@@ -10,14 +10,14 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 256 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 256 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wclfeb %v21, %f0, 0, 5
+;   wclfeb %v20, %f0, 0, 5
-;   vlgvf %r2, %v21, 0
+;   vlgvf %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f32_i8(f32) -> i8 {
@@ -29,14 +29,14 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 128 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 128 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -129 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -129 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wcfeb %v21, %f0, 0, 5
+;   wcfeb %v20, %f0, 0, 5
-;   vlgvf %r2, %v21, 0
+;   vlgvf %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_uint_f32_i16(f32) -> i16 {
@@ -48,14 +48,14 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 65536 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 65536 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wclfeb %v21, %f0, 0, 5
+;   wclfeb %v20, %f0, 0, 5
-;   vlgvf %r2, %v21, 0
+;   vlgvf %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f32_i16(f32) -> i16 {
@@ -67,14 +67,14 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 32768 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 32768 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -32769 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -32769 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wcfeb %v21, %f0, 0, 5
+;   wcfeb %v20, %f0, 0, 5
-;   vlgvf %r2, %v21, 0
+;   vlgvf %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_uint_f32_i32(f32) -> i32 {
@@ -86,14 +86,14 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 4294967300 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 4294967300 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wclfeb %v21, %f0, 0, 5
+;   wclfeb %v20, %f0, 0, 5
-;   vlgvf %r2, %v21, 0
+;   vlgvf %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f32_i32(f32) -> i32 {
@@ -105,14 +105,14 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 2147483600 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 2147483600 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -2147484000 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -2147484000 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wcfeb %v21, %f0, 0, 5
+;   wcfeb %v20, %f0, 0, 5
-;   vlgvf %r2, %v21, 0
+;   vlgvf %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_uint_f32_i64(f32) -> i64 {
@@ -124,15 +124,15 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 18446744000000000000 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 18446744000000000000 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wldeb %v21, %f0
+;   wldeb %v20, %f0
-;   wclgdb %v23, %v21, 0, 5
+;   wclgdb %v22, %v20, 0, 5
-;   vlgvg %r2, %v23, 0
+;   vlgvg %r2, %v22, 0
 ;   br %r14
 
 function %fcvt_to_sint_f32_i64(f32) -> i64 {
@@ -144,15 +144,15 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 9223372000000000000 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 9223372000000000000 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -9223373000000000000 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -9223373000000000000 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wldeb %v21, %f0
+;   wldeb %v20, %f0
-;   wcgdb %v23, %v21, 0, 5
+;   wcgdb %v22, %v20, 0, 5
-;   vlgvg %r2, %v23, 0
+;   vlgvg %r2, %v22, 0
 ;   br %r14
 
 function %fcvt_to_uint_f64_i8(f64) -> i8 {
@@ -164,14 +164,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 256 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 256 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wclgdb %v21, %f0, 0, 5
+;   wclgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f64_i8(f64) -> i8 {
@@ -183,14 +183,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 128 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 128 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -129 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -129 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wcgdb %v21, %f0, 0, 5
+;   wcgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_uint_f64_i16(f64) -> i16 {
@@ -202,14 +202,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 65536 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 65536 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wclgdb %v21, %f0, 0, 5
+;   wclgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f64_i16(f64) -> i16 {
@@ -221,14 +221,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 32768 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 32768 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -32769 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -32769 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wcgdb %v21, %f0, 0, 5
+;   wcgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_uint_f64_i32(f64) -> i32 {
@@ -240,14 +240,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 4294967296 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 4294967296 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wclgdb %v21, %f0, 0, 5
+;   wclgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f64_i32(f64) -> i32 {
@@ -259,14 +259,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 2147483648 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 2147483648 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -2147483649 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -2147483649 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wcgdb %v21, %f0, 0, 5
+;   wcgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_uint_f64_i64(f64) -> i64 {
@@ -278,14 +278,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 18446744073709552000 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 18446744073709552000 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wclgdb %v21, %f0, 0, 5
+;   wclgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f64_i64(f64) -> i64 {
@@ -297,14 +297,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 9223372036854776000 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 9223372036854776000 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -9223372036854778000 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -9223372036854778000 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wcgdb %v21, %f0, 0, 5
+;   wcgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_from_uint_i8_f32(i8) -> f32 {
@@ -314,9 +314,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   llcr %r5, %r2
+;   llcr %r4, %r2
-;   vlvgf %v5, %r5, 0
+;   vlvgf %v4, %r4, 0
-;   wcelfb %f0, %f5, 0, 4
+;   wcelfb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i8_f32(i8) -> f32 {
@@ -326,9 +326,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lbr %r5, %r2
+;   lbr %r4, %r2
-;   vlvgf %v5, %r5, 0
+;   vlvgf %v4, %r4, 0
-;   wcefb %f0, %f5, 0, 4
+;   wcefb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_uint_i16_f32(i16) -> f32 {
@@ -338,9 +338,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   llhr %r5, %r2
+;   llhr %r4, %r2
-;   vlvgf %v5, %r5, 0
+;   vlvgf %v4, %r4, 0
-;   wcelfb %f0, %f5, 0, 4
+;   wcelfb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i16_f32(i16) -> f32 {
@@ -350,9 +350,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lhr %r5, %r2
+;   lhr %r4, %r2
-;   vlvgf %v5, %r5, 0
+;   vlvgf %v4, %r4, 0
-;   wcefb %f0, %f5, 0, 4
+;   wcefb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_uint_i32_f32(i32) -> f32 {
@@ -362,8 +362,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   vlvgf %v3, %r2, 0
+;   vlvgf %v2, %r2, 0
-;   wcelfb %f0, %f3, 0, 4
+;   wcelfb %f0, %f2, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i32_f32(i32) -> f32 {
@@ -373,8 +373,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   vlvgf %v3, %r2, 0
+;   vlvgf %v2, %r2, 0
-;   wcefb %f0, %f3, 0, 4
+;   wcefb %f0, %f2, 0, 4
 ;   br %r14
 
 function %fcvt_from_uint_i64_f32(i64) -> f32 {
@@ -384,9 +384,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldgr %f3, %r2
+;   ldgr %f2, %r2
-;   wcdlgb %f5, %f3, 0, 3
+;   wcdlgb %f4, %f2, 0, 3
-;   ledbra %f0, %f5, 4
+;   ledbra %f0, %f4, 4
 ;   br %r14
 
 function %fcvt_from_sint_i64_f32(i64) -> f32 {
@@ -396,9 +396,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldgr %f3, %r2
+;   ldgr %f2, %r2
-;   wcdgb %f5, %f3, 0, 3
+;   wcdgb %f4, %f2, 0, 3
-;   ledbra %f0, %f5, 4
+;   ledbra %f0, %f4, 4
 ;   br %r14
 
 function %fcvt_from_uint_i8_f64(i8) -> f64 {
@@ -408,9 +408,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   llgcr %r5, %r2
+;   llgcr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdlgb %f0, %f5, 0, 4
+;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i8_f64(i8) -> f64 {
@@ -420,9 +420,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lgbr %r5, %r2
+;   lgbr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdgb %f0, %f5, 0, 4
+;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_uint_i16_f64(i16) -> f64 {
@@ -432,9 +432,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   llghr %r5, %r2
+;   llghr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdlgb %f0, %f5, 0, 4
+;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i16_f64(i16) -> f64 {
@@ -444,9 +444,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lghr %r5, %r2
+;   lghr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdgb %f0, %f5, 0, 4
+;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_uint_i32_f64(i32) -> f64 {
@@ -456,9 +456,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   llgfr %r5, %r2
+;   llgfr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdlgb %f0, %f5, 0, 4
+;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i32_f64(i32) -> f64 {
@@ -468,9 +468,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   lgfr %r5, %r2
+;   lgfr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdgb %f0, %f5, 0, 4
+;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_uint_i64_f64(i64) -> f64 {
@@ -480,8 +480,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldgr %f3, %r2
+;   ldgr %f2, %r2
-;   wcdlgb %f0, %f3, 0, 4
+;   wcdlgb %f0, %f2, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i64_f64(i64) -> f64 {
@@ -491,8 +491,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldgr %f3, %r2
+;   ldgr %f2, %r2
-;   wcdgb %f0, %f3, 0, 4
+;   wcdgb %f0, %f2, 0, 4
 ;   br %r14
 
 function %fcvt_to_uint_sat_f32_i8(f32) -> i8 {
@@ -502,8 +502,8 @@ block0(v0: f32):
 }
 
 ; block0:
-;   wclfeb %f3, %f0, 0, 5
+;   wclfeb %f2, %f0, 0, 5
-;   vlgvf %r2, %v3, 0
+;   vlgvf %r2, %v2, 0
 ;   clfi %r2, 256
 ;   lochih %r2, 255
 ;   br %r14
@@ -515,8 +515,8 @@ block0(v0: f32):
 }
 
 ; block0:
-;   wcfeb %f3, %f0, 0, 5
+;   wcfeb %f2, %f0, 0, 5
-;   vlgvf %r2, %v3, 0
+;   vlgvf %r2, %v2, 0
 ;   cebr %f0, %f0
 ;   lochio %r2, 0
 ;   chi %r2, 127
@@ -532,8 +532,8 @@ block0(v0: f32):
 }
 
 ; block0:
-;   wclfeb %f3, %f0, 0, 5
+;   wclfeb %f2, %f0, 0, 5
-;   vlgvf %r2, %v3, 0
+;   vlgvf %r2, %v2, 0
 ;   clfi %r2, 65535
 ;   lochih %r2, -1
 ;   br %r14
@@ -545,8 +545,8 @@ block0(v0: f32):
 }
 
 ; block0:
-;   wcfeb %f3, %f0, 0, 5
+;   wcfeb %f2, %f0, 0, 5
-;   vlgvf %r2, %v3, 0
+;   vlgvf %r2, %v2, 0
 ;   cebr %f0, %f0
 ;   lochio %r2, 0
 ;   chi %r2, 32767
@@ -562,8 +562,8 @@ block0(v0: f32):
 }
 
 ; block0:
-;   wclfeb %f3, %f0, 0, 5
+;   wclfeb %f2, %f0, 0, 5
-;   vlgvf %r2, %v3, 0
+;   vlgvf %r2, %v2, 0
 ;   br %r14
 
 function %fcvt_to_sint_sat_f32_i32(f32) -> i32 {
@@ -573,8 +573,8 @@ block0(v0: f32):
 }
 
 ; block0:
-;   wcfeb %f3, %f0, 0, 5
+;   wcfeb %f2, %f0, 0, 5
-;   vlgvf %r2, %v3, 0
+;   vlgvf %r2, %v2, 0
 ;   cebr %f0, %f0
 ;   lochio %r2, 0
 ;   br %r14
@@ -586,9 +586,9 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ldebr %f3, %f0
+;   ldebr %f2, %f0
-;   wclgdb %f5, %f3, 0, 5
+;   wclgdb %f4, %f2, 0, 5
-;   lgdr %r2, %f5
+;   lgdr %r2, %f4
 ;   br %r14
 
 function %fcvt_to_sint_sat_f32_i64(f32) -> i64 {
@@ -598,9 +598,9 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ldebr %f3, %f0
+;   ldebr %f2, %f0
-;   wcgdb %f5, %f3, 0, 5
+;   wcgdb %f4, %f2, 0, 5
-;   lgdr %r2, %f5
+;   lgdr %r2, %f4
 ;   cebr %f0, %f0
 ;   locghio %r2, 0
 ;   br %r14
@@ -612,8 +612,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wclgdb %f3, %f0, 0, 5
+;   wclgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   clgfi %r2, 256
 ;   locghih %r2, 255
 ;   br %r14
@@ -625,8 +625,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wcgdb %f3, %f0, 0, 5
+;   wcgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   cdbr %f0, %f0
 ;   locghio %r2, 0
 ;   cghi %r2, 127
@@ -642,8 +642,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wclgdb %f3, %f0, 0, 5
+;   wclgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   clgfi %r2, 65535
 ;   locghih %r2, -1
 ;   br %r14
@@ -655,8 +655,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wcgdb %f3, %f0, 0, 5
+;   wcgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   cdbr %f0, %f0
 ;   locghio %r2, 0
 ;   cghi %r2, 32767
@@ -672,11 +672,11 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wclgdb %f3, %f0, 0, 5
+;   wclgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
-;   llilf %r5, 4294967295
+;   llilf %r4, 4294967295
-;   clgr %r2, %r5
+;   clgr %r2, %r4
-;   locgrh %r2, %r5
+;   locgrh %r2, %r4
 ;   br %r14
 
 function %fcvt_to_sint_sat_f64_i32(f64) -> i32 {
@@ -686,16 +686,16 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wcgdb %f3, %f0, 0, 5
+;   wcgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   cdbr %f0, %f0
 ;   locghio %r2, 0
-;   lgfi %r4, 2147483647
+;   lgfi %r3, 2147483647
+;   cgr %r2, %r3
+;   locgrh %r2, %r3
+;   lgfi %r4, -2147483648
 ;   cgr %r2, %r4
-;   locgrh %r2, %r4
+;   locgrl %r2, %r4
-;   lgfi %r5, -2147483648
-;   cgr %r2, %r5
-;   locgrl %r2, %r5
 ;   br %r14
 
 function %fcvt_to_uint_sat_f64_i64(f64) -> i64 {
@@ -705,8 +705,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wclgdb %f3, %f0, 0, 5
+;   wclgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   br %r14
 
 function %fcvt_to_sint_sat_f64_i64(f64) -> i64 {
@@ -716,8 +716,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wcgdb %f3, %f0, 0, 5
+;   wcgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   cdbr %f0, %f0
 ;   locghio %r2, 0
 ;   br %r14

cranelift/filetests/filetests/isa/s390x/floating-point.clif

@@ -395,8 +395,8 @@ block0(v0: f32, v1: f32):
 }
 
 ; block0:
-;   bras %r1, 8 ; data.f32 NaN ; le %f4, 0(%r1)
+;   bras %r1, 8 ; data.f32 NaN ; le %f3, 0(%r1)
-;   vsel %v0, %v0, %v2, %v4
+;   vsel %v0, %v0, %v2, %v3
 ;   br %r14
 
 function %fcopysign_f64(f64, f64) -> f64 {
@@ -406,8 +406,8 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   bras %r1, 12 ; data.f64 NaN ; ld %f4, 0(%r1)
+;   bras %r1, 12 ; data.f64 NaN ; ld %f3, 0(%r1)
-;   vsel %v0, %v0, %v2, %v4
+;   vsel %v0, %v0, %v2, %v3
 ;   br %r14
 
 function %fcvt_to_uint_f32_i8(f32) -> i8 {
@@ -419,15 +419,15 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 256 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 256 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wldeb %v21, %f0
+;   wldeb %v20, %f0
-;   wclgdb %v23, %v21, 0, 5
+;   wclgdb %v22, %v20, 0, 5
-;   vlgvg %r2, %v23, 0
+;   vlgvg %r2, %v22, 0
 ;   br %r14
 
 function %fcvt_to_sint_f32_i8(f32) -> i8 {
@@ -439,15 +439,15 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 128 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 128 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -129 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -129 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wldeb %v21, %f0
+;   wldeb %v20, %f0
-;   wcgdb %v23, %v21, 0, 5
+;   wcgdb %v22, %v20, 0, 5
-;   vlgvg %r2, %v23, 0
+;   vlgvg %r2, %v22, 0
 ;   br %r14
 
 function %fcvt_to_uint_f32_i16(f32) -> i16 {
@@ -459,15 +459,15 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 65536 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 65536 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wldeb %v21, %f0
+;   wldeb %v20, %f0
-;   wclgdb %v23, %v21, 0, 5
+;   wclgdb %v22, %v20, 0, 5
-;   vlgvg %r2, %v23, 0
+;   vlgvg %r2, %v22, 0
 ;   br %r14
 
 function %fcvt_to_sint_f32_i16(f32) -> i16 {
@@ -479,15 +479,15 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 32768 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 32768 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -32769 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -32769 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wldeb %v21, %f0
+;   wldeb %v20, %f0
-;   wcgdb %v23, %v21, 0, 5
+;   wcgdb %v22, %v20, 0, 5
-;   vlgvg %r2, %v23, 0
+;   vlgvg %r2, %v22, 0
 ;   br %r14
 
 function %fcvt_to_uint_f32_i32(f32) -> i32 {
@@ -499,15 +499,15 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 4294967300 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 4294967300 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wldeb %v21, %f0
+;   wldeb %v20, %f0
-;   wclgdb %v23, %v21, 0, 5
+;   wclgdb %v22, %v20, 0, 5
-;   vlgvg %r2, %v23, 0
+;   vlgvg %r2, %v22, 0
 ;   br %r14
 
 function %fcvt_to_sint_f32_i32(f32) -> i32 {
@@ -519,15 +519,15 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 2147483600 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 2147483600 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -2147484000 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -2147484000 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wldeb %v21, %f0
+;   wldeb %v20, %f0
-;   wcgdb %v23, %v21, 0, 5
+;   wcgdb %v22, %v20, 0, 5
-;   vlgvg %r2, %v23, 0
+;   vlgvg %r2, %v22, 0
 ;   br %r14
 
 function %fcvt_to_uint_f32_i64(f32) -> i64 {
@@ -539,15 +539,15 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 18446744000000000000 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 18446744000000000000 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wldeb %v21, %f0
+;   wldeb %v20, %f0
-;   wclgdb %v23, %v21, 0, 5
+;   wclgdb %v22, %v20, 0, 5
-;   vlgvg %r2, %v23, 0
+;   vlgvg %r2, %v22, 0
 ;   br %r14
 
 function %fcvt_to_sint_f32_i64(f32) -> i64 {
@@ -559,15 +559,15 @@ block0(v0: f32):
 ; block0:
 ;   cebr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 8 ; data.f32 9223372000000000000 ; le %f5, 0(%r1)
+;   bras %r1, 8 ; data.f32 9223372000000000000 ; le %f4, 0(%r1)
-;   cebr %f0, %f5
+;   cebr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 8 ; data.f32 -9223373000000000000 ; vlef %v17, 0(%r1), 0
+;   bras %r1, 8 ; data.f32 -9223373000000000000 ; vlef %v16, 0(%r1), 0
-;   wfcsb %f0, %v17
+;   wfcsb %f0, %v16
 ;   jnle 6 ; trap
-;   wldeb %v21, %f0
+;   wldeb %v20, %f0
-;   wcgdb %v23, %v21, 0, 5
+;   wcgdb %v22, %v20, 0, 5
-;   vlgvg %r2, %v23, 0
+;   vlgvg %r2, %v22, 0
 ;   br %r14
 
 function %fcvt_to_uint_f64_i8(f64) -> i8 {
@@ -579,14 +579,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 256 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 256 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wclgdb %v21, %f0, 0, 5
+;   wclgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f64_i8(f64) -> i8 {
@@ -598,14 +598,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 128 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 128 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -129 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -129 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wcgdb %v21, %f0, 0, 5
+;   wcgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_uint_f64_i16(f64) -> i16 {
@@ -617,14 +617,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 65536 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 65536 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wclgdb %v21, %f0, 0, 5
+;   wclgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f64_i16(f64) -> i16 {
@@ -636,14 +636,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 32768 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 32768 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -32769 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -32769 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wcgdb %v21, %f0, 0, 5
+;   wcgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_uint_f64_i32(f64) -> i32 {
@@ -655,14 +655,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 4294967296 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 4294967296 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wclgdb %v21, %f0, 0, 5
+;   wclgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f64_i32(f64) -> i32 {
@@ -674,14 +674,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 2147483648 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 2147483648 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -2147483649 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -2147483649 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wcgdb %v21, %f0, 0, 5
+;   wcgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_uint_f64_i64(f64) -> i64 {
@@ -693,14 +693,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 18446744073709552000 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 18446744073709552000 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wclgdb %v21, %f0, 0, 5
+;   wclgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_to_sint_f64_i64(f64) -> i64 {
@@ -712,14 +712,14 @@ block0(v0: f64):
 ; block0:
 ;   cdbr %f0, %f0
 ;   jno 6 ; trap
-;   bras %r1, 12 ; data.f64 9223372036854776000 ; ld %f5, 0(%r1)
+;   bras %r1, 12 ; data.f64 9223372036854776000 ; ld %f4, 0(%r1)
-;   cdbr %f0, %f5
+;   cdbr %f0, %f4
 ;   jnhe 6 ; trap
-;   bras %r1, 12 ; data.f64 -9223372036854778000 ; vleg %v17, 0(%r1), 0
+;   bras %r1, 12 ; data.f64 -9223372036854778000 ; vleg %v16, 0(%r1), 0
-;   wfcdb %f0, %v17
+;   wfcdb %f0, %v16
 ;   jnle 6 ; trap
-;   wcgdb %v21, %f0, 0, 5
+;   wcgdb %v20, %f0, 0, 5
-;   vlgvg %r2, %v21, 0
+;   vlgvg %r2, %v20, 0
 ;   br %r14
 
 function %fcvt_from_uint_i8_f32(i8) -> f32 {
@@ -729,10 +729,10 @@ block0(v0: i8):
 }
 
 ; block0:
-;   llgcr %r5, %r2
+;   llgcr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdlgb %f7, %f5, 0, 3
+;   wcdlgb %f6, %f4, 0, 3
-;   ledbra %f0, %f7, 4
+;   ledbra %f0, %f6, 4
 ;   br %r14
 
 function %fcvt_from_sint_i8_f32(i8) -> f32 {
@@ -742,10 +742,10 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lgbr %r5, %r2
+;   lgbr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdgb %f7, %f5, 0, 3
+;   wcdgb %f6, %f4, 0, 3
-;   ledbra %f0, %f7, 4
+;   ledbra %f0, %f6, 4
 ;   br %r14
 
 function %fcvt_from_uint_i16_f32(i16) -> f32 {
@@ -755,10 +755,10 @@ block0(v0: i16):
 }
 
 ; block0:
-;   llghr %r5, %r2
+;   llghr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdlgb %f7, %f5, 0, 3
+;   wcdlgb %f6, %f4, 0, 3
-;   ledbra %f0, %f7, 4
+;   ledbra %f0, %f6, 4
 ;   br %r14
 
 function %fcvt_from_sint_i16_f32(i16) -> f32 {
@@ -768,10 +768,10 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lghr %r5, %r2
+;   lghr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdgb %f7, %f5, 0, 3
+;   wcdgb %f6, %f4, 0, 3
-;   ledbra %f0, %f7, 4
+;   ledbra %f0, %f6, 4
 ;   br %r14
 
 function %fcvt_from_uint_i32_f32(i32) -> f32 {
@@ -781,10 +781,10 @@ block0(v0: i32):
 }
 
 ; block0:
-;   llgfr %r5, %r2
+;   llgfr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdlgb %f7, %f5, 0, 3
+;   wcdlgb %f6, %f4, 0, 3
-;   ledbra %f0, %f7, 4
+;   ledbra %f0, %f6, 4
 ;   br %r14
 
 function %fcvt_from_sint_i32_f32(i32) -> f32 {
@@ -794,10 +794,10 @@ block0(v0: i32):
 }
 
 ; block0:
-;   lgfr %r5, %r2
+;   lgfr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdgb %f7, %f5, 0, 3
+;   wcdgb %f6, %f4, 0, 3
-;   ledbra %f0, %f7, 4
+;   ledbra %f0, %f6, 4
 ;   br %r14
 
 function %fcvt_from_uint_i64_f32(i64) -> f32 {
@@ -807,9 +807,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldgr %f3, %r2
+;   ldgr %f2, %r2
-;   wcdlgb %f5, %f3, 0, 3
+;   wcdlgb %f4, %f2, 0, 3
-;   ledbra %f0, %f5, 4
+;   ledbra %f0, %f4, 4
 ;   br %r14
 
 function %fcvt_from_sint_i64_f32(i64) -> f32 {
@@ -819,9 +819,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldgr %f3, %r2
+;   ldgr %f2, %r2
-;   wcdgb %f5, %f3, 0, 3
+;   wcdgb %f4, %f2, 0, 3
-;   ledbra %f0, %f5, 4
+;   ledbra %f0, %f4, 4
 ;   br %r14
 
 function %fcvt_from_uint_i8_f64(i8) -> f64 {
@@ -831,9 +831,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   llgcr %r5, %r2
+;   llgcr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdlgb %f0, %f5, 0, 4
+;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i8_f64(i8) -> f64 {
@@ -843,9 +843,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   lgbr %r5, %r2
+;   lgbr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdgb %f0, %f5, 0, 4
+;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_uint_i16_f64(i16) -> f64 {
@@ -855,9 +855,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   llghr %r5, %r2
+;   llghr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdlgb %f0, %f5, 0, 4
+;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i16_f64(i16) -> f64 {
@@ -867,9 +867,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lghr %r5, %r2
+;   lghr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdgb %f0, %f5, 0, 4
+;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_uint_i32_f64(i32) -> f64 {
@@ -879,9 +879,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   llgfr %r5, %r2
+;   llgfr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdlgb %f0, %f5, 0, 4
+;   wcdlgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i32_f64(i32) -> f64 {
@@ -891,9 +891,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   lgfr %r5, %r2
+;   lgfr %r4, %r2
-;   ldgr %f5, %r5
+;   ldgr %f4, %r4
-;   wcdgb %f0, %f5, 0, 4
+;   wcdgb %f0, %f4, 0, 4
 ;   br %r14
 
 function %fcvt_from_uint_i64_f64(i64) -> f64 {
@@ -903,8 +903,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldgr %f3, %r2
+;   ldgr %f2, %r2
-;   wcdlgb %f0, %f3, 0, 4
+;   wcdlgb %f0, %f2, 0, 4
 ;   br %r14
 
 function %fcvt_from_sint_i64_f64(i64) -> f64 {
@@ -914,8 +914,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldgr %f3, %r2
+;   ldgr %f2, %r2
-;   wcdgb %f0, %f3, 0, 4
+;   wcdgb %f0, %f2, 0, 4
 ;   br %r14
 
 function %fcvt_to_uint_sat_f32_i8(f32) -> i8 {
@@ -925,9 +925,9 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ldebr %f3, %f0
+;   ldebr %f2, %f0
-;   wclgdb %f5, %f3, 0, 5
+;   wclgdb %f4, %f2, 0, 5
-;   lgdr %r2, %f5
+;   lgdr %r2, %f4
 ;   clgfi %r2, 256
 ;   locghih %r2, 255
 ;   br %r14
@@ -939,9 +939,9 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ldebr %f3, %f0
+;   ldebr %f2, %f0
-;   wcgdb %f5, %f3, 0, 5
+;   wcgdb %f4, %f2, 0, 5
-;   lgdr %r2, %f5
+;   lgdr %r2, %f4
 ;   cebr %f0, %f0
 ;   locghio %r2, 0
 ;   cghi %r2, 127
@@ -957,9 +957,9 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ldebr %f3, %f0
+;   ldebr %f2, %f0
-;   wclgdb %f5, %f3, 0, 5
+;   wclgdb %f4, %f2, 0, 5
-;   lgdr %r2, %f5
+;   lgdr %r2, %f4
 ;   clgfi %r2, 65535
 ;   locghih %r2, -1
 ;   br %r14
@@ -971,9 +971,9 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ldebr %f3, %f0
+;   ldebr %f2, %f0
-;   wcgdb %f5, %f3, 0, 5
+;   wcgdb %f4, %f2, 0, 5
-;   lgdr %r2, %f5
+;   lgdr %r2, %f4
 ;   cebr %f0, %f0
 ;   locghio %r2, 0
 ;   cghi %r2, 32767
@@ -989,9 +989,9 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ldebr %f3, %f0
+;   ldebr %f2, %f0
-;   wclgdb %f5, %f3, 0, 5
+;   wclgdb %f4, %f2, 0, 5
-;   lgdr %r2, %f5
+;   lgdr %r2, %f4
 ;   llilf %r3, 4294967295
 ;   clgr %r2, %r3
 ;   locgrh %r2, %r3
@@ -1004,14 +1004,14 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ldebr %f3, %f0
+;   ldebr %f2, %f0
-;   wcgdb %f5, %f3, 0, 5
+;   wcgdb %f4, %f2, 0, 5
-;   lgdr %r2, %f5
+;   lgdr %r2, %f4
 ;   cebr %f0, %f0
 ;   locghio %r2, 0
-;   lgfi %r3, 2147483647
+;   lgfi %r5, 2147483647
-;   cgr %r2, %r3
+;   cgr %r2, %r5
-;   locgrh %r2, %r3
+;   locgrh %r2, %r5
 ;   lgfi %r3, -2147483648
 ;   cgr %r2, %r3
 ;   locgrl %r2, %r3
@@ -1024,9 +1024,9 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ldebr %f3, %f0
+;   ldebr %f2, %f0
-;   wclgdb %f5, %f3, 0, 5
+;   wclgdb %f4, %f2, 0, 5
-;   lgdr %r2, %f5
+;   lgdr %r2, %f4
 ;   br %r14
 
 function %fcvt_to_sint_sat_f32_i64(f32) -> i64 {
@@ -1036,9 +1036,9 @@ block0(v0: f32):
 }
 
 ; block0:
-;   ldebr %f3, %f0
+;   ldebr %f2, %f0
-;   wcgdb %f5, %f3, 0, 5
+;   wcgdb %f4, %f2, 0, 5
-;   lgdr %r2, %f5
+;   lgdr %r2, %f4
 ;   cebr %f0, %f0
 ;   locghio %r2, 0
 ;   br %r14
@@ -1050,8 +1050,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wclgdb %f3, %f0, 0, 5
+;   wclgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   clgfi %r2, 256
 ;   locghih %r2, 255
 ;   br %r14
@@ -1063,8 +1063,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wcgdb %f3, %f0, 0, 5
+;   wcgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   cdbr %f0, %f0
 ;   locghio %r2, 0
 ;   cghi %r2, 127
@@ -1080,8 +1080,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wclgdb %f3, %f0, 0, 5
+;   wclgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   clgfi %r2, 65535
 ;   locghih %r2, -1
 ;   br %r14
@@ -1093,8 +1093,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wcgdb %f3, %f0, 0, 5
+;   wcgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   cdbr %f0, %f0
 ;   locghio %r2, 0
 ;   cghi %r2, 32767
@@ -1110,11 +1110,11 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wclgdb %f3, %f0, 0, 5
+;   wclgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
-;   llilf %r5, 4294967295
+;   llilf %r4, 4294967295
-;   clgr %r2, %r5
+;   clgr %r2, %r4
-;   locgrh %r2, %r5
+;   locgrh %r2, %r4
 ;   br %r14
 
 function %fcvt_to_sint_sat_f64_i32(f64) -> i32 {
@@ -1124,16 +1124,16 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wcgdb %f3, %f0, 0, 5
+;   wcgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   cdbr %f0, %f0
 ;   locghio %r2, 0
-;   lgfi %r4, 2147483647
+;   lgfi %r3, 2147483647
+;   cgr %r2, %r3
+;   locgrh %r2, %r3
+;   lgfi %r4, -2147483648
 ;   cgr %r2, %r4
-;   locgrh %r2, %r4
+;   locgrl %r2, %r4
-;   lgfi %r5, -2147483648
-;   cgr %r2, %r5
-;   locgrl %r2, %r5
 ;   br %r14
 
 function %fcvt_to_uint_sat_f64_i64(f64) -> i64 {
@@ -1143,8 +1143,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wclgdb %f3, %f0, 0, 5
+;   wclgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   br %r14
 
 function %fcvt_to_sint_sat_f64_i64(f64) -> i64 {
@@ -1154,8 +1154,8 @@ block0(v0: f64):
 }
 
 ; block0:
-;   wcgdb %f3, %f0, 0, 5
+;   wcgdb %f2, %f0, 0, 5
-;   lgdr %r2, %f3
+;   lgdr %r2, %f2
 ;   cdbr %f0, %f0
 ;   locghio %r2, 0
 ;   br %r14

cranelift/filetests/filetests/isa/s390x/fpmem.clif

@@ -28,8 +28,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   lrvg %r5, 0(%r2)
+;   lrvg %r4, 0(%r2)
-;   ldgr %f0, %r5
+;   ldgr %f0, %r4
 ;   br %r14
 
 function %load_f32_little(i64) -> f32 {
@@ -39,8 +39,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   lrv %r5, 0(%r2)
+;   lrv %r4, 0(%r2)
-;   vlvgf %v0, %r5, 0
+;   vlvgf %v0, %r4, 0
 ;   br %r14
 
 function %store_f64(f64, i64) {

cranelift/filetests/filetests/isa/s390x/heap_addr.clif

@@ -12,16 +12,17 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   llgfr %r3, %r3
+;   llgfr %r5, %r3
-;   lg %r4, 0(%r2)
+;   lgr %r4, %r2
-;   aghi %r4, 0
+;   lg %r2, 0(%r4)
-;   clgr %r3, %r4
+;   aghik %r3, %r2, 0
+;   clgr %r5, %r3
 ;   jgnh label1 ; jg label2
 ; block1:
-;   agr %r2, %r3
+;   agrk %r2, %r4, %r5
-;   lghi %r5, 0
+;   lghi %r4, 0
-;   clgr %r3, %r4
+;   clgr %r5, %r3
-;   locgrh %r2, %r5
+;   locgrh %r2, %r4
 ;   br %r14
 ; block2:
 ;   trap
@@ -36,14 +37,14 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   llgfr %r5, %r3
+;   llgfr %r4, %r3
-;   clgfi %r5, 65536
+;   clgfi %r4, 65536
 ;   jgnh label1 ; jg label2
 ; block1:
-;   agr %r2, %r5
+;   agr %r2, %r4
-;   lghi %r3, 0
+;   lghi %r5, 0
-;   clgfi %r5, 65536
+;   clgfi %r4, 65536
-;   locgrh %r2, %r3
+;   locgrh %r2, %r5
 ;   br %r14
 ; block2:
 ;   trap