T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Files
b077854b57b3aa25295e37ad55a21300e7768c7c
wasmtime/cranelift/filetests/filetests/isa/riscv64/stack.clif
Trevor Elliott b077854b57 Generate SSA code from returns (#5172) 
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
2022-11-08 16:00:49 -08:00

631 lines
11 KiB
Plaintext
Raw Blame History

test compile precise-output
set unwind_info=false
target riscv64
function %stack_addr_small() -> i64 {
ss0 = explicit_slot 8
block0:
v0 = stack_addr.i64 ss0
return v0
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; add sp,-16
; block0:
; load_addr a0,nsp+0
; add sp,+16
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %stack_addr_big() -> i64 {
ss0 = explicit_slot 100000
ss1 = explicit_slot 8
block0:
v0 = stack_addr.i64 ss0
return v0
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; lui a0,24
; addi a0,a0,1712
; call %Probestack
; add sp,-100016
; block0:
; load_addr a0,nsp+0
; add sp,+100016
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %stack_load_small() -> i64 {
ss0 = explicit_slot 8
block0:
v0 = stack_load.i64 ss0
return v0
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; add sp,-16
; block0:
; load_addr t1,nsp+0
; ld a0,0(t1)
; add sp,+16
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %stack_load_big() -> i64 {
ss0 = explicit_slot 100000
ss1 = explicit_slot 8
block0:
v0 = stack_load.i64 ss0
return v0
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; lui a0,24
; addi a0,a0,1712
; call %Probestack
; add sp,-100016
; block0:
; load_addr t1,nsp+0
; ld a0,0(t1)
; add sp,+100016
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %stack_store_small(i64) {
ss0 = explicit_slot 8
block0(v0: i64):
stack_store.i64 v0, ss0
return
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; add sp,-16
; block0:
; load_addr t2,nsp+0
; sd a0,0(t2)
; add sp,+16
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %stack_store_big(i64) {
ss0 = explicit_slot 100000
ss1 = explicit_slot 8
block0(v0: i64):
stack_store.i64 v0, ss0
return
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; lui a0,24
; addi a0,a0,1712
; call %Probestack
; add sp,-100016
; block0:
; load_addr t2,nsp+0
; sd a0,0(t2)
; add sp,+100016
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %i8_spill_slot(i8) -> i8, i64 {
ss0 = explicit_slot 1000
block0(v0: i8):
v1 = iconst.i64 1
v2 = iconst.i64 2
v3 = iconst.i64 3
v4 = iconst.i64 4
v5 = iconst.i64 5
v6 = iconst.i64 6
v7 = iconst.i64 7
v8 = iconst.i64 8
v9 = iconst.i64 9
v10 = iconst.i64 10
v11 = iconst.i64 11
v12 = iconst.i64 12
v13 = iconst.i64 13
v14 = iconst.i64 14
v15 = iconst.i64 15
v16 = iconst.i64 16
v17 = iconst.i64 17
v18 = iconst.i64 18
v19 = iconst.i64 19
v20 = iconst.i64 20
v21 = iconst.i64 21
v22 = iconst.i64 22
v23 = iconst.i64 23
v24 = iconst.i64 24
v25 = iconst.i64 25
v26 = iconst.i64 26
v27 = iconst.i64 27
v28 = iconst.i64 28
v29 = iconst.i64 29
v30 = iconst.i64 30
v31 = iconst.i64 31
v32 = iconst.i64 32
v33 = iconst.i64 33
v34 = iconst.i64 34
v35 = iconst.i64 35
v36 = iconst.i64 36
v37 = iconst.i64 37
v38 = iconst.i64 38
v39 = iconst.i64 39
v40 = iconst.i64 30
v41 = iconst.i64 31
v42 = iconst.i64 32
v43 = iconst.i64 33
v44 = iconst.i64 34
v45 = iconst.i64 35
v46 = iconst.i64 36
v47 = iconst.i64 37
v48 = iconst.i64 38
v49 = iconst.i64 39
v50 = iconst.i64 30
v51 = iconst.i64 31
v52 = iconst.i64 32
v53 = iconst.i64 33
v54 = iconst.i64 34
v55 = iconst.i64 35
v56 = iconst.i64 36
v57 = iconst.i64 37
v58 = iconst.i64 38
v59 = iconst.i64 39
v60 = iconst.i64 30
v61 = iconst.i64 31
v62 = iconst.i64 32
v63 = iconst.i64 33
v64 = iconst.i64 34
v65 = iconst.i64 35
v66 = iconst.i64 36
v67 = iconst.i64 37
v68 = iconst.i64 38
v69 = iconst.i64 39
v70 = iadd.i64 v1, v2
v71 = iadd.i64 v3, v4
v72 = iadd.i64 v5, v6
v73 = iadd.i64 v7, v8
v74 = iadd.i64 v9, v10
v75 = iadd.i64 v11, v12
v76 = iadd.i64 v13, v14
v77 = iadd.i64 v15, v16
v78 = iadd.i64 v17, v18
v79 = iadd.i64 v19, v20
v80 = iadd.i64 v21, v22
v81 = iadd.i64 v23, v24
v82 = iadd.i64 v25, v26
v83 = iadd.i64 v27, v28
v84 = iadd.i64 v29, v30
v85 = iadd.i64 v31, v32
v86 = iadd.i64 v33, v34
v87 = iadd.i64 v35, v36
v88 = iadd.i64 v37, v38
v89 = iadd.i64 v39, v40
v90 = iadd.i64 v41, v42
v91 = iadd.i64 v43, v44
v92 = iadd.i64 v45, v46
v93 = iadd.i64 v47, v48
v94 = iadd.i64 v49, v50
v95 = iadd.i64 v51, v52
v96 = iadd.i64 v53, v54
v97 = iadd.i64 v55, v56
v98 = iadd.i64 v57, v58
v99 = iadd.i64 v59, v60
v100 = iadd.i64 v61, v62
v101 = iadd.i64 v63, v64
v102 = iadd.i64 v65, v66
v103 = iadd.i64 v67, v68
v104 = iadd.i64 v69, v70
v105 = iadd.i64 v71, v72
v106 = iadd.i64 v73, v74
v107 = iadd.i64 v75, v76
v108 = iadd.i64 v77, v78
v109 = iadd.i64 v79, v80
v110 = iadd.i64 v81, v82
v111 = iadd.i64 v83, v84
v112 = iadd.i64 v85, v86
v113 = iadd.i64 v87, v88
v114 = iadd.i64 v89, v90
v115 = iadd.i64 v91, v92
v116 = iadd.i64 v93, v94
v117 = iadd.i64 v95, v96
v118 = iadd.i64 v97, v98
v119 = iadd.i64 v99, v100
v120 = iadd.i64 v101, v102
v121 = iadd.i64 v103, v104
v122 = iadd.i64 v105, v106
v123 = iadd.i64 v107, v108
v124 = iadd.i64 v109, v110
v125 = iadd.i64 v111, v112
v126 = iadd.i64 v113, v114
v127 = iadd.i64 v115, v116
v128 = iadd.i64 v117, v118
v129 = iadd.i64 v119, v120
v130 = iadd.i64 v121, v122
v131 = iadd.i64 v123, v124
v132 = iadd.i64 v125, v126
v133 = iadd.i64 v127, v128
v134 = iadd.i64 v129, v130
v135 = iadd.i64 v131, v132
v136 = iadd.i64 v133, v134
v137 = iadd.i64 v135, v136
return v0, v137
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; sd s1,-8(sp)
; sd s2,-16(sp)
; sd s3,-24(sp)
; sd s4,-32(sp)
; sd s5,-40(sp)
; sd s6,-48(sp)
; sd s7,-56(sp)
; sd s8,-64(sp)
; sd s9,-72(sp)
; sd s10,-80(sp)
; sd s11,-88(sp)
; add sp,-1280
; block0:
; sd a0,1000(nominal_sp)
; li t3,2
; addi t1,t3,1
; sd t1,1176(nominal_sp)
; li t3,4
; addi t2,t3,3
; sd t2,1168(nominal_sp)
; li t3,6
; addi a1,t3,5
; sd a1,1160(nominal_sp)
; li t3,8
; addi a2,t3,7
; sd a2,1152(nominal_sp)
; li t3,10
; addi a3,t3,9
; sd a3,1144(nominal_sp)
; li t3,12
; addi a4,t3,11
; sd a4,1136(nominal_sp)
; li t3,14
; addi a5,t3,13
; sd a5,1128(nominal_sp)
; li t3,16
; addi a6,t3,15
; sd a6,1120(nominal_sp)
; li t3,18
; addi a7,t3,17
; sd a7,1112(nominal_sp)
; li t3,20
; addi t3,t3,19
; sd t3,1104(nominal_sp)
; li t3,22
; addi t4,t3,21
; sd t4,1096(nominal_sp)
; li t3,24
; addi s6,t3,23
; sd s6,1088(nominal_sp)
; li t3,26
; addi s7,t3,25
; sd s7,1080(nominal_sp)
; li t3,28
; addi s8,t3,27
; sd s8,1072(nominal_sp)
; li t3,30
; addi s9,t3,29
; sd s9,1064(nominal_sp)
; li t3,32
; addi s10,t3,31
; sd s10,1056(nominal_sp)
; li t3,34
; addi s11,t3,33
; sd s11,1048(nominal_sp)
; li t3,36
; addi s1,t3,35
; sd s1,1040(nominal_sp)
; li t3,38
; addi s2,t3,37
; sd s2,1032(nominal_sp)
; li t3,30
; addi s3,t3,39
; sd s3,1024(nominal_sp)
; li t3,32
; addi s4,t3,31
; sd s4,1016(nominal_sp)
; li t3,34
; addi s5,t3,33
; sd s5,1008(nominal_sp)
; li t3,36
; addi s5,t3,35
; li t3,38
; addi a0,t3,37
; li t3,30
; addi t0,t3,39
; li t3,32
; addi t1,t3,31
; li t3,34
; addi t2,t3,33
; li t3,36
; addi a1,t3,35
; li t3,38
; addi a2,t3,37
; li t3,30
; addi a3,t3,39
; li t3,32
; addi a4,t3,31
; li t3,34
; addi a5,t3,33
; li t3,36
; addi a6,t3,35
; li t3,38
; addi a7,t3,37
; ld t3,1176(nominal_sp)
; addi t3,t3,39
; ld t4,1160(nominal_sp)
; ld s2,1168(nominal_sp)
; add t4,s2,t4
; ld s9,1144(nominal_sp)
; ld s7,1152(nominal_sp)
; add s6,s7,s9
; ld s3,1128(nominal_sp)
; ld s1,1136(nominal_sp)
; add s7,s1,s3
; ld s8,1112(nominal_sp)
; ld s9,1120(nominal_sp)
; add s8,s9,s8
; ld s2,1096(nominal_sp)
; ld s11,1104(nominal_sp)
; add s9,s11,s2
; ld s10,1080(nominal_sp)
; ld s11,1088(nominal_sp)
; add s10,s11,s10
; ld s1,1064(nominal_sp)
; ld s11,1072(nominal_sp)
; add s11,s11,s1
; ld s1,1048(nominal_sp)
; ld s4,1056(nominal_sp)
; add s1,s4,s1
; ld s2,1032(nominal_sp)
; ld s3,1040(nominal_sp)
; add s2,s3,s2
; ld s4,1016(nominal_sp)
; ld s3,1024(nominal_sp)
; add s3,s3,s4
; ld s4,1008(nominal_sp)
; add s5,s4,s5
; add t0,a0,t0
; add t1,t1,t2
; add t2,a1,a2
; add a0,a3,a4
; add a1,a5,a6
; add a2,a7,t3
; add t4,t4,s6
; add a3,s7,s8
; add a4,s9,s10
; add a5,s11,s1
; add a6,s2,s3
; add t0,s5,t0
; add t1,t1,t2
; add t2,a0,a1
; add t4,a2,t4
; add a0,a3,a4
; add a1,a5,a6
; add t0,t0,t1
; add t4,t2,t4
; add t1,a0,a1
; add t4,t0,t4
; add a1,t1,t4
; ld a0,1000(nominal_sp)
; add sp,+1280
; ld s1,-8(sp)
; ld s2,-16(sp)
; ld s3,-24(sp)
; ld s4,-32(sp)
; ld s5,-40(sp)
; ld s6,-48(sp)
; ld s7,-56(sp)
; ld s8,-64(sp)
; ld s9,-72(sp)
; ld s10,-80(sp)
; ld s11,-88(sp)
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %i128_stack_store(i128) {
ss0 = explicit_slot 16
block0(v0: i128):
stack_store.i128 v0, ss0
return
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; add sp,-16
; block0:
; mv a2,a0
; load_addr a0,nsp+0
; sd a2,0(a0)
; sd a1,8(a0)
; add sp,+16
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %i128_stack_store_inst_offset(i128) {
ss0 = explicit_slot 16
ss1 = explicit_slot 16
block0(v0: i128):
stack_store.i128 v0, ss1+16
return
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; add sp,-32
; block0:
; mv a2,a0
; load_addr a0,nsp+32
; sd a2,0(a0)
; sd a1,8(a0)
; add sp,+32
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %i128_stack_store_big(i128) {
ss0 = explicit_slot 100000
ss1 = explicit_slot 8
block0(v0: i128):
stack_store.i128 v0, ss0
return
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; lui a0,24
; addi a0,a0,1712
; call %Probestack
; add sp,-100016
; block0:
; mv a2,a0
; load_addr a0,nsp+0
; sd a2,0(a0)
; sd a1,8(a0)
; add sp,+100016
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %i128_stack_load() -> i128 {
ss0 = explicit_slot 16
block0:
v0 = stack_load.i128 ss0
return v0
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; add sp,-16
; block0:
; load_addr t2,nsp+0
; ld a0,0(t2)
; ld a1,8(t2)
; add sp,+16
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %i128_stack_load_inst_offset() -> i128 {
ss0 = explicit_slot 16
ss1 = explicit_slot 16
block0:
v0 = stack_load.i128 ss1+16
return v0
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; add sp,-32
; block0:
; load_addr t2,nsp+32
; ld a0,0(t2)
; ld a1,8(t2)
; add sp,+32
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
function %i128_stack_load_big() -> i128 {
ss0 = explicit_slot 100000
ss1 = explicit_slot 8
block0:
v0 = stack_load.i128 ss0
return v0
}
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; lui a0,24
; addi a0,a0,1712
; call %Probestack
; add sp,-100016
; block0:
; load_addr t2,nsp+0
; ld a0,0(t2)
; ld a1,8(t2)
; add sp,+100016
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
Reference in New Issue View Git Blame Copy Permalink