Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
418 lines
6.4 KiB
Plaintext
418 lines
6.4 KiB
Plaintext
test compile precise-output
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set avoid_div_traps=1
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target s390x
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; SDIV
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %sdiv_i64(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = sdiv.i64 v0, v1
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return v2
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}
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; block0:
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; cgite %r3, 0
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; llihf %r4, 2147483647
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; iilf %r4, 4294967295
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; xgr %r4, %r2
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; lgr %r5, %r2
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; ngr %r4, %r3
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; lgr %r2, %r3
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; cgite %r4, -1
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; lgr %r4, %r2
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; lgr %r3, %r5
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; dsgr %r2, %r4
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; lgr %r2, %r3
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; br %r14
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function %sdiv_i64_imm(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 2
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v2 = sdiv.i64 v0, v1
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return v2
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}
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; block0:
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; lgr %r3, %r2
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; lghi %r4, 2
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; dsgr %r2, %r4
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; lgr %r2, %r3
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; br %r14
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function %sdiv_i32(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = sdiv.i32 v0, v1
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return v2
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}
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; stmg %r7, %r15, 56(%r15)
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; block0:
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; lgfr %r5, %r2
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; lgr %r7, %r5
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; cite %r3, 0
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; iilf %r5, 2147483647
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; lgr %r4, %r7
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; xrk %r2, %r5, %r4
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; nrk %r4, %r2, %r3
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; lgr %r5, %r3
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; cite %r4, -1
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; lgr %r3, %r7
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; dsgfr %r2, %r5
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; lgr %r2, %r3
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; lmg %r7, %r15, 56(%r15)
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; br %r14
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function %sdiv_i32_imm(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = sdiv.i32 v0, v1
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return v2
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}
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; block0:
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; lgfr %r3, %r2
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; lhi %r2, 2
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; dsgfr %r2, %r2
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; lgr %r2, %r3
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; br %r14
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function %sdiv_i16(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = sdiv.i16 v0, v1
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return v2
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}
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; block0:
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; lghr %r5, %r2
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; lhr %r4, %r3
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; cite %r4, 0
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; lhi %r2, 32767
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; lgr %r3, %r5
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; xrk %r5, %r2, %r3
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; nrk %r2, %r5, %r4
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; cite %r2, -1
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; dsgfr %r2, %r4
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; lgr %r2, %r3
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; br %r14
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function %sdiv_i16_imm(i16) -> i16 {
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block0(v0: i16):
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v1 = iconst.i16 2
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v2 = sdiv.i16 v0, v1
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return v2
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}
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; block0:
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; lghr %r3, %r2
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; lhi %r2, 2
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; dsgfr %r2, %r2
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; lgr %r2, %r3
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; br %r14
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function %sdiv_i8(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = sdiv.i8 v0, v1
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return v2
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}
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; block0:
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; lgbr %r5, %r2
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; lbr %r4, %r3
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; cite %r4, 0
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; lhi %r2, 127
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; lgr %r3, %r5
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; xrk %r5, %r2, %r3
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; nrk %r2, %r5, %r4
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; cite %r2, -1
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; dsgfr %r2, %r4
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; lgr %r2, %r3
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; br %r14
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function %sdiv_i8_imm(i8) -> i8 {
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block0(v0: i8):
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v1 = iconst.i8 2
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v2 = sdiv.i8 v0, v1
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return v2
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}
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; block0:
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; lgbr %r3, %r2
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; lhi %r2, 2
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; dsgfr %r2, %r2
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; lgr %r2, %r3
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; br %r14
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function %udiv_i64(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = udiv.i64 v0, v1
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return v2
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}
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; block0:
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; lgr %r5, %r2
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; lghi %r2, 0
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; cgite %r3, 0
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; lgr %r4, %r3
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; lgr %r3, %r5
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; lgr %r5, %r4
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; dlgr %r2, %r5
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; lgr %r2, %r3
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; br %r14
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function %udiv_i64_imm(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 2
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v2 = udiv.i64 v0, v1
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return v2
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}
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; block0:
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; lgr %r3, %r2
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; lghi %r2, 0
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; lghi %r4, 2
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; dlgr %r2, %r4
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; lgr %r2, %r3
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; br %r14
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function %udiv_i32(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = udiv.i32 v0, v1
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return v2
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}
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; block0:
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; lgr %r5, %r2
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; lhi %r2, 0
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; cite %r3, 0
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; lgr %r4, %r3
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; lgr %r3, %r5
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; lgr %r5, %r4
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; dlr %r2, %r5
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; lgr %r2, %r3
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; br %r14
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function %udiv_i32_imm(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = udiv.i32 v0, v1
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return v2
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}
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; block0:
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; lgr %r3, %r2
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; lhi %r2, 0
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; lhi %r4, 2
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; dlr %r2, %r4
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; lgr %r2, %r3
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; br %r14
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function %udiv_i16(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = udiv.i16 v0, v1
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return v2
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}
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; stmg %r8, %r15, 64(%r15)
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; block0:
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; lgr %r4, %r3
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; lhi %r5, 0
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; lgr %r8, %r5
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; llhr %r3, %r2
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; lgr %r5, %r4
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; llhr %r5, %r5
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; cite %r5, 0
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; lgr %r2, %r8
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; dlr %r2, %r5
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; lgr %r2, %r3
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; lmg %r8, %r15, 64(%r15)
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; br %r14
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function %udiv_i16_imm(i16) -> i16 {
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block0(v0: i16):
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v1 = iconst.i16 2
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v2 = udiv.i16 v0, v1
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return v2
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}
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; block0:
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; lhi %r4, 0
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; lgr %r5, %r4
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; llhr %r3, %r2
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; lhi %r4, 2
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; lgr %r2, %r5
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; dlr %r2, %r4
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; lgr %r2, %r3
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; br %r14
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function %udiv_i8(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = udiv.i8 v0, v1
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return v2
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}
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; stmg %r8, %r15, 64(%r15)
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; block0:
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; lgr %r4, %r3
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; lhi %r5, 0
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; lgr %r8, %r5
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; llcr %r3, %r2
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; lgr %r5, %r4
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; llcr %r5, %r5
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; cite %r5, 0
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; lgr %r2, %r8
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; dlr %r2, %r5
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; lgr %r2, %r3
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; lmg %r8, %r15, 64(%r15)
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; br %r14
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function %udiv_i8_imm(i8) -> i8 {
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block0(v0: i8):
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v1 = iconst.i8 2
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v2 = udiv.i8 v0, v1
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return v2
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}
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; block0:
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; lhi %r4, 0
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; lgr %r5, %r4
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; llcr %r3, %r2
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; lhi %r4, 2
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; lgr %r2, %r5
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; dlr %r2, %r4
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; lgr %r2, %r3
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; br %r14
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function %srem_i64(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = srem.i64 v0, v1
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return v2
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}
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; block0:
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; cgite %r3, 0
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; cghi %r3, -1
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; lgr %r4, %r3
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; lgr %r3, %r2
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; locghie %r3, 0
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; dsgr %r2, %r4
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; br %r14
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function %srem_i32(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = srem.i32 v0, v1
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return v2
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}
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; block0:
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; lgr %r5, %r3
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; lgfr %r3, %r2
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; lgr %r2, %r5
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; cite %r2, 0
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; dsgfr %r2, %r2
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; br %r14
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function %srem_i16(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = srem.i16 v0, v1
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return v2
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}
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; block0:
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; lghr %r5, %r2
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; lgr %r2, %r5
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; lhr %r4, %r3
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; cite %r4, 0
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; lgr %r3, %r2
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; dsgfr %r2, %r4
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; br %r14
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function %srem_i8(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = srem.i8 v0, v1
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return v2
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}
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; block0:
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; lgbr %r5, %r2
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; lgr %r2, %r5
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; lbr %r4, %r3
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; cite %r4, 0
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; lgr %r3, %r2
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; dsgfr %r2, %r4
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; br %r14
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function %urem_i64(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = urem.i64 v0, v1
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return v2
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}
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; block0:
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; lgr %r5, %r2
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; lghi %r2, 0
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; cgite %r3, 0
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; lgr %r4, %r3
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; lgr %r3, %r5
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; lgr %r5, %r4
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; dlgr %r2, %r5
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; br %r14
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function %urem_i32(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = urem.i32 v0, v1
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return v2
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}
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; block0:
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; lgr %r5, %r2
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; lhi %r2, 0
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; cite %r3, 0
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; lgr %r4, %r3
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; lgr %r3, %r5
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; lgr %r5, %r4
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; dlr %r2, %r5
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; br %r14
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function %urem_i16(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = urem.i16 v0, v1
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return v2
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}
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; stmg %r8, %r15, 64(%r15)
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; block0:
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; lgr %r4, %r3
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; lhi %r5, 0
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; lgr %r8, %r5
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; llhr %r3, %r2
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; lgr %r5, %r4
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; llhr %r5, %r5
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; cite %r5, 0
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; lgr %r2, %r8
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; dlr %r2, %r5
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; lmg %r8, %r15, 64(%r15)
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; br %r14
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function %urem_i8(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = urem.i8 v0, v1
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return v2
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}
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; stmg %r8, %r15, 64(%r15)
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; block0:
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; lgr %r4, %r3
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; lhi %r5, 0
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; lgr %r8, %r5
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; llcr %r3, %r2
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; lgr %r5, %r4
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; llcr %r5, %r5
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; cite %r5, 0
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; lgr %r2, %r8
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; dlr %r2, %r5
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; lmg %r8, %r15, 64(%r15)
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; br %r14
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