b077854b57
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
426 lines
6.3 KiB
Plaintext
426 lines
6.3 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target riscv64
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function %f1(i64) -> i64 {
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fn0 = %g(i64) -> i64
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block0(v0: i64):
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v1 = call fn0(v0)
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return v1
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; load_sym a1,%g+0
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; callind a1
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f2(i32) -> i64 {
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fn0 = %g(i32 uext) -> i64
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; uext.w a0,a0
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; load_sym a2,%g+0
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; callind a2
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f3(i32) -> i32 uext {
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block0(v0: i32):
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return v0
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}
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; block0:
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; uext.w a0,a0
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; ret
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function %f4(i32) -> i64 {
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fn0 = %g(i32 sext) -> i64
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; sext.w a0,a0
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; load_sym a2,%g+0
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; callind a2
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f5(i32) -> i32 sext {
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block0(v0: i32):
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return v0
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}
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; block0:
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; sext.w a0,a0
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; ret
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function %f6(i8) -> i64 {
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fn0 = %g(i32, i32, i32, i32, i32, i32, i32, i32, i8 sext) -> i64
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block0(v0: i8):
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v1 = iconst.i32 42
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v2 = call fn0(v1, v1, v1, v1, v1, v1, v1, v1, v0)
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return v2
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; mv t3,a0
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; add sp,-16
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; virtual_sp_offset_adj +16
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; li a0,42
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; li a1,42
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; li a2,42
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; li a3,42
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; li a4,42
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; li a5,42
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; li a6,42
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; li a7,42
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; sext.b t3,t3
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; sd t3,0(sp)
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; load_sym t3,%g+0
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; callind t3
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; add sp,+16
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; virtual_sp_offset_adj -16
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f7(i8) -> i32, i32, i32, i32, i32, i32, i32, i32, i8 sext {
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block0(v0: i8):
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v1 = iconst.i32 42
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return v1, v1, v1, v1, v1, v1, v1, v1, v0
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}
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; block0:
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; li a2,42
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; mv t1,a2
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; li a2,42
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; mv a3,a2
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; li a4,42
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; li a6,42
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; li t3,42
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; li t0,42
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; li t2,42
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; li a2,42
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; sw a4,0(a1)
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; sw a6,8(a1)
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; sw t3,16(a1)
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; sw t0,24(a1)
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; sw t2,32(a1)
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; sw a2,40(a1)
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; sext.b t4,a0
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; sd a0,48(a1)
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; mv a0,t1
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; mv a1,a3
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; ret
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function %f8() {
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fn0 = %g0() -> f32
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fn1 = %g1() -> f64
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fn2 = %g2()
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fn3 = %g3(f32)
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fn4 = %g4(f64)
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block0:
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v0 = call fn0()
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v1 = call fn1()
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v2 = call fn1()
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call fn2()
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call fn3(v0)
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call fn4(v1)
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call fn4(v2)
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return
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; fsd fs2,-8(sp)
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; fsd fs3,-16(sp)
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; fsd fs11,-24(sp)
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; add sp,-32
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; block0:
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; load_sym a6,%g0+0
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; callind a6
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; fmv.d fs11,fa0
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; load_sym a6,%g1+0
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; callind a6
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; fmv.d fs2,fa0
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; load_sym a6,%g1+0
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; callind a6
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; fmv.d fs3,fa0
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; load_sym a6,%g2+0
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; callind a6
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; load_sym a7,%g3+0
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; fmv.d fa0,fs11
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; callind a7
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; load_sym t3,%g4+0
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; fmv.d fa0,fs2
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; callind t3
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; load_sym t4,%g4+0
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; fmv.d fa0,fs3
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; callind t4
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; add sp,+32
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; fld fs2,-8(sp)
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; fld fs3,-16(sp)
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; fld fs11,-24(sp)
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f11(i128, i64) -> i64 {
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block0(v0: i128, v1: i64):
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v2, v3 = isplit v0
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return v3
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}
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; block0:
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; mv a0,a1
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; ret
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function %f11_call(i64) -> i64 {
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fn0 = %f11(i128, i64) -> i64
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block0(v0: i64):
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v1 = iconst.i64 42
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v2 = iconcat v1, v0
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v3 = call fn0(v2, v1)
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return v3
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; mv a5,a0
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; li a0,42
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; mv a1,a5
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; li a2,42
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; load_sym a5,%f11+0
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; callind a5
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f12(i64, i128) -> i64 {
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block0(v0: i64, v1: i128):
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v2, v3 = isplit v1
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return v2
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}
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; block0:
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; mv a0,a1
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; mv a1,a2
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; ret
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function %f12_call(i64) -> i64 {
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fn0 = %f12(i64, i128) -> i64
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block0(v0: i64):
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v1 = iconst.i64 42
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v2 = iconcat v0, v1
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v3 = call fn0(v1, v2)
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return v3
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; mv a1,a0
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; li a2,42
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; li a0,42
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; load_sym a5,%f12+0
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; callind a5
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f13(i64, i128) -> i64 {
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block0(v0: i64, v1: i128):
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v2, v3 = isplit v1
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return v2
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}
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; block0:
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; mv a0,a1
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; mv a1,a2
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; ret
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function %f13_call(i64) -> i64 {
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fn0 = %f13(i64, i128) -> i64
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block0(v0: i64):
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v1 = iconst.i64 42
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v2 = iconcat v0, v1
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v3 = call fn0(v1, v2)
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return v3
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; mv a1,a0
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; li a2,42
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; li a0,42
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; load_sym a5,%f13+0
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; callind a5
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f14(i128, i128, i128, i64, i128) -> i128 {
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block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
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return v4
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; mv a0,a7
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; ld a1,16(fp)
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f14_call(i128, i64) -> i128 {
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fn0 = %f14(i128, i128, i128, i64, i128) -> i128
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block0(v0: i128, v1: i64):
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v2 = call fn0(v0, v0, v0, v1, v0)
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return v2
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; mv a7,a0
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; mv a6,a2
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; add sp,-16
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; virtual_sp_offset_adj +16
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; sd a1,0(sp)
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; mv a5,a1
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; load_sym t3,%f14+0
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; mv a1,a5
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; mv a3,a5
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; mv a0,a7
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; mv a2,a7
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; mv a4,a7
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; callind t3
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; add sp,+16
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; virtual_sp_offset_adj -16
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f15(i128, i128, i128, i64, i128) -> i128{
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block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
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return v4
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; mv a0,a7
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; ld a1,16(fp)
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f15_call(i128, i64) -> i128 {
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fn0 = %f15(i128, i128, i128, i64, i128) -> i128
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block0(v0: i128, v1: i64):
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v2 = call fn0(v0, v0, v0, v1, v0)
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return v2
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; block0:
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; mv a7,a0
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; mv a6,a2
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; add sp,-16
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; virtual_sp_offset_adj +16
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; sd a1,0(sp)
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; mv a5,a1
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; load_sym t3,%f15+0
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; mv a1,a5
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; mv a3,a5
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; mv a0,a7
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; mv a2,a7
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; mv a4,a7
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; callind t3
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; add sp,+16
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; virtual_sp_offset_adj -16
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %f16() -> i32, i32 {
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block0:
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v0 = iconst.i32 0
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v1 = iconst.i32 1
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return v0, v1
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}
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; block0:
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; li a0,0
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; li a1,1
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; ret
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