diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index cf50abe595..be6d2d978b 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -398,7 +398,7 @@ impl ABIMachineSpec for AArch64MachineDeps { Inst::Args { args } } - fn gen_ret(setup_frame: bool, isa_flags: &aarch64_settings::Flags, rets: Vec) -> Inst { + fn gen_ret(setup_frame: bool, isa_flags: &aarch64_settings::Flags, rets: Vec) -> Inst { if isa_flags.sign_return_address() && (setup_frame || isa_flags.sign_return_address_all()) { let key = if isa_flags.sign_return_address_with_bkey() { APIKey::B diff --git a/cranelift/codegen/src/isa/aarch64/inst.isle b/cranelift/codegen/src/isa/aarch64/inst.isle index e4bf8bbf05..5f439329e4 100644 --- a/cranelift/codegen/src/isa/aarch64/inst.isle +++ b/cranelift/codegen/src/isa/aarch64/inst.isle @@ -787,7 +787,7 @@ ;; A machine return instruction. (Ret - (rets VecReg)) + (rets VecRetPair)) ;; A machine return instruction with pointer authentication using SP as the ;; modifier. This instruction requires pointer authentication support @@ -797,7 +797,7 @@ (AuthenticatedRet (key APIKey) (is_hint bool) - (rets VecReg)) + (rets VecRetPair)) ;; An unconditional branch. (Jump diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index ab354166c3..dc52b84daf 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -1022,8 +1022,8 @@ fn aarch64_get_operands VReg>(inst: &Inst, collector: &mut Operan } } &Inst::Ret { ref rets } | &Inst::AuthenticatedRet { ref rets, .. } => { - for &ret in rets { - collector.reg_use(ret); + for ret in rets { + collector.reg_fixed_use(ret.vreg, ret.preg); } } &Inst::Jump { .. } => {} diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index bef16944f6..445dddfce3 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -265,12 +265,15 @@ mod test { let buffer = backend.compile_function(&mut func, false).unwrap().buffer; let code = buffer.data(); - // mov x3, #0x1234 - // add w0, w0, w3 - // ret - let golden = vec![ - 0x83, 0x46, 0x82, 0xd2, 0x00, 0x00, 0x03, 0x0b, 0xc0, 0x03, 0x5f, 0xd6, - ]; + // To update this comment, write the golden bytes to a file, and run the following command + // on it to update: + // > aarch64-linux-gnu-objdump -b binary -D -m aarch64 + // + // 0: d2824682 mov x2, #0x1234 // #4660 + // 4: 0b020000 add w0, w0, w2 + // 8: d65f03c0 ret + + let golden = vec![130, 70, 130, 210, 0, 0, 2, 11, 192, 3, 95, 214]; assert_eq!(code, &golden[..]); } @@ -320,24 +323,28 @@ mod test { .unwrap(); let code = result.buffer.data(); - // mov x10, #0x1234 // #4660 - // add w12, w0, w10 - // mov w11, w12 - // cbnz x11, 0x20 - // mov x13, #0x1234 // #4660 - // add w15, w12, w13 - // mov w14, w15 - // cbnz x14, 0x10 - // mov w1, w12 - // cbnz x1, 0x10 - // mov x2, #0x1234 // #4660 - // sub w0, w12, w2 - // ret + // To update this comment, write the golden bytes to a file, and run the following command + // on it to update: + // > aarch64-linux-gnu-objdump -b binary -D -m aarch64 + // + // 0: d2824689 mov x9, #0x1234 // #4660 + // 4: 0b09000b add w11, w0, w9 + // 8: 2a0b03ea mov w10, w11 + // c: b50000aa cbnz x10, 0x20 + // 10: d282468c mov x12, #0x1234 // #4660 + // 14: 0b0c016e add w14, w11, w12 + // 18: 2a0e03ed mov w13, w14 + // 1c: b5ffffad cbnz x13, 0x10 + // 20: 2a0b03e0 mov w0, w11 + // 24: b5ffff60 cbnz x0, 0x10 + // 28: d2824681 mov x1, #0x1234 // #4660 + // 2c: 4b010160 sub w0, w11, w1 + // 30: d65f03c0 ret let golden = vec![ - 138, 70, 130, 210, 12, 0, 10, 11, 235, 3, 12, 42, 171, 0, 0, 181, 141, 70, 130, 210, - 143, 1, 13, 11, 238, 3, 15, 42, 174, 255, 255, 181, 225, 3, 12, 42, 97, 255, 255, 181, - 130, 70, 130, 210, 128, 1, 2, 75, 192, 3, 95, 214, + 137, 70, 130, 210, 11, 0, 9, 11, 234, 3, 11, 42, 170, 0, 0, 181, 140, 70, 130, 210, + 110, 1, 12, 11, 237, 3, 14, 42, 173, 255, 255, 181, 224, 3, 11, 42, 96, 255, 255, 181, + 129, 70, 130, 210, 96, 1, 1, 75, 192, 3, 95, 214, ]; assert_eq!(code, &golden[..]); @@ -393,14 +400,18 @@ mod test { .unwrap(); let code = result.buffer.data(); + // To update this comment, write the golden bytes to a file, and run the following command + // on it to update: + // > aarch64-linux-gnu-objdump -b binary -D -m aarch64 + // // 0: 7100081f cmp w0, #0x2 // 4: 54000122 b.cs 0x28 // b.hs, b.nlast - // 8: 9a8023e9 csel x9, xzr, x0, cs // cs = hs, nlast + // 8: 9a8023e8 csel x8, xzr, x0, cs // cs = hs, nlast // c: d503229f csdb - // 10: 10000088 adr x8, 0x1c - // 14: b8a95909 ldrsw x9, [x8, w9, uxtw #2] - // 18: 8b090108 add x8, x8, x9 - // 1c: d61f0100 br x8 + // 10: 10000087 adr x7, 0x20 + // 14: b8a858e8 ldrsw x8, [x7, w8, uxtw #2] + // 18: 8b0800e7 add x7, x7, x8 + // 1c: d61f00e0 br x7 // 20: 00000010 udf #16 // 24: 00000018 udf #24 // 28: d2800060 mov x0, #0x3 // #3 @@ -411,9 +422,10 @@ mod test { // 3c: d65f03c0 ret let golden = vec![ - 31, 8, 0, 113, 34, 1, 0, 84, 233, 35, 128, 154, 159, 34, 3, 213, 136, 0, 0, 16, 9, 89, - 169, 184, 8, 1, 9, 139, 0, 1, 31, 214, 16, 0, 0, 0, 24, 0, 0, 0, 96, 0, 128, 210, 192, - 3, 95, 214, 32, 0, 128, 210, 192, 3, 95, 214, 64, 0, 128, 210, 192, 3, 95, 214, + 31, 8, 0, 113, 34, 1, 0, 84, 232, 35, 128, 154, 159, 34, 3, 213, 135, 0, 0, 16, 232, + 88, 168, 184, 231, 0, 8, 139, 224, 0, 31, 214, 16, 0, 0, 0, 24, 0, 0, 0, 96, 0, 128, + 210, 192, 3, 95, 214, 32, 0, 128, 210, 192, 3, 95, 214, 64, 0, 128, 210, 192, 3, 95, + 214, ]; assert_eq!(code, &golden[..]); diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs index 8e5446d4e9..7aeee8ba57 100644 --- a/cranelift/codegen/src/isa/riscv64/abi.rs +++ b/cranelift/codegen/src/isa/riscv64/abi.rs @@ -235,7 +235,7 @@ impl ABIMachineSpec for Riscv64MachineDeps { Inst::Args { args } } - fn gen_ret(_setup_frame: bool, _isa_flags: &Self::F, rets: Vec) -> Inst { + fn gen_ret(_setup_frame: bool, _isa_flags: &Self::F, rets: Vec) -> Inst { Inst::Ret { rets } } diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle index 88e7af4a84..62df94a605 100644 --- a/cranelift/codegen/src/isa/riscv64/inst.isle +++ b/cranelift/codegen/src/isa/riscv64/inst.isle @@ -71,7 +71,7 @@ (Args (args VecArgPair)) - (Ret (rets VecReg)) + (Ret (rets VecRetPair)) (Extend (rd WritableReg) diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 1221edd2d9..9cb7c8c50b 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -352,7 +352,9 @@ fn riscv64_get_operands VReg>(inst: &Inst, collector: &mut Operan } } &Inst::Ret { ref rets } => { - collector.reg_uses(&rets[..]); + for ret in rets { + collector.reg_fixed_use(ret.vreg, ret.preg); + } } &Inst::Extend { rd, rn, .. } => { diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index 603279c06f..ffff098611 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -233,13 +233,18 @@ mod test { ); let buffer = backend.compile_function(&mut func, true).unwrap(); let code = buffer.buffer.data(); - // 0: 000015b7 lui a1,0x1 - // 4: 23458593 addi a1,a1,564 # 0x1234 - // 8: 00b5053b addw a0,a0,a1 + + // To update this comment, write the golden bytes to a file, and run the following command + // on it to update: + // > riscv64-linux-gnu-objdump -b binary -D -m riscv + // + // 0: 000013b7 lui t2,0x1 + // 4: 23438393 addi t2,t2,564 # 0x1234 + // 8: 0075053b .4byte 0x75053b // c: 00008067 ret + let golden = vec![ - 0xb7, 0x15, 0x0, 0x0, 0x93, 0x85, 0x45, 0x23, 0x3b, 0x5, 0xb5, 0x0, 0x67, 0x80, 0x0, - 0x0, + 183, 19, 0, 0, 147, 131, 67, 35, 59, 5, 117, 0, 103, 128, 0, 0, ]; assert_eq!(code, &golden[..]); } diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 2422536046..45e051f021 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -457,7 +457,7 @@ impl ABIMachineSpec for S390xMachineDeps { Inst::Args { args } } - fn gen_ret(_setup_frame: bool, _isa_flags: &s390x_settings::Flags, rets: Vec) -> Inst { + fn gen_ret(_setup_frame: bool, _isa_flags: &s390x_settings::Flags, rets: Vec) -> Inst { Inst::Ret { link: gpr(14), rets, diff --git a/cranelift/codegen/src/isa/s390x/inst.isle b/cranelift/codegen/src/isa/s390x/inst.isle index 5261138ba2..db76ff60ab 100644 --- a/cranelift/codegen/src/isa/s390x/inst.isle +++ b/cranelift/codegen/src/isa/s390x/inst.isle @@ -906,7 +906,7 @@ ;; A machine return instruction. (Ret (link Reg) - (rets VecReg)) + (rets VecRetPair)) ;; An unconditional branch. (Jump diff --git a/cranelift/codegen/src/isa/s390x/inst/emit.rs b/cranelift/codegen/src/isa/s390x/inst/emit.rs index 94739c4907..f0cd7b879d 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit.rs @@ -3480,7 +3480,7 @@ impl Inst { } &Inst::Call { link, ref info } => { - let link = allocs.next_writable(link); + debug_assert_eq!(link.to_reg(), gpr(14)); // Add relocation for TLS libcalls to enable linker optimizations. match &info.tls_symbol { @@ -3509,7 +3509,7 @@ impl Inst { } } &Inst::CallInd { link, ref info } => { - let link = allocs.next_writable(link); + debug_assert_eq!(link.to_reg(), gpr(14)); let rn = allocs.next(info.rn); let opcode = 0x0d; // BASR @@ -3523,7 +3523,7 @@ impl Inst { } &Inst::Args { .. } => {} &Inst::Ret { link, .. } => { - let link = allocs.next(link); + debug_assert_eq!(link, gpr(14)); let opcode = 0x07; // BCR put(sink, &enc_rr(opcode, gpr(15), link)); diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 8e3e4eda57..4c8d27a367 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -1009,17 +1009,17 @@ fn s390x_get_operands VReg>(inst: &Inst, collector: &mut OperandC collector.reg_use(rn); } &Inst::Call { link, ref info } => { - collector.reg_def(link); for u in &info.uses { collector.reg_fixed_use(u.vreg, u.preg); } for d in &info.defs { collector.reg_fixed_def(d.vreg, d.preg); } - collector.reg_clobbers(info.clobbers); + let mut clobbers = info.clobbers.clone(); + clobbers.add(link.to_reg().to_real_reg().unwrap().into()); + collector.reg_clobbers(clobbers); } &Inst::CallInd { link, ref info } => { - collector.reg_def(link); collector.reg_use(info.rn); for u in &info.uses { collector.reg_fixed_use(u.vreg, u.preg); @@ -1027,16 +1027,21 @@ fn s390x_get_operands VReg>(inst: &Inst, collector: &mut OperandC for d in &info.defs { collector.reg_fixed_def(d.vreg, d.preg); } - collector.reg_clobbers(info.clobbers); + let mut clobbers = info.clobbers.clone(); + clobbers.add(link.to_reg().to_real_reg().unwrap().into()); + collector.reg_clobbers(clobbers); } &Inst::Args { ref args } => { for arg in args { collector.reg_fixed_def(arg.vreg, arg.preg); } } - &Inst::Ret { link, ref rets } => { - collector.reg_use(link); - collector.reg_uses(&rets[..]); + &Inst::Ret { ref rets, .. } => { + // NOTE: we explicitly don't mark the link register as used here, as the use is only in + // the epilog where callee-save registers are restored. + for ret in rets { + collector.reg_fixed_use(ret.vreg, ret.preg); + } } &Inst::Jump { .. } => {} &Inst::IndirectBr { rn, .. } => { @@ -3231,7 +3236,7 @@ impl Inst { format!("{} {}, {}", op, rd, rn) } &Inst::Call { link, ref info, .. } => { - let link = pretty_print_reg(link.to_reg(), allocs); + let link = link.to_reg(); let tls_symbol = match &info.tls_symbol { None => "".to_string(), Some(SymbolReloc::TlsGd { name }) => { @@ -3239,12 +3244,19 @@ impl Inst { } _ => unreachable!(), }; - format!("brasl {}, {}{}", link, info.dest.display(None), tls_symbol) + debug_assert_eq!(link, gpr(14)); + format!( + "brasl {}, {}{}", + show_reg(link), + info.dest.display(None), + tls_symbol + ) } &Inst::CallInd { link, ref info, .. } => { - let link = pretty_print_reg(link.to_reg(), allocs); + let link = link.to_reg(); let rn = pretty_print_reg(info.rn, allocs); - format!("basr {}, {}", link, rn) + debug_assert_eq!(link, gpr(14)); + format!("basr {}, {}", show_reg(link), rn) } &Inst::Args { ref args } => { let mut s = "args".to_string(); @@ -3257,8 +3269,8 @@ impl Inst { s } &Inst::Ret { link, .. } => { - let link = pretty_print_reg(link, allocs); - format!("br {}", link) + debug_assert_eq!(link, gpr(14)); + format!("br {}", show_reg(link)) } &Inst::Jump { dest } => { let dest = dest.to_string(); diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index 134cd2165f..a10ad17bef 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -298,26 +298,25 @@ mod test { // FIXME: the branching logic should be optimized more - // ahi %r2, 4660 - // chi %r2, 0 - // jglh label1 ; jg label2 - // jg label6 - // jg label3 - // ahik %r3, %r2, 4660 - // chi %r3, 0 - // jglh label4 ; jg label5 - // jg label3 - // jg label6 - // chi %r2, 0 - // jglh label7 ; jg label8 - // jg label3 - // ahi %r2, -4660 - // br %r14 + // To update this comment, write the golden bytes to a file, and run the following command + // on it to update: + // > s390x-linux-gnu-objdump -b binary -D -m s390 + // + // 0: a7 2a 12 34 ahi %r2,4660 + // 4: a7 2e 00 00 chi %r2,0 + // 8: c0 64 00 00 00 0b jglh 0x1e + // e: ec 32 12 34 00 d8 ahik %r3,%r2,4660 + // 14: a7 3e 00 00 chi %r3,0 + // 18: c0 64 ff ff ff fb jglh 0xe + // 1e: a7 2e 00 00 chi %r2,0 + // 22: c0 64 ff ff ff f6 jglh 0xe + // 28: a7 2a ed cc ahi %r2,-4660 + // 2c: 07 fe br %r14 let golden = vec![ - 236, 50, 18, 52, 0, 216, 167, 62, 0, 0, 192, 100, 0, 0, 0, 11, 236, 67, 18, 52, 0, 216, - 167, 78, 0, 0, 192, 100, 255, 255, 255, 251, 167, 62, 0, 0, 192, 100, 255, 255, 255, - 246, 236, 35, 237, 204, 0, 216, 7, 254, + 167, 42, 18, 52, 167, 46, 0, 0, 192, 100, 0, 0, 0, 11, 236, 50, 18, 52, 0, 216, 167, + 62, 0, 0, 192, 100, 255, 255, 255, 251, 167, 46, 0, 0, 192, 100, 255, 255, 255, 246, + 167, 42, 237, 204, 7, 254, ]; assert_eq!(code, &golden[..]); diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index 555a767b5d..3e697a33bb 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -298,7 +298,11 @@ impl ABIMachineSpec for X64ABIMachineSpec { Inst::Args { args } } - fn gen_ret(_setup_frame: bool, _isa_flags: &x64_settings::Flags, rets: Vec) -> Self::I { + fn gen_ret( + _setup_frame: bool, + _isa_flags: &x64_settings::Flags, + rets: Vec, + ) -> Self::I { Inst::ret(rets) } diff --git a/cranelift/codegen/src/isa/x64/inst.isle b/cranelift/codegen/src/isa/x64/inst.isle index be1c06dc4c..793be99de0 100644 --- a/cranelift/codegen/src/isa/x64/inst.isle +++ b/cranelift/codegen/src/isa/x64/inst.isle @@ -333,7 +333,7 @@ (args VecArgPair)) ;; Return. - (Ret (rets VecReg)) + (Ret (rets VecRetPair)) ;; Jump to a known target: jmp simm32. (JmpKnown (dst MachLabel)) diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 6a3eae120a..aaa698b5fe 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -526,7 +526,7 @@ impl Inst { } } - pub(crate) fn ret(rets: Vec) -> Inst { + pub(crate) fn ret(rets: Vec) -> Inst { Inst::Ret { rets } } @@ -2081,8 +2081,8 @@ fn x64_get_operands VReg>(inst: &Inst, collector: &mut OperandCol Inst::Ret { rets } => { // The return value(s) are live-out; we represent this // with register uses on the return instruction. - for &ret in rets { - collector.reg_use(ret); + for ret in rets.iter() { + collector.reg_fixed_use(ret.vreg, ret.preg); } } diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 4a6664e628..30d553ead8 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -333,31 +333,36 @@ mod test { .unwrap(); let code = result.buffer.data(); - // 00000000 55 push rbp - // 00000001 4889E5 mov rbp,rsp - // 00000004 81C734120000 add edi,0x1234 - // 0000000A 85FF test edi,edi - // 0000000C 0F841C000000 jz near 0x2e - // 00000012 4989F8 mov r8,rdi - // 00000015 4889F8 mov rax,rdi - // 00000018 81E834120000 sub eax,0x1234 - // 0000001E 4401C0 add eax,r8d - // 00000021 85FF test edi,edi - // 00000023 0F8505000000 jnz near 0x2e - // 00000029 4889EC mov rsp,rbp - // 0000002C 5D pop rbp - // 0000002D C3 ret - // 0000002E 4989F8 mov r8,rdi - // 00000031 4181C034120000 add r8d,0x1234 - // 00000038 4585C0 test r8d,r8d - // 0000003B 0F85EDFFFFFF jnz near 0x2e - // 00000041 E9CFFFFFFF jmp 0x15 + // To update this comment, write the golden bytes to a file, and run the following + // command on it: + // > objdump -b binary -D -m i386:x86-64 -M intel + // + // 0: 55 push rbp + // 1: 48 89 e5 mov rbp,rsp + // 4: 48 89 fe mov rsi,rdi + // 7: 81 c6 34 12 00 00 add esi,0x1234 + // d: 85 f6 test esi,esi + // f: 0f 84 1c 00 00 00 je 0x31 + // 15: 49 89 f0 mov r8,rsi + // 18: 48 89 f0 mov rax,rsi + // 1b: 81 e8 34 12 00 00 sub eax,0x1234 + // 21: 44 01 c0 add eax,r8d + // 24: 85 f6 test esi,esi + // 26: 0f 85 05 00 00 00 jne 0x31 + // 2c: 48 89 ec mov rsp,rbp + // 2f: 5d pop rbp + // 30: c3 ret + // 31: 49 89 f0 mov r8,rsi + // 34: 41 81 c0 34 12 00 00 add r8d,0x1234 + // 3b: 45 85 c0 test r8d,r8d + // 3e: 0f 85 ed ff ff ff jne 0x31 + // 44: e9 cf ff ff ff jmp 0x18 let golden = vec![ - 85, 72, 137, 229, 129, 199, 52, 18, 0, 0, 133, 255, 15, 132, 28, 0, 0, 0, 73, 137, 248, - 72, 137, 248, 129, 232, 52, 18, 0, 0, 68, 1, 192, 133, 255, 15, 133, 5, 0, 0, 0, 72, - 137, 236, 93, 195, 73, 137, 248, 65, 129, 192, 52, 18, 0, 0, 69, 133, 192, 15, 133, - 237, 255, 255, 255, 233, 207, 255, 255, 255, + 85, 72, 137, 229, 72, 137, 254, 129, 198, 52, 18, 0, 0, 133, 246, 15, 132, 28, 0, 0, 0, + 73, 137, 240, 72, 137, 240, 129, 232, 52, 18, 0, 0, 68, 1, 192, 133, 246, 15, 133, 5, + 0, 0, 0, 72, 137, 236, 93, 195, 73, 137, 240, 65, 129, 192, 52, 18, 0, 0, 69, 133, 192, + 15, 133, 237, 255, 255, 255, 233, 207, 255, 255, 255, ]; assert_eq!(code, &golden[..]); @@ -433,35 +438,42 @@ mod test { .unwrap(); let code = result.buffer.data(); - // 00000000 55 push rbp - // 00000001 4889E5 mov rbp,rsp - // 00000004 83FF02 cmp edi,byte +0x2 - // 00000007 0F8327000000 jnc near 0x34 - // 0000000D 448BDF mov r11d,edi - // 00000010 41BA00000000 mov r10d,0x0 - // 00000016 4D0F43DA cmovnc r11,r10 - // 0000001A 4C8D150B000000 lea r10,[rel 0x2c] - // 00000021 4F635C9A00 movsxd r11,dword [r10+r11*4+0x0] - // 00000026 4D01DA add r10,r11 - // 00000029 41FFE2 jmp r10 - // 0000002C 120000001C000000 (jumptable data) - // 00000034 B803000000 mov eax,0x3 - // 00000039 4889EC mov rsp,rbp - // 0000003C 5D pop rbp - // 0000003D C3 ret - // 0000003E B801000000 mov eax,0x1 - // 00000043 4889EC mov rsp,rbp - // 00000046 5D pop rbp - // 00000047 C3 ret - // 00000048 B802000000 mov eax,0x2 - // 0000004D 4889EC mov rsp,rbp - // 00000050 5D pop rbp - // 00000051 C3 ret + // To update this comment, write the golden bytes to a file, and run the following + // command on it: + // > objdump -b binary -D -m i386:x86-64 -M intel + // + // 0: 55 push rbp + // 1: 48 89 e5 mov rbp,rsp + // 4: 83 ff 02 cmp edi,0x2 + // 7: 0f 83 27 00 00 00 jae 0x34 + // d: 44 8b d7 mov r10d,edi + // 10: 41 b9 00 00 00 00 mov r9d,0x0 + // 16: 4d 0f 43 d1 cmovae r10,r9 + // 1a: 4c 8d 0d 0b 00 00 00 lea r9,[rip+0xb] # 0x2c + // 21: 4f 63 54 91 00 movsxd r10,DWORD PTR [r9+r10*4+0x0] + // 26: 4d 01 d1 add r9,r10 + // 29: 41 ff e1 jmp r9 + // 2c: 12 00 adc al,BYTE PTR [rax] + // 2e: 00 00 add BYTE PTR [rax],al + // 30: 1c 00 sbb al,0x0 + // 32: 00 00 add BYTE PTR [rax],al + // 34: b8 03 00 00 00 mov eax,0x3 + // 39: 48 89 ec mov rsp,rbp + // 3c: 5d pop rbp + // 3d: c3 ret + // 3e: b8 01 00 00 00 mov eax,0x1 + // 43: 48 89 ec mov rsp,rbp + // 46: 5d pop rbp + // 47: c3 ret + // 48: b8 02 00 00 00 mov eax,0x2 + // 4d: 48 89 ec mov rsp,rbp + // 50: 5d pop rbp + // 51: c3 ret let golden = vec![ - 85, 72, 137, 229, 131, 255, 2, 15, 131, 39, 0, 0, 0, 68, 139, 223, 65, 186, 0, 0, 0, 0, - 77, 15, 67, 218, 76, 141, 21, 11, 0, 0, 0, 79, 99, 92, 154, 0, 77, 1, 218, 65, 255, - 226, 18, 0, 0, 0, 28, 0, 0, 0, 184, 3, 0, 0, 0, 72, 137, 236, 93, 195, 184, 1, 0, 0, 0, + 85, 72, 137, 229, 131, 255, 2, 15, 131, 39, 0, 0, 0, 68, 139, 215, 65, 185, 0, 0, 0, 0, + 77, 15, 67, 209, 76, 141, 13, 11, 0, 0, 0, 79, 99, 84, 145, 0, 77, 1, 209, 65, 255, + 225, 18, 0, 0, 0, 28, 0, 0, 0, 184, 3, 0, 0, 0, 72, 137, 236, 93, 195, 184, 1, 0, 0, 0, 72, 137, 236, 93, 195, 184, 2, 0, 0, 0, 72, 137, 236, 93, 195, ]; diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs index 4a0c262147..1e76e230d8 100644 --- a/cranelift/codegen/src/machinst/abi.rs +++ b/cranelift/codegen/src/machinst/abi.rs @@ -136,6 +136,17 @@ pub struct ArgPair { pub preg: Reg, } +/// A type used by backends to track return register binding info in the "ret" +/// pseudoinst. The pseudoinst holds a vec of `RetPair` structs. +#[derive(Clone, Debug)] +pub struct RetPair { + /// The vreg that is returned by this pseudionst. + pub vreg: Reg, + /// The preg that the arg is returned through; this constrains the vreg's + /// placement at the pseudoinst. + pub preg: Reg, +} + /// A location for (part of) an argument or return value. These "storage slots" /// are specified for each register-sized part of an argument. #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -421,7 +432,7 @@ pub trait ABIMachineSpec { fn gen_args(isa_flags: &Self::F, args: Vec) -> Self::I; /// Generate a return instruction. - fn gen_ret(setup_frame: bool, isa_flags: &Self::F, rets: Vec) -> Self::I; + fn gen_ret(setup_frame: bool, isa_flags: &Self::F, rets: Vec) -> Self::I; /// Generate an add-with-immediate. Note that even if this uses a scratch /// register, it must satisfy two requirements: @@ -1483,8 +1494,10 @@ impl Callee { &self, sigs: &SigSet, idx: usize, - from_regs: ValueRegs>, - ) -> SmallInstVec { + from_regs: ValueRegs, + vregs: &mut VRegAllocator, + ) -> (SmallVec<[RetPair; 2]>, SmallInstVec) { + let mut reg_pairs = smallvec![]; let mut ret = smallvec![]; let word_bits = M::word_bits() as u8; match &sigs[self.sig].rets(sigs)[idx] { @@ -1497,24 +1510,31 @@ impl Callee { } => { let from_bits = ty_bits(ty) as u8; let ext = M::get_ext_mode(sigs[self.sig].call_conv, extension); - let reg: Writable = Writable::from_reg(Reg::from(reg)); - match (ext, from_bits) { - (ArgumentExtension::Uext, n) | (ArgumentExtension::Sext, n) + let vreg = match (ext, from_bits) { + (ir::ArgumentExtension::Uext, n) + | (ir::ArgumentExtension::Sext, n) if n < word_bits => { - let signed = ext == ArgumentExtension::Sext; + let signed = ext == ir::ArgumentExtension::Sext; + let dst = writable_value_regs(vregs.alloc(ty).unwrap()) + .only_reg() + .unwrap(); ret.push(M::gen_extend( - reg, - from_reg.to_reg(), - signed, - from_bits, + dst, from_reg, signed, from_bits, /* to_bits = */ word_bits, )); + dst.to_reg() } _ => { - ret.push(M::gen_move(reg, from_reg.to_reg(), ty)); + // No move needed, regalloc2 will emit it using the constraint + // added by the RetPair. + from_reg } }; + reg_pairs.push(RetPair { + vreg, + preg: Reg::from(reg), + }); } &ABIArgSlot::Stack { offset, @@ -1533,16 +1553,17 @@ impl Callee { let ext = M::get_ext_mode(sigs[self.sig].call_conv, extension); // Trash the from_reg; it should be its last use. match (ext, from_bits) { - (ArgumentExtension::Uext, n) | (ArgumentExtension::Sext, n) + (ir::ArgumentExtension::Uext, n) + | (ir::ArgumentExtension::Sext, n) if n < word_bits => { - assert_eq!(M::word_reg_class(), from_reg.to_reg().class()); - let signed = ext == ArgumentExtension::Sext; + assert_eq!(M::word_reg_class(), from_reg.class()); + let signed = ext == ir::ArgumentExtension::Sext; + let dst = writable_value_regs(vregs.alloc(ty).unwrap()) + .only_reg() + .unwrap(); ret.push(M::gen_extend( - Writable::from_reg(from_reg.to_reg()), - from_reg.to_reg(), - signed, - from_bits, + dst, from_reg, signed, from_bits, /* to_bits = */ word_bits, )); // Store the extended version. @@ -1553,21 +1574,21 @@ impl Callee { ret.push(M::gen_store_base_offset( self.ret_area_ptr.unwrap().to_reg(), off, - from_reg.to_reg(), + from_reg, ty, )); } } } } - &ABIArg::StructArg { .. } => { + ABIArg::StructArg { .. } => { panic!("StructArg in return position is unsupported"); } - &ABIArg::ImplicitPtrArg { .. } => { + ABIArg::ImplicitPtrArg { .. } => { panic!("ImplicitPtrArg in return position is unsupported"); } } - ret + (reg_pairs, ret) } /// Generate any setup instruction needed to save values to the @@ -1594,22 +1615,7 @@ impl Callee { } /// Generate a return instruction. - pub fn gen_ret(&self, sigs: &SigSet) -> M::I { - let mut rets = vec![]; - for ret in sigs[self.sig].rets(sigs) { - match ret { - ABIArg::Slots { slots, .. } => { - for slot in slots { - match slot { - ABIArgSlot::Reg { reg, .. } => rets.push(Reg::from(*reg)), - _ => {} - } - } - } - _ => {} - } - } - + pub fn gen_ret(&self, rets: Vec) -> M::I { M::gen_ret(self.setup_frame, &self.isa_flags, rets) } diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index 5b70bb0b22..441a37fa8d 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -7,8 +7,9 @@ use std::cell::Cell; use target_lexicon::Triple; pub use super::MachLabel; +use super::RetPair; pub use crate::ir::{ - condcodes, condcodes::CondCode, dynamic_to_fixed, ArgumentExtension, Constant, + condcodes, condcodes::CondCode, dynamic_to_fixed, ArgumentExtension, ArgumentPurpose, Constant, DynamicStackSlot, ExternalName, FuncRef, GlobalValue, Immediate, SigRef, StackSlot, }; pub use crate::isa::unwind::UnwindInst; @@ -23,7 +24,7 @@ pub type ValueSlice = (ValueList, usize); pub type ValueArray2 = [Value; 2]; pub type ValueArray3 = [Value; 3]; pub type WritableReg = Writable; -pub type VecReg = Vec; +pub type VecRetPair = Vec; pub type VecMask = Vec; pub type ValueRegs = crate::machinst::ValueRegs; pub type WritableValueRegs = crate::machinst::ValueRegs; @@ -422,10 +423,6 @@ macro_rules! isle_lower_prelude_methods { )) } - fn retval(&mut self, i: usize) -> WritableValueRegs { - self.lower_ctx.retval(i) - } - fn only_writable_reg(&mut self, regs: WritableValueRegs) -> Option { regs.only_reg() } @@ -590,6 +587,17 @@ macro_rules! isle_lower_prelude_methods { fn floatcc_inverse(&mut self, cc: &FloatCC) -> FloatCC { cc.inverse() } + + /// Generate the return instruction. + fn gen_return(&mut self, (list, off): ValueSlice) { + let rets = (off..list.len(&self.lower_ctx.dfg().value_lists)) + .map(|ix| { + let val = list.get(ix, &self.lower_ctx.dfg().value_lists).unwrap(); + self.put_in_regs(val) + }) + .collect(); + self.lower_ctx.gen_return(rets); + } }; } diff --git a/cranelift/codegen/src/machinst/lower.rs b/cranelift/codegen/src/machinst/lower.rs index 3dea3b2793..8e7dc6a02c 100644 --- a/cranelift/codegen/src/machinst/lower.rs +++ b/cranelift/codegen/src/machinst/lower.rs @@ -158,8 +158,8 @@ pub struct Lower<'func, I: VCodeInst> { /// Mapping from `Value` (SSA value in IR) to virtual register. value_regs: SecondaryMap>, - /// Return-value vregs. - retval_regs: Vec>, + /// sret registers, if needed. + sret_reg: Option>, /// Instruction colors at block exits. From this map, we can recover all /// instruction colors by scanning backward from the block end and @@ -370,12 +370,13 @@ impl<'func, I: VCodeInst> Lower<'func, I> { } } - // Assign vreg(s) to each return value. - let mut retval_regs = vec![]; + // Make a sret register, if one is needed. + let mut sret_reg = None; for ret in &vcode.abi().signature().returns.clone() { - let regs = vregs.alloc(ret.value_type)?; - retval_regs.push(regs); - trace!("retval gets regs {:?}", regs); + if ret.purpose == ArgumentPurpose::StructReturn { + assert!(sret_reg.is_none()); + sret_reg = Some(vregs.alloc(ret.value_type)?); + } } // Compute instruction colors, find constant instructions, and find instructions with @@ -414,7 +415,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> { vcode, vregs, value_regs, - retval_regs, + sret_reg, block_end_colors, side_effect_inst_entry_colors, inst_constants, @@ -576,15 +577,15 @@ impl<'func, I: VCodeInst> Lower<'func, I> { let ty = self.abi().signature().params[i].value_type; // The ABI implementation must have ensured that a StructReturn // arg is present in the return values. - let struct_ret_idx = self + assert!(self .abi() .signature() .returns .iter() .position(|ret| ret.purpose == ArgumentPurpose::StructReturn) - .expect("StructReturn return value not present!"); + .is_some()); self.emit(I::gen_move( - Writable::from_reg(self.retval_regs[struct_ret_idx].regs()[0]), + Writable::from_reg(self.sret_reg.unwrap().regs()[0]), regs.regs()[0].to_reg(), ty, )); @@ -611,21 +612,36 @@ impl<'func, I: VCodeInst> Lower<'func, I> { } } - fn gen_retval_setup(&mut self) { - let retval_regs = self.retval_regs.clone(); - for (i, regs) in retval_regs.into_iter().enumerate() { - let regs = writable_value_regs(regs); - for insn in self - .vcode - .abi() - .gen_copy_regs_to_retval(self.sigs(), i, regs) - .into_iter() - { + /// Generate the return instruction. + pub fn gen_return(&mut self, rets: Vec>) { + let mut out_rets = vec![]; + + let mut rets = rets.into_iter(); + for (i, ret) in self + .abi() + .signature() + .returns + .clone() + .into_iter() + .enumerate() + { + let regs = if ret.purpose == ArgumentPurpose::StructReturn { + self.sret_reg.unwrap().clone() + } else { + rets.next().unwrap() + }; + + let (regs, insns) = self.vcode.abi().gen_copy_regs_to_retval( + self.vcode.sigs(), + i, + regs, + &mut self.vregs, + ); + out_rets.extend(regs); + for insn in insns { self.emit(insn); } } - let inst = self.vcode.abi().gen_ret(self.sigs()); - self.emit(inst); // Hack: generate a virtual instruction that uses vmctx in // order to keep it alive for the duration of the function, @@ -636,6 +652,9 @@ impl<'func, I: VCodeInst> Lower<'func, I> { self.emit(I::gen_dummy_use(vmctx_reg)); } } + + let inst = self.abi().gen_ret(out_rets); + self.emit(inst); } /// Has this instruction been sunk to a use-site (i.e., away from its @@ -720,10 +739,6 @@ impl<'func, I: VCodeInst> Lower<'func, I> { trace!("lowering: inst {}: {:?}", inst, self.f.dfg[inst]); backend.lower(self, inst)?; } - if data.opcode().is_return() { - // Return: handle specially, using ABI-appropriate sequence. - self.gen_retval_setup(); - } let loc = self.srcloc(inst); self.finish_ir_inst(loc); @@ -1026,14 +1041,6 @@ impl<'func, I: VCodeInst> Lower<'func, I> { pub fn abi_mut(&mut self) -> &mut Callee { self.vcode.abi_mut() } - - /// Get the (virtual) register that receives the return value. A return - /// instruction should lower into a sequence that fills this register. (Why - /// not allow the backend to specify its own result register for the return? - /// Because there may be multiple return points.) - pub fn retval(&self, idx: usize) -> ValueRegs> { - writable_value_regs(self.retval_regs[idx]) - } } /// Instruction input/output queries. diff --git a/cranelift/codegen/src/prelude_lower.isle b/cranelift/codegen/src/prelude_lower.isle index e88a4d5931..597ddb0043 100644 --- a/cranelift/codegen/src/prelude_lower.isle +++ b/cranelift/codegen/src/prelude_lower.isle @@ -158,6 +158,7 @@ (type BoxExternalName (primitive BoxExternalName)) (type RelocDistance (primitive RelocDistance)) (type VecArgPair extern (enum)) +(type VecRetPair extern (enum)) ;;;; Helper Clif Extractors ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -614,10 +615,6 @@ ;;;; Helpers for generating returns ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; The (writable) register(s) that will contain the n'th return value. -(decl retval (usize) WritableValueRegs) -(extern constructor retval retval) - ;; Extractor to check for the special case that a `WritableValueRegs` ;; contains only a single register. (decl only_writable_reg (WritableReg) WritableValueRegs) @@ -725,31 +722,14 @@ (decl gen_move (Type WritableReg Reg) MInst) (extern constructor gen_move gen_move) -;; Copy a return value to a set of registers. -(decl copy_to_regs (WritableValueRegs Value) Unit) -(rule (copy_to_regs dsts val @ (value_type ty)) - (let ((srcs ValueRegs (put_in_regs val))) - (copy_to_regs_range ty (value_regs_range srcs) dsts srcs))) - -;; Helper for `copy_to_regs` that uses a range to index into the reg/value -;; vectors. Fails for the empty range. -(decl copy_to_regs_range (Type Range WritableValueRegs ValueRegs) Unit) - -(rule (copy_to_regs_range ty (range_empty) dsts srcs) - (unit)) - -(rule (copy_to_regs_range ty (range_unwrap head tail) dsts srcs) - (let ((dst WritableReg (writable_regs_get dsts head)) - (src Reg (value_regs_get srcs head)) - (_ Unit (emit (gen_move ty dst src)))) - (copy_to_regs_range ty tail dsts srcs))) - - +;; Generate a return instruction (decl lower_return (Range ValueSlice) InstOutput) -(rule (lower_return (range_empty) _) (output_none)) -(rule (lower_return (range_unwrap head tail) args) - (let ((_ Unit (copy_to_regs (retval head) (value_slice_get args head)))) - (lower_return tail args))) +(rule (lower_return _ vals) + (let ((_ Unit (gen_return vals))) + (output_none))) + +(decl gen_return (ValueSlice) Unit) +(extern constructor gen_return gen_return) ;;;; Automatic conversions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/cranelift/filetests/filetests/isa/aarch64/amodes.clif b/cranelift/filetests/filetests/isa/aarch64/amodes.clif index c28ec2eb49..43ef1b4d63 100644 --- a/cranelift/filetests/filetests/isa/aarch64/amodes.clif +++ b/cranelift/filetests/filetests/isa/aarch64/amodes.clif @@ -36,8 +36,8 @@ block0(v0: i32, v1: i32): } ; block0: -; mov w4, w0 -; ldr w0, [x4, w1, UXTW] +; mov w3, w0 +; ldr w0, [x3, w1, UXTW] ; ret function %f8(i64, i32) -> i32 { @@ -52,10 +52,10 @@ block0(v0: i64, v1: i32): } ; block0: -; add x4, x0, #68 -; add x4, x4, x0 -; add x4, x4, x1, SXTW -; ldr w0, [x4, w1, SXTW] +; add x3, x0, #68 +; add x3, x3, x0 +; add x3, x3, x1, SXTW +; ldr w0, [x3, w1, SXTW] ; ret function %f9(i64, i64, i64) -> i32 { @@ -69,10 +69,10 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; mov x6, x0 -; add x6, x6, x2 -; add x6, x6, x1 -; ldr w0, [x6, #48] +; mov x5, x0 +; add x5, x5, x2 +; add x5, x5, x1 +; ldr w0, [x5, #48] ; ret function %f10(i64, i64, i64) -> i32 { @@ -86,10 +86,10 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; movz x5, #4100 -; add x5, x5, x1 -; add x5, x5, x2 -; ldr w0, [x5, x0] +; movz x4, #4100 +; add x4, x4, x1 +; add x4, x4, x2 +; ldr w0, [x4, x0] ; ret function %f10() -> i32 { @@ -100,8 +100,8 @@ block0: } ; block0: -; movz x1, #1234 -; ldr w0, [x1] +; movz x0, #1234 +; ldr w0, [x0] ; ret function %f11(i64) -> i32 { @@ -113,8 +113,8 @@ block0(v0: i64): } ; block0: -; add x3, x0, #8388608 -; ldr w0, [x3] +; add x2, x0, #8388608 +; ldr w0, [x2] ; ret function %f12(i64) -> i32 { @@ -126,8 +126,8 @@ block0(v0: i64): } ; block0: -; sub x3, x0, #4 -; ldr w0, [x3] +; sub x2, x0, #4 +; ldr w0, [x2] ; ret function %f13(i64) -> i32 { @@ -139,10 +139,10 @@ block0(v0: i64): } ; block0: -; movz w3, #51712 -; movk w3, w3, #15258, LSL #16 -; add x3, x3, x0 -; ldr w0, [x3] +; movz w2, #51712 +; movk w2, w2, #15258, LSL #16 +; add x2, x2, x0 +; ldr w0, [x2] ; ret function %f14(i32) -> i32 { @@ -153,8 +153,8 @@ block0(v0: i32): } ; block0: -; sxtw x3, w0 -; ldr w0, [x3] +; sxtw x2, w0 +; ldr w0, [x2] ; ret function %f15(i32, i32) -> i32 { @@ -167,8 +167,8 @@ block0(v0: i32, v1: i32): } ; block0: -; sxtw x4, w0 -; ldr w0, [x4, w1, SXTW] +; sxtw x3, w0 +; ldr w0, [x3, w1, SXTW] ; ret function %f18(i64, i64, i64) -> i32 { @@ -180,8 +180,8 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; movn w5, #4097 -; ldrsh x0, [x5] +; movn w4, #4097 +; ldrsh x0, [x4] ; ret function %f19(i64, i64, i64) -> i32 { @@ -193,8 +193,8 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; movz x5, #4098 -; ldrsh x0, [x5] +; movz x4, #4098 +; ldrsh x0, [x4] ; ret function %f20(i64, i64, i64) -> i32 { @@ -206,9 +206,9 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; movn w5, #4097 -; sxtw x7, w5 -; ldrsh x0, [x7] +; movn w4, #4097 +; sxtw x6, w4 +; ldrsh x0, [x6] ; ret function %f21(i64, i64, i64) -> i32 { @@ -220,9 +220,9 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; movz x5, #4098 -; sxtw x7, w5 -; ldrsh x0, [x7] +; movz x4, #4098 +; sxtw x6, w4 +; ldrsh x0, [x6] ; ret function %i128(i64) -> i128 { @@ -233,11 +233,11 @@ block0(v0: i64): } ; block0: -; mov x8, x0 -; mov x6, x8 -; ldp x0, x1, [x6] -; mov x7, x8 -; stp x0, x1, [x7] +; mov x6, x0 +; mov x4, x6 +; ldp x0, x1, [x4] +; mov x5, x6 +; stp x0, x1, [x5] ; ret function %i128_imm_offset(i64) -> i128 { @@ -248,11 +248,11 @@ block0(v0: i64): } ; block0: -; mov x8, x0 -; mov x6, x8 -; ldp x0, x1, [x6, #16] -; mov x7, x8 -; stp x0, x1, [x7, #16] +; mov x6, x0 +; mov x4, x6 +; ldp x0, x1, [x4, #16] +; mov x5, x6 +; stp x0, x1, [x5, #16] ; ret function %i128_imm_offset_large(i64) -> i128 { @@ -263,11 +263,11 @@ block0(v0: i64): } ; block0: -; mov x8, x0 -; mov x6, x8 -; ldp x0, x1, [x6, #504] -; mov x7, x8 -; stp x0, x1, [x7, #504] +; mov x6, x0 +; mov x4, x6 +; ldp x0, x1, [x4, #504] +; mov x5, x6 +; stp x0, x1, [x5, #504] ; ret function %i128_imm_offset_negative_large(i64) -> i128 { @@ -278,11 +278,11 @@ block0(v0: i64): } ; block0: -; mov x8, x0 -; mov x6, x8 -; ldp x0, x1, [x6, #-512] -; mov x7, x8 -; stp x0, x1, [x7, #-512] +; mov x6, x0 +; mov x4, x6 +; ldp x0, x1, [x4, #-512] +; mov x5, x6 +; stp x0, x1, [x5, #-512] ; ret function %i128_add_offset(i64) -> i128 { @@ -294,11 +294,11 @@ block0(v0: i64): } ; block0: -; mov x8, x0 -; mov x6, x8 -; ldp x0, x1, [x6, #32] -; mov x7, x8 -; stp x0, x1, [x7, #32] +; mov x6, x0 +; mov x4, x6 +; ldp x0, x1, [x4, #32] +; mov x5, x6 +; stp x0, x1, [x5, #32] ; ret function %i128_32bit_sextend_simple(i32) -> i128 { @@ -310,11 +310,11 @@ block0(v0: i32): } ; block0: -; sxtw x6, w0 -; ldp x10, x1, [x6] -; sxtw x7, w0 -; mov x0, x10 -; stp x0, x1, [x7] +; sxtw x4, w0 +; mov x11, x0 +; ldp x0, x1, [x4] +; sxtw x5, w11 +; stp x0, x1, [x5] ; ret function %i128_32bit_sextend(i64, i32) -> i128 { @@ -328,13 +328,13 @@ block0(v0: i64, v1: i32): } ; block0: -; mov x11, x0 -; mov x7, x11 -; add x7, x7, x1, SXTW -; ldp x0, x10, [x7, #24] -; mov x9, x11 -; add x9, x9, x1, SXTW -; mov x1, x10 -; stp x0, x1, [x9, #24] +; mov x9, x0 +; mov x5, x9 +; add x5, x5, x1, SXTW +; mov x11, x1 +; ldp x0, x1, [x5, #24] +; mov x7, x9 +; add x7, x7, x11, SXTW +; stp x0, x1, [x7, #24] ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif b/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif index 657736e41b..b8c3d77ce5 100644 --- a/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif +++ b/cranelift/filetests/filetests/isa/aarch64/arithmetic.clif @@ -74,8 +74,8 @@ block0(v0: i64): } ; block0: -; movz w3, #2 -; sdiv x0, x0, x3 +; movz w2, #2 +; sdiv x0, x0, x2 ; ret function %f8(i64, i64) -> i64 { @@ -97,8 +97,8 @@ block0(v0: i64): } ; block0: -; orr x3, xzr, #2 -; udiv x0, x0, x3 +; orr x2, xzr, #2 +; udiv x0, x0, x2 ; ret function %f10(i64, i64) -> i64 { @@ -109,8 +109,8 @@ block0(v0: i64, v1: i64): ; block0: ; cbnz x1, 8 ; udf -; sdiv x5, x0, x1 -; msub x0, x5, x1, x0 +; sdiv x4, x0, x1 +; msub x0, x4, x1, x0 ; ret function %f11(i64, i64) -> i64 { @@ -121,8 +121,8 @@ block0(v0: i64, v1: i64): ; block0: ; cbnz x1, 8 ; udf -; udiv x5, x0, x1 -; msub x0, x5, x1, x0 +; udiv x4, x0, x1 +; msub x0, x4, x1, x0 ; ret function %f12(i32, i32) -> i32 { @@ -132,13 +132,13 @@ block0(v0: i32, v1: i32): } ; block0: -; sxtw x4, w0 -; sxtw x6, w1 -; cbnz x6, 8 ; udf -; adds wzr, w6, #1 -; ccmp w4, #1, #nzcv, eq +; sxtw x3, w0 +; sxtw x5, w1 +; cbnz x5, 8 ; udf +; adds wzr, w5, #1 +; ccmp w3, #1, #nzcv, eq ; b.vc 8 ; udf -; sdiv x0, x4, x6 +; sdiv x0, x3, x5 ; ret function %f13(i32) -> i32 { @@ -149,9 +149,9 @@ block0(v0: i32): } ; block0: -; sxtw x3, w0 -; movz w5, #2 -; sdiv x0, x3, x5 +; sxtw x2, w0 +; movz w4, #2 +; sdiv x0, x2, x4 ; ret function %f14(i32, i32) -> i32 { @@ -161,10 +161,10 @@ block0(v0: i32, v1: i32): } ; block0: -; mov w4, w0 -; mov w6, w1 -; cbnz x6, 8 ; udf -; udiv x0, x4, x6 +; mov w3, w0 +; mov w5, w1 +; cbnz x5, 8 ; udf +; udiv x0, x3, x5 ; ret function %f15(i32) -> i32 { @@ -175,9 +175,9 @@ block0(v0: i32): } ; block0: -; mov w3, w0 -; orr w5, wzr, #2 -; udiv x0, x3, x5 +; mov w2, w0 +; orr w4, wzr, #2 +; udiv x0, x2, x4 ; ret function %f16(i32, i32) -> i32 { @@ -187,11 +187,11 @@ block0(v0: i32, v1: i32): } ; block0: -; sxtw x4, w0 -; sxtw x6, w1 -; cbnz x6, 8 ; udf -; sdiv x9, x4, x6 -; msub x0, x9, x6, x4 +; sxtw x3, w0 +; sxtw x5, w1 +; cbnz x5, 8 ; udf +; sdiv x8, x3, x5 +; msub x0, x8, x5, x3 ; ret function %f17(i32, i32) -> i32 { @@ -201,11 +201,11 @@ block0(v0: i32, v1: i32): } ; block0: -; mov w4, w0 -; mov w6, w1 -; cbnz x6, 8 ; udf -; udiv x9, x4, x6 -; msub x0, x9, x6, x4 +; mov w3, w0 +; mov w5, w1 +; cbnz x5, 8 ; udf +; udiv x8, x3, x5 +; msub x0, x8, x5, x3 ; ret function %f18(i64, i64) -> i64 { @@ -331,8 +331,8 @@ block0(v0: i64): } ; block0: -; movz x3, #1 -; sub x0, xzr, x3 +; movz x2, #1 +; sub x0, xzr, x2 ; ret function %f30(i8x16) -> i8x16 { @@ -343,11 +343,11 @@ block0(v0: i8x16): } ; block0: -; movz x3, #1 -; and w5, w3, #7 -; sub x7, xzr, x5 -; dup v17.16b, w7 -; ushl v0.16b, v0.16b, v17.16b +; movz x2, #1 +; and w4, w2, #7 +; sub x6, xzr, x4 +; dup v16.16b, w6 +; ushl v0.16b, v0.16b, v16.16b ; ret function %add_i128(i128, i128) -> i128 { @@ -379,9 +379,9 @@ block0(v0: i128, v1: i128): } ; block0: -; umulh x7, x0, x2 -; madd x9, x0, x3, x7 -; madd x1, x1, x2, x9 +; umulh x5, x0, x2 +; madd x7, x0, x3, x5 +; madd x1, x1, x2, x7 ; madd x0, x0, x2, xzr ; ret @@ -437,8 +437,8 @@ block0(v0: i32, v1: i32, v2: i32): } ; block0: -; madd w6, w1, w2, wzr -; sub w0, w6, w0 +; madd w5, w1, w2, wzr +; sub w0, w5, w0 ; ret function %imul_sub_i64(i64, i64, i64) -> i64 { @@ -449,8 +449,8 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; madd x6, x1, x2, xzr -; sub x0, x6, x0 +; madd x5, x1, x2, xzr +; sub x0, x5, x0 ; ret function %srem_const (i64) -> i64 { @@ -461,9 +461,9 @@ block0(v0: i64): } ; block0: -; movz w3, #2 -; sdiv x5, x0, x3 -; msub x0, x5, x3, x0 +; movz w2, #2 +; sdiv x4, x0, x2 +; msub x0, x4, x2, x0 ; ret function %urem_const (i64) -> i64 { @@ -474,9 +474,9 @@ block0(v0: i64): } ; block0: -; orr x3, xzr, #2 -; udiv x5, x0, x3 -; msub x0, x5, x3, x0 +; orr x2, xzr, #2 +; udiv x4, x0, x2 +; msub x0, x4, x2, x0 ; ret function %sdiv_minus_one(i64) -> i64 { @@ -487,9 +487,10 @@ block0(v0: i64): } ; block0: -; movn x3, #0 -; adds xzr, x3, #1 +; movn x2, #0 +; adds xzr, x2, #1 ; ccmp x0, #1, #nzcv, eq ; b.vc 8 ; udf -; sdiv x0, x0, x3 +; sdiv x0, x0, x2 ; ret + diff --git a/cranelift/filetests/filetests/isa/aarch64/bitops.clif b/cranelift/filetests/filetests/isa/aarch64/bitops.clif index b74e9ef420..6ea2115a4e 100644 --- a/cranelift/filetests/filetests/isa/aarch64/bitops.clif +++ b/cranelift/filetests/filetests/isa/aarch64/bitops.clif @@ -9,8 +9,8 @@ block0(v0: i8): } ; block0: -; rbit w3, w0 -; lsr w0, w3, #24 +; rbit w2, w0 +; lsr w0, w2, #24 ; ret function %a(i16) -> i16 { @@ -20,8 +20,8 @@ block0(v0: i16): } ; block0: -; rbit w3, w0 -; lsr w0, w3, #16 +; rbit w2, w0 +; lsr w0, w2, #16 ; ret function %a(i32) -> i32 { @@ -51,9 +51,9 @@ block0(v0: i128): } ; block0: -; rbit x5, x0 -; rbit x0, x1 -; mov x1, x5 +; mov x6, x1 +; rbit x1, x0 +; rbit x0, x6 ; ret function %b(i8) -> i8 { @@ -63,9 +63,9 @@ block0(v0: i8): } ; block0: -; uxtb w3, w0 -; clz w5, w3 -; sub w0, w5, #24 +; uxtb w2, w0 +; clz w4, w2 +; sub w0, w4, #24 ; ret function %b(i16) -> i16 { @@ -75,9 +75,9 @@ block0(v0: i16): } ; block0: -; uxth w3, w0 -; clz w5, w3 -; sub w0, w5, #16 +; uxth w2, w0 +; clz w4, w2 +; sub w0, w4, #16 ; ret function %b(i32) -> i32 { @@ -107,10 +107,10 @@ block0(v0: i128): } ; block0: -; clz x5, x1 -; clz x7, x0 -; lsr x9, x5, #6 -; madd x0, x7, x9, x5 +; clz x3, x1 +; clz x5, x0 +; lsr x7, x3, #6 +; madd x0, x5, x7, x3 ; movz w1, #0 ; ret @@ -121,9 +121,9 @@ block0(v0: i8): } ; block0: -; sxtb w3, w0 -; cls w5, w3 -; sub w0, w5, #24 +; sxtb w2, w0 +; cls w4, w2 +; sub w0, w4, #24 ; ret function %c(i16) -> i16 { @@ -133,9 +133,9 @@ block0(v0: i16): } ; block0: -; sxth w3, w0 -; cls w5, w3 -; sub w0, w5, #16 +; sxth w2, w0 +; cls w4, w2 +; sub w0, w4, #16 ; ret function %c(i32) -> i32 { @@ -165,14 +165,14 @@ block0(v0: i128): } ; block0: -; cls x5, x0 -; cls x7, x1 -; eon x9, x1, x0 -; lsr x11, x9, #63 -; madd x13, x5, x11, x11 -; subs xzr, x7, #63 -; csel x0, x13, xzr, eq -; add x0, x0, x7 +; cls x3, x0 +; cls x5, x1 +; eon x7, x1, x0 +; lsr x9, x7, #63 +; madd x11, x3, x9, x9 +; subs xzr, x5, #63 +; csel x14, x11, xzr, eq +; add x0, x14, x5 ; movz w1, #0 ; ret @@ -183,9 +183,9 @@ block0(v0: i8): } ; block0: -; rbit w3, w0 -; orr w5, w3, #8388608 -; clz w0, w5 +; rbit w2, w0 +; orr w4, w2, #8388608 +; clz w0, w4 ; ret function %d(i16) -> i16 { @@ -195,9 +195,9 @@ block0(v0: i16): } ; block0: -; rbit w3, w0 -; orr w5, w3, #32768 -; clz w0, w5 +; rbit w2, w0 +; orr w4, w2, #32768 +; clz w0, w4 ; ret function %d(i32) -> i32 { @@ -207,8 +207,8 @@ block0(v0: i32): } ; block0: -; rbit w3, w0 -; clz w0, w3 +; rbit w2, w0 +; clz w0, w2 ; ret function %d(i64) -> i64 { @@ -217,24 +217,24 @@ block0(v0: i64): return v1 } +; block0: +; rbit x2, x0 +; clz x0, x2 +; ret + +function %d(i128) -> i128 { +block0(v0: i128): + v1 = ctz v0 + return v1 +} + ; block0: ; rbit x3, x0 -; clz x0, x3 -; ret - -function %d(i128) -> i128 { -block0(v0: i128): - v1 = ctz v0 - return v1 -} - -; block0: -; rbit x5, x0 -; rbit x7, x1 +; rbit x5, x1 +; clz x7, x3 ; clz x9, x5 -; clz x11, x7 -; lsr x13, x9, #6 -; madd x0, x11, x13, x9 +; lsr x11, x7, #6 +; madd x0, x9, x11, x7 ; movz w1, #0 ; ret @@ -245,11 +245,11 @@ block0(v0: i128): } ; block0: -; fmov d6, x0 -; mov v6.d[1], v6.d[1], x1 -; cnt v17.16b, v6.16b -; addv b19, v17.16b -; umov w0, v19.b[0] +; fmov d4, x0 +; mov v4.d[1], v4.d[1], x1 +; cnt v7.16b, v4.16b +; addv b17, v7.16b +; umov w0, v17.b[0] ; movz w1, #0 ; ret @@ -260,10 +260,10 @@ block0(v0: i64): } ; block0: -; fmov d3, x0 -; cnt v5.8b, v3.8b -; addv b7, v5.8b -; umov w0, v7.b[0] +; fmov d2, x0 +; cnt v4.8b, v2.8b +; addv b6, v4.8b +; umov w0, v6.b[0] ; ret function %d(i32) -> i32 { @@ -273,10 +273,10 @@ block0(v0: i32): } ; block0: -; fmov s3, w0 -; cnt v5.8b, v3.8b -; addv b7, v5.8b -; umov w0, v7.b[0] +; fmov s2, w0 +; cnt v4.8b, v2.8b +; addv b6, v4.8b +; umov w0, v6.b[0] ; ret function %d(i16) -> i16 { @@ -286,10 +286,10 @@ block0(v0: i16): } ; block0: -; fmov s3, w0 -; cnt v5.8b, v3.8b -; addp v7.8b, v5.8b, v5.8b -; umov w0, v7.b[0] +; fmov s2, w0 +; cnt v4.8b, v2.8b +; addp v6.8b, v4.8b, v4.8b +; umov w0, v6.b[0] ; ret function %d(i8) -> i8 { @@ -299,9 +299,9 @@ block0(v0: i8): } ; block0: -; fmov s3, w0 -; cnt v5.8b, v3.8b -; umov w0, v5.b[0] +; fmov s2, w0 +; cnt v4.8b, v2.8b +; umov w0, v4.b[0] ; ret function %sextend_i8() -> i32 { @@ -312,8 +312,8 @@ block0: } ; block0: -; movn x1, #0 -; sxtb w0, w1 +; movn x0, #0 +; sxtb w0, w0 ; ret function %sextend_i8() -> i32 { @@ -324,8 +324,8 @@ block0: } ; block0: -; movn x1, #0 -; sxtb w0, w1 +; movn x0, #0 +; sxtb w0, w0 ; ret function %bnot_i32(i32) -> i32 { @@ -821,15 +821,15 @@ block0(v0: i128, v1: i8): } ; block0: -; lsl x6, x0, x2 -; lsl x8, x1, x2 -; orn w10, wzr, w2 -; lsr x12, x0, #1 -; lsr x14, x12, x10 -; orr x1, x8, x14 +; lsl x4, x0, x2 +; lsl x6, x1, x2 +; orn w8, wzr, w2 +; lsr x10, x0, #1 +; lsr x12, x10, x8 +; orr x14, x6, x12 ; ands xzr, x2, #64 -; csel x0, xzr, x6, ne -; csel x1, x6, x1, ne +; csel x0, xzr, x4, ne +; csel x1, x4, x14, ne ; ret function %ishl_i128_i128(i128, i128) -> i128 { @@ -839,15 +839,15 @@ block0(v0: i128, v1: i128): } ; block0: -; lsl x7, x0, x2 -; lsl x9, x1, x2 -; orn w11, wzr, w2 -; lsr x13, x0, #1 -; lsr x15, x13, x11 -; orr x1, x9, x15 +; lsl x5, x0, x2 +; lsl x7, x1, x2 +; orn w9, wzr, w2 +; lsr x11, x0, #1 +; lsr x13, x11, x9 +; orr x15, x7, x13 ; ands xzr, x2, #64 -; csel x0, xzr, x7, ne -; csel x1, x7, x1, ne +; csel x0, xzr, x5, ne +; csel x1, x5, x15, ne ; ret function %ushr_i128_i8(i128, i8) -> i128 { @@ -857,15 +857,15 @@ block0(v0: i128, v1: i8): } ; block0: -; lsr x6, x0, x2 -; lsr x8, x1, x2 -; orn w10, wzr, w2 -; lsl x12, x1, #1 -; lsl x14, x12, x10 -; orr x0, x6, x14 +; lsr x4, x0, x2 +; lsr x6, x1, x2 +; orn w8, wzr, w2 +; lsl x10, x1, #1 +; lsl x12, x10, x8 +; orr x14, x4, x12 ; ands xzr, x2, #64 -; csel x0, x8, x0, ne -; csel x1, xzr, x8, ne +; csel x0, x6, x14, ne +; csel x1, xzr, x6, ne ; ret function %ushr_i128_i128(i128, i128) -> i128 { @@ -875,15 +875,15 @@ block0(v0: i128, v1: i128): } ; block0: -; lsr x7, x0, x2 -; lsr x9, x1, x2 -; orn w11, wzr, w2 -; lsl x13, x1, #1 -; lsl x15, x13, x11 -; orr x1, x7, x15 +; lsr x5, x0, x2 +; lsr x7, x1, x2 +; orn w9, wzr, w2 +; lsl x11, x1, #1 +; lsl x13, x11, x9 +; orr x15, x5, x13 ; ands xzr, x2, #64 -; csel x0, x9, x1, ne -; csel x1, xzr, x9, ne +; csel x0, x7, x15, ne +; csel x1, xzr, x7, ne ; ret function %sshr_i128_i8(i128, i8) -> i128 { @@ -893,16 +893,16 @@ block0(v0: i128, v1: i8): } ; block0: -; lsr x6, x0, x2 -; asr x8, x1, x2 -; orn w10, wzr, w2 -; lsl x12, x1, #1 -; lsl x14, x12, x10 -; asr x1, x1, #63 -; orr x3, x6, x14 +; lsr x4, x0, x2 +; asr x6, x1, x2 +; orn w8, wzr, w2 +; lsl x10, x1, #1 +; lsl x12, x10, x8 +; asr x14, x1, #63 +; orr x0, x4, x12 ; ands xzr, x2, #64 -; csel x0, x8, x3, ne -; csel x1, x1, x8, ne +; csel x0, x6, x0, ne +; csel x1, x14, x6, ne ; ret function %sshr_i128_i128(i128, i128) -> i128 { @@ -912,15 +912,15 @@ block0(v0: i128, v1: i128): } ; block0: -; lsr x7, x0, x2 -; asr x9, x1, x2 -; orn w11, wzr, w2 -; lsl x13, x1, #1 -; lsl x15, x13, x11 -; asr x1, x1, #63 -; orr x3, x7, x15 +; lsr x5, x0, x2 +; asr x7, x1, x2 +; orn w9, wzr, w2 +; lsl x11, x1, #1 +; lsl x13, x11, x9 +; asr x15, x1, #63 +; orr x1, x5, x13 ; ands xzr, x2, #64 -; csel x0, x9, x3, ne -; csel x1, x1, x9, ne +; csel x0, x7, x1, ne +; csel x1, x15, x7, ne ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/bti.clif b/cranelift/filetests/filetests/isa/aarch64/bti.clif index 157a767fa3..98d5957db4 100644 --- a/cranelift/filetests/filetests/isa/aarch64/bti.clif +++ b/cranelift/filetests/filetests/isa/aarch64/bti.clif @@ -33,7 +33,7 @@ block5(v5: i32): ; block0: ; emit_island 44 ; subs wzr, w0, #3 -; b.hs label1 ; csel x1, xzr, x0, hs ; csdb ; adr x15, pc+16 ; ldrsw x1, [x15, x1, uxtw #2] ; add x15, x15, x1 ; br x15 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))] +; b.hs label1 ; csel x15, xzr, x0, hs ; csdb ; adr x14, pc+16 ; ldrsw x15, [x14, x15, uxtw #2] ; add x14, x14, x15 ; br x14 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))] ; block1: ; movz x5, #4 ; b label2 @@ -80,16 +80,17 @@ block2: ; bti c ; block0: -; ldr x6, [x0] +; ldr x5, [x0] +; mov x8, x5 ; emit_island 36 ; subs wzr, w0, #1 -; b.hs label1 ; csel x8, xzr, x0, hs ; csdb ; adr x7, pc+16 ; ldrsw x8, [x7, x8, uxtw #2] ; add x7, x7, x8 ; br x7 ; jt_entries [Label(MachLabel(2))] +; b.hs label1 ; csel x7, xzr, x0, hs ; csdb ; adr x6, pc+16 ; ldrsw x7, [x6, x7, uxtw #2] ; add x6, x6, x7 ; br x6 ; jt_entries [Label(MachLabel(2))] ; block1: -; mov x0, x6 +; mov x0, x8 ; ret ; block2: ; bti j -; mov x0, x6 +; mov x0, x8 ; add x0, x0, #42 ; ret @@ -105,8 +106,8 @@ block0(v0: i64): ; stp fp, lr, [sp, #-16]! ; mov fp, sp ; block0: -; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0 -; blr x4 +; ldr x3, 8 ; b 12 ; data TestCase(%g) + 0 +; blr x3 ; ldp fp, lr, [sp], #16 ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif b/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif index bb1a853f90..c6e7be3de4 100644 --- a/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif +++ b/cranelift/filetests/filetests/isa/aarch64/call-pauth.clif @@ -14,8 +14,8 @@ block0(v0: i64): ; stp fp, lr, [sp, #-16]! ; mov fp, sp ; block0: -; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0 -; blr x4 +; ldr x3, 8 ; b 12 ; data TestCase(%g) + 0 +; blr x3 ; ldp fp, lr, [sp], #16 ; autiasp ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/call.clif b/cranelift/filetests/filetests/isa/aarch64/call.clif index add90de40e..71c3592479 100644 --- a/cranelift/filetests/filetests/isa/aarch64/call.clif +++ b/cranelift/filetests/filetests/isa/aarch64/call.clif @@ -14,8 +14,8 @@ block0(v0: i64): ; stp fp, lr, [sp, #-16]! ; mov fp, sp ; block0: -; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0 -; blr x4 +; ldr x3, 8 ; b 12 ; data TestCase(%g) + 0 +; blr x3 ; ldp fp, lr, [sp], #16 ; ret @@ -30,8 +30,8 @@ block0(v0: i32): ; stp fp, lr, [sp, #-16]! ; mov fp, sp ; block0: -; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0 -; blr x4 +; ldr x3, 8 ; b 12 ; data TestCase(%g) + 0 +; blr x3 ; ldp fp, lr, [sp], #16 ; ret @@ -54,8 +54,8 @@ block0(v0: i32): ; stp fp, lr, [sp, #-16]! ; mov fp, sp ; block0: -; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0 -; blr x4 +; ldr x3, 8 ; b 12 ; data TestCase(%g) + 0 +; blr x3 ; ldp fp, lr, [sp], #16 ; ret @@ -105,8 +105,8 @@ block0(v0: i8): } ; block0: -; mov x8, x0 -; mov x13, x1 +; mov x9, x0 +; mov x8, x1 ; movz x0, #42 ; movz x1, #42 ; movz x2, #42 @@ -115,8 +115,7 @@ block0(v0: i8): ; movz x5, #42 ; movz x6, #42 ; movz x7, #42 -; mov x11, x8 -; strb w11, [x13] +; strb w9, [x8] ; ret function %f8() { @@ -283,8 +282,8 @@ block0(v0: i64): ; mov x1, x0 ; movz x0, #42 ; movz x2, #42 -; ldr x7, 8 ; b 12 ; data TestCase(%f11) + 0 -; blr x7 +; ldr x6, 8 ; b 12 ; data TestCase(%f11) + 0 +; blr x6 ; ldp fp, lr, [sp], #16 ; ret @@ -314,8 +313,8 @@ block0(v0: i64): ; mov x2, x0 ; movz x3, #42 ; movz x0, #42 -; ldr x7, 8 ; b 12 ; data TestCase(%f12) + 0 -; blr x7 +; ldr x6, 8 ; b 12 ; data TestCase(%f12) + 0 +; blr x6 ; ldp fp, lr, [sp], #16 ; ret @@ -345,8 +344,8 @@ block0(v0: i64): ; mov x1, x0 ; movz x2, #42 ; movz x0, #42 -; ldr x7, 8 ; b 12 ; data TestCase(%f13) + 0 -; blr x7 +; ldr x6, 8 ; b 12 ; data TestCase(%f13) + 0 +; blr x6 ; ldp fp, lr, [sp], #16 ; ret @@ -381,12 +380,12 @@ block0(v0: i128, v1: i64): ; mov x4, x0 ; str x1, [sp, #8] ; mov x5, x1 -; ldr x12, 8 ; b 12 ; data TestCase(%f14) + 0 +; ldr x10, 8 ; b 12 ; data TestCase(%f14) + 0 ; mov x0, x4 ; mov x2, x4 ; mov x1, x5 ; mov x3, x5 -; blr x12 +; blr x10 ; add sp, sp, #16 ; virtual_sp_offset_adjust -16 ; ldp fp, lr, [sp], #16 @@ -423,12 +422,12 @@ block0(v0: i128, v1: i64): ; mov x4, x0 ; str x1, [sp, #8] ; mov x5, x1 -; ldr x12, 8 ; b 12 ; data TestCase(%f15) + 0 +; ldr x10, 8 ; b 12 ; data TestCase(%f15) + 0 ; mov x0, x4 ; mov x2, x4 ; mov x1, x5 ; mov x3, x5 -; blr x12 +; blr x10 ; add sp, sp, #16 ; virtual_sp_offset_adjust -16 ; ldp fp, lr, [sp], #16 @@ -442,10 +441,10 @@ block0: } ; block0: -; mov x11, x0 +; mov x6, x0 ; movz x0, #0 -; movz x7, #1 -; str w7, [x11] +; movz x4, #1 +; str w4, [x6] ; ret function %f17(i64 sret) { @@ -473,8 +472,8 @@ block0(v0: i64): ; mov fp, sp ; block0: ; mov x8, x0 -; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0 -; blr x4 +; ldr x3, 8 ; b 12 ; data TestCase(%g) + 0 +; blr x3 ; ldp fp, lr, [sp], #16 ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/compare_zero.clif b/cranelift/filetests/filetests/isa/aarch64/compare_zero.clif index 556d7b5f2c..4b13b8c150 100644 --- a/cranelift/filetests/filetests/isa/aarch64/compare_zero.clif +++ b/cranelift/filetests/filetests/isa/aarch64/compare_zero.clif @@ -57,8 +57,8 @@ block0(v0: i32x4): } ; block0: -; cmeq v3.4s, v0.4s, #0 -; mvn v0.16b, v3.16b +; cmeq v2.4s, v0.4s, #0 +; mvn v0.16b, v2.16b ; ret function %f2_vconst(i32x4) -> i32x4 { @@ -69,8 +69,8 @@ block0(v0: i32x4): } ; block0: -; cmeq v3.4s, v0.4s, #0 -; mvn v0.16b, v3.16b +; cmeq v2.4s, v0.4s, #0 +; mvn v0.16b, v2.16b ; ret function %f3(i64x2) -> i64x2 { @@ -82,8 +82,8 @@ block0(v0: i64x2): } ; block0: -; cmeq v3.2d, v0.2d, #0 -; mvn v0.16b, v3.16b +; cmeq v2.2d, v0.2d, #0 +; mvn v0.16b, v2.16b ; ret function %f3_vconst(i64x2) -> i64x2 { @@ -94,8 +94,8 @@ block0(v0: i64x2): } ; block0: -; cmeq v3.2d, v0.2d, #0 -; mvn v0.16b, v3.16b +; cmeq v2.2d, v0.2d, #0 +; mvn v0.16b, v2.16b ; ret function %f4(i8x16) -> i8x16 { @@ -337,8 +337,8 @@ block0(v0: f64x2): } ; block0: -; fcmeq v3.2d, v0.2d, #0.0 -; mvn v0.16b, v3.16b +; fcmeq v2.2d, v0.2d, #0.0 +; mvn v0.16b, v2.16b ; ret function %f14_vconst(f64x2) -> i64x2 { @@ -349,8 +349,8 @@ block0(v0: f64x2): } ; block0: -; fcmeq v3.2d, v0.2d, #0.0 -; mvn v0.16b, v3.16b +; fcmeq v2.2d, v0.2d, #0.0 +; mvn v0.16b, v2.16b ; ret function %f15(f32x4) -> i32x4 { @@ -362,8 +362,8 @@ block0(v0: f32x4): } ; block0: -; fcmeq v3.4s, v0.4s, #0.0 -; mvn v0.16b, v3.16b +; fcmeq v2.4s, v0.4s, #0.0 +; mvn v0.16b, v2.16b ; ret function %f15_vconst(f32x4) -> i32x4 { @@ -374,8 +374,8 @@ block0(v0: f32x4): } ; block0: -; fcmeq v3.4s, v0.4s, #0.0 -; mvn v0.16b, v3.16b +; fcmeq v2.4s, v0.4s, #0.0 +; mvn v0.16b, v2.16b ; ret function %f16(f32x4) -> i32x4 { diff --git a/cranelift/filetests/filetests/isa/aarch64/condbr.clif b/cranelift/filetests/filetests/isa/aarch64/condbr.clif index 247393d072..6aa63389a7 100644 --- a/cranelift/filetests/filetests/isa/aarch64/condbr.clif +++ b/cranelift/filetests/filetests/isa/aarch64/condbr.clif @@ -45,10 +45,10 @@ block0(v0: i128, v1: i128): ; block0: ; subs xzr, x0, x2 -; cset x7, lo +; cset x6, lo ; subs xzr, x1, x3 -; cset x10, lt -; csel x0, x7, x10, eq +; cset x9, lt +; csel x0, x6, x9, eq ; ret function %icmp_ult_i128(i128, i128) -> i8 { @@ -59,10 +59,10 @@ block0(v0: i128, v1: i128): ; block0: ; subs xzr, x0, x2 -; cset x7, lo +; cset x6, lo ; subs xzr, x1, x3 -; cset x10, lo -; csel x0, x7, x10, eq +; cset x9, lo +; csel x0, x6, x9, eq ; ret function %icmp_sle_i128(i128, i128) -> i8 { @@ -73,10 +73,10 @@ block0(v0: i128, v1: i128): ; block0: ; subs xzr, x0, x2 -; cset x7, ls +; cset x6, ls ; subs xzr, x1, x3 -; cset x10, le -; csel x0, x7, x10, eq +; cset x9, le +; csel x0, x6, x9, eq ; ret function %icmp_ule_i128(i128, i128) -> i8 { @@ -87,10 +87,10 @@ block0(v0: i128, v1: i128): ; block0: ; subs xzr, x0, x2 -; cset x7, ls +; cset x6, ls ; subs xzr, x1, x3 -; cset x10, ls -; csel x0, x7, x10, eq +; cset x9, ls +; csel x0, x6, x9, eq ; ret function %icmp_sgt_i128(i128, i128) -> i8 { @@ -101,10 +101,10 @@ block0(v0: i128, v1: i128): ; block0: ; subs xzr, x0, x2 -; cset x7, hi +; cset x6, hi ; subs xzr, x1, x3 -; cset x10, gt -; csel x0, x7, x10, eq +; cset x9, gt +; csel x0, x6, x9, eq ; ret function %icmp_ugt_i128(i128, i128) -> i8 { @@ -115,10 +115,10 @@ block0(v0: i128, v1: i128): ; block0: ; subs xzr, x0, x2 -; cset x7, hi +; cset x6, hi ; subs xzr, x1, x3 -; cset x10, hi -; csel x0, x7, x10, eq +; cset x9, hi +; csel x0, x6, x9, eq ; ret function %icmp_sge_i128(i128, i128) -> i8 { @@ -129,10 +129,10 @@ block0(v0: i128, v1: i128): ; block0: ; subs xzr, x0, x2 -; cset x7, hs +; cset x6, hs ; subs xzr, x1, x3 -; cset x10, ge -; csel x0, x7, x10, eq +; cset x9, ge +; csel x0, x6, x9, eq ; ret function %icmp_uge_i128(i128, i128) -> i8 { @@ -143,10 +143,10 @@ block0(v0: i128, v1: i128): ; block0: ; subs xzr, x0, x2 -; cset x7, hs +; cset x6, hs ; subs xzr, x1, x3 -; cset x10, hs -; csel x0, x7, x10, eq +; cset x9, hs +; csel x0, x6, x9, eq ; ret function %f(i64, i64) -> i64 { diff --git a/cranelift/filetests/filetests/isa/aarch64/condops.clif b/cranelift/filetests/filetests/isa/aarch64/condops.clif index 3ca6d03e9f..9f964e7f3f 100644 --- a/cranelift/filetests/filetests/isa/aarch64/condops.clif +++ b/cranelift/filetests/filetests/isa/aarch64/condops.clif @@ -11,8 +11,8 @@ block0(v0: i8, v1: i8, v2: i8): } ; block0: -; uxtb w5, w0 -; subs wzr, w5, #42 +; uxtb w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; ret @@ -25,8 +25,8 @@ block0(v0: i8, v1: i16, v2: i16): } ; block0: -; uxtb w5, w0 -; subs wzr, w5, #42 +; uxtb w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; ret @@ -39,8 +39,8 @@ block0(v0: i8, v1: i32, v2: i32): } ; block0: -; uxtb w5, w0 -; subs wzr, w5, #42 +; uxtb w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; ret @@ -53,8 +53,8 @@ block0(v0: i8, v1: i64, v2: i64): } ; block0: -; uxtb w5, w0 -; subs wzr, w5, #42 +; uxtb w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; ret @@ -67,8 +67,8 @@ block0(v0: i8, v1: i128, v2: i128): } ; block0: -; uxtb w8, w0 -; subs wzr, w8, #42 +; uxtb w6, w0 +; subs wzr, w6, #42 ; csel x0, x2, x4, eq ; csel x1, x3, x5, eq ; ret @@ -82,8 +82,8 @@ block0(v0: i16, v1: i8, v2: i8): } ; block0: -; uxth w5, w0 -; subs wzr, w5, #42 +; uxth w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; ret @@ -96,8 +96,8 @@ block0(v0: i16, v1: i16, v2: i16): } ; block0: -; uxth w5, w0 -; subs wzr, w5, #42 +; uxth w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; ret @@ -110,8 +110,8 @@ block0(v0: i16, v1: i32, v2: i32): } ; block0: -; uxth w5, w0 -; subs wzr, w5, #42 +; uxth w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; ret @@ -124,8 +124,8 @@ block0(v0: i16, v1: i64, v2: i64): } ; block0: -; uxth w5, w0 -; subs wzr, w5, #42 +; uxth w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; ret @@ -138,8 +138,8 @@ block0(v0: i16, v1: i128, v2: i128): } ; block0: -; uxth w8, w0 -; subs wzr, w8, #42 +; uxth w6, w0 +; subs wzr, w6, #42 ; csel x0, x2, x4, eq ; csel x1, x3, x5, eq ; ret @@ -286,10 +286,10 @@ block0(v0: i128, v1: i8, v2: i8): } ; block0: -; movz x7, #42 -; movz w9, #0 -; subs xzr, x0, x7 -; ccmp x1, x9, #nzcv, eq +; movz x6, #42 +; movz w8, #0 +; subs xzr, x0, x6 +; ccmp x1, x8, #nzcv, eq ; csel x0, x2, x3, eq ; ret @@ -303,10 +303,10 @@ block0(v0: i128, v1: i16, v2: i16): } ; block0: -; movz x7, #42 -; movz w9, #0 -; subs xzr, x0, x7 -; ccmp x1, x9, #nzcv, eq +; movz x6, #42 +; movz w8, #0 +; subs xzr, x0, x6 +; ccmp x1, x8, #nzcv, eq ; csel x0, x2, x3, eq ; ret @@ -320,10 +320,10 @@ block0(v0: i128, v1: i32, v2: i32): } ; block0: -; movz x7, #42 -; movz w9, #0 -; subs xzr, x0, x7 -; ccmp x1, x9, #nzcv, eq +; movz x6, #42 +; movz w8, #0 +; subs xzr, x0, x6 +; ccmp x1, x8, #nzcv, eq ; csel x0, x2, x3, eq ; ret @@ -337,10 +337,10 @@ block0(v0: i128, v1: i64, v2: i64): } ; block0: -; movz x7, #42 -; movz w9, #0 -; subs xzr, x0, x7 -; ccmp x1, x9, #nzcv, eq +; movz x6, #42 +; movz w8, #0 +; subs xzr, x0, x6 +; ccmp x1, x8, #nzcv, eq ; csel x0, x2, x3, eq ; ret @@ -354,10 +354,10 @@ block0(v0: i128, v1: i128, v2: i128): } ; block0: -; movz x11, #42 -; movz w13, #0 -; subs xzr, x0, x11 -; ccmp x1, x13, #nzcv, eq +; movz x9, #42 +; movz w11, #0 +; subs xzr, x0, x9 +; ccmp x1, x11, #nzcv, eq ; csel x0, x2, x4, eq ; csel x1, x3, x5, eq ; ret @@ -371,8 +371,8 @@ block0(v0: i8, v1: i8, v2: i8): } ; block0: -; uxtb w5, w0 -; subs wzr, w5, #42 +; uxtb w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; csdb ; ret @@ -386,8 +386,8 @@ block0(v0: i8, v1: i16, v2: i16): } ; block0: -; uxtb w5, w0 -; subs wzr, w5, #42 +; uxtb w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; csdb ; ret @@ -401,8 +401,8 @@ block0(v0: i8, v1: i32, v2: i32): } ; block0: -; uxtb w5, w0 -; subs wzr, w5, #42 +; uxtb w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; csdb ; ret @@ -416,8 +416,8 @@ block0(v0: i8, v1: i64, v2: i64): } ; block0: -; uxtb w5, w0 -; subs wzr, w5, #42 +; uxtb w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; csdb ; ret @@ -431,8 +431,8 @@ block0(v0: i8, v1: i128, v2: i128): } ; block0: -; uxtb w8, w0 -; subs wzr, w8, #42 +; uxtb w6, w0 +; subs wzr, w6, #42 ; csel x0, x2, x4, eq ; csel x1, x3, x5, eq ; csdb @@ -447,8 +447,8 @@ block0(v0: i16, v1: i8, v2: i8): } ; block0: -; uxth w5, w0 -; subs wzr, w5, #42 +; uxth w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; csdb ; ret @@ -462,8 +462,8 @@ block0(v0: i16, v1: i16, v2: i16): } ; block0: -; uxth w5, w0 -; subs wzr, w5, #42 +; uxth w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; csdb ; ret @@ -477,8 +477,8 @@ block0(v0: i16, v1: i32, v2: i32): } ; block0: -; uxth w5, w0 -; subs wzr, w5, #42 +; uxth w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; csdb ; ret @@ -492,8 +492,8 @@ block0(v0: i16, v1: i64, v2: i64): } ; block0: -; uxth w5, w0 -; subs wzr, w5, #42 +; uxth w4, w0 +; subs wzr, w4, #42 ; csel x0, x1, x2, eq ; csdb ; ret @@ -507,8 +507,8 @@ block0(v0: i16, v1: i128, v2: i128): } ; block0: -; uxth w8, w0 -; subs wzr, w8, #42 +; uxth w6, w0 +; subs wzr, w6, #42 ; csel x0, x2, x4, eq ; csel x1, x3, x5, eq ; csdb @@ -666,10 +666,10 @@ block0(v0: i128, v1: i8, v2: i8): } ; block0: -; movz x7, #42 -; movz w9, #0 -; subs xzr, x0, x7 -; ccmp x1, x9, #nzcv, eq +; movz x6, #42 +; movz w8, #0 +; subs xzr, x0, x6 +; ccmp x1, x8, #nzcv, eq ; csel x0, x2, x3, eq ; csdb ; ret @@ -684,10 +684,10 @@ block0(v0: i128, v1: i16, v2: i16): } ; block0: -; movz x7, #42 -; movz w9, #0 -; subs xzr, x0, x7 -; ccmp x1, x9, #nzcv, eq +; movz x6, #42 +; movz w8, #0 +; subs xzr, x0, x6 +; ccmp x1, x8, #nzcv, eq ; csel x0, x2, x3, eq ; csdb ; ret @@ -702,10 +702,10 @@ block0(v0: i128, v1: i32, v2: i32): } ; block0: -; movz x7, #42 -; movz w9, #0 -; subs xzr, x0, x7 -; ccmp x1, x9, #nzcv, eq +; movz x6, #42 +; movz w8, #0 +; subs xzr, x0, x6 +; ccmp x1, x8, #nzcv, eq ; csel x0, x2, x3, eq ; csdb ; ret @@ -720,10 +720,10 @@ block0(v0: i128, v1: i64, v2: i64): } ; block0: -; movz x7, #42 -; movz w9, #0 -; subs xzr, x0, x7 -; ccmp x1, x9, #nzcv, eq +; movz x6, #42 +; movz w8, #0 +; subs xzr, x0, x6 +; ccmp x1, x8, #nzcv, eq ; csel x0, x2, x3, eq ; csdb ; ret @@ -738,10 +738,10 @@ block0(v0: i128, v1: i128, v2: i128): } ; block0: -; movz x11, #42 -; movz w13, #0 -; subs xzr, x0, x11 -; ccmp x1, x13, #nzcv, eq +; movz x9, #42 +; movz w11, #0 +; subs xzr, x0, x9 +; ccmp x1, x11, #nzcv, eq ; csel x0, x2, x4, eq ; csel x1, x3, x5, eq ; csdb @@ -755,8 +755,8 @@ block0(v0: i8): } ; block0: -; uxtb w3, w0 -; subs wzr, w3, #42 +; uxtb w2, w0 +; subs wzr, w2, #42 ; cset x0, eq ; ret @@ -767,9 +767,9 @@ block0(v0: i8, v1: i8, v2: i8): } ; block0: -; and w5, w1, w0 -; bic w7, w2, w0 -; orr w0, w5, w7 +; and w4, w1, w0 +; bic w6, w2, w0 +; orr w0, w4, w6 ; ret function %i(i8, i8, i8) -> i8 { diff --git a/cranelift/filetests/filetests/isa/aarch64/constants.clif b/cranelift/filetests/filetests/isa/aarch64/constants.clif index f40a4c9082..4059ac782e 100644 --- a/cranelift/filetests/filetests/isa/aarch64/constants.clif +++ b/cranelift/filetests/filetests/isa/aarch64/constants.clif @@ -224,8 +224,8 @@ block0: } ; block0: -; movz x2, #16457, LSL #48 -; fmov d0, x2 +; movz x1, #16457, LSL #48 +; fmov d0, x1 ; ret function %f() -> f32 { @@ -235,8 +235,8 @@ block0: } ; block0: -; movz x2, #16968, LSL #16 -; fmov s0, w2 +; movz x1, #16968, LSL #16 +; fmov s0, w1 ; ret function %f() -> f64 { diff --git a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-narrow.clif b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-narrow.clif index 303e030ab1..9c9123f356 100644 --- a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-narrow.clif +++ b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-narrow.clif @@ -15,9 +15,9 @@ block0(v0: i16): } ; block0: -; dup v4.4h, w0 -; mov v4.d[1], v4.d[1], v4.d[0] -; sqxtn v0.8b, v4.8h +; dup v3.4h, w0 +; mov v3.d[1], v3.d[1], v3.d[0] +; sqxtn v0.8b, v3.8h ; ret function %snarrow_i16x8(i16) -> i8x16 { @@ -34,9 +34,9 @@ block0(v0: i16): } ; block0: -; dup v6.8h, w0 -; sqxtn v0.8b, v6.8h -; sqxtn2 v0.16b, v0.16b, v6.8h +; dup v5.8h, w0 +; sqxtn v0.8b, v5.8h +; sqxtn2 v0.16b, v0.16b, v5.8h ; ret function %snarrow_i32x2(i32) -> i16x4 { @@ -53,9 +53,9 @@ block0(v0: i32): } ; block0: -; dup v4.2s, w0 -; mov v4.d[1], v4.d[1], v4.d[0] -; sqxtn v0.4h, v4.4s +; dup v3.2s, w0 +; mov v3.d[1], v3.d[1], v3.d[0] +; sqxtn v0.4h, v3.4s ; ret function %snarrow_i32x4(i32) -> i16x8 { @@ -72,9 +72,9 @@ block0(v0: i32): } ; block0: -; dup v6.4s, w0 -; sqxtn v0.4h, v6.4s -; sqxtn2 v0.8h, v0.8h, v6.4s +; dup v5.4s, w0 +; sqxtn v0.4h, v5.4s +; sqxtn2 v0.8h, v0.8h, v5.4s ; ret function %snarrow_i64x2(i64) -> i32x4 { @@ -91,9 +91,9 @@ block0(v0: i64): } ; block0: -; dup v6.2d, x0 -; sqxtn v0.2s, v6.2d -; sqxtn2 v0.4s, v0.4s, v6.2d +; dup v5.2d, x0 +; sqxtn v0.2s, v5.2d +; sqxtn2 v0.4s, v0.4s, v5.2d ; ret function %unarrow_i16x4(i16) -> i8x8 { @@ -110,9 +110,9 @@ block0(v0: i16): } ; block0: -; dup v4.4h, w0 -; mov v4.d[1], v4.d[1], v4.d[0] -; sqxtun v0.8b, v4.8h +; dup v3.4h, w0 +; mov v3.d[1], v3.d[1], v3.d[0] +; sqxtun v0.8b, v3.8h ; ret function %unarrow_i16x8(i16) -> i8x16 { @@ -129,9 +129,9 @@ block0(v0: i16): } ; block0: -; dup v6.8h, w0 -; sqxtun v0.8b, v6.8h -; sqxtun2 v0.16b, v0.16b, v6.8h +; dup v5.8h, w0 +; sqxtun v0.8b, v5.8h +; sqxtun2 v0.16b, v0.16b, v5.8h ; ret function %unarrow_i32x2(i32) -> i16x4 { @@ -148,9 +148,9 @@ block0(v0: i32): } ; block0: -; dup v4.2s, w0 -; mov v4.d[1], v4.d[1], v4.d[0] -; sqxtun v0.4h, v4.4s +; dup v3.2s, w0 +; mov v3.d[1], v3.d[1], v3.d[0] +; sqxtun v0.4h, v3.4s ; ret function %unarrow_i32x4(i32) -> i16x8 { @@ -167,9 +167,9 @@ block0(v0: i32): } ; block0: -; dup v6.4s, w0 -; sqxtun v0.4h, v6.4s -; sqxtun2 v0.8h, v0.8h, v6.4s +; dup v5.4s, w0 +; sqxtun v0.4h, v5.4s +; sqxtun2 v0.8h, v0.8h, v5.4s ; ret function %unarrow_i64x2(i64) -> i32x4 { @@ -186,9 +186,9 @@ block0(v0: i64): } ; block0: -; dup v6.2d, x0 -; sqxtun v0.2s, v6.2d -; sqxtun2 v0.4s, v0.4s, v6.2d +; dup v5.2d, x0 +; sqxtun v0.2s, v5.2d +; sqxtun2 v0.4s, v0.4s, v5.2d ; ret function %uunarrow_i16x4(i16) -> i8x8 { @@ -205,9 +205,9 @@ block0(v0: i16): } ; block0: -; dup v4.4h, w0 -; mov v4.d[1], v4.d[1], v4.d[0] -; uqxtn v0.8b, v4.8h +; dup v3.4h, w0 +; mov v3.d[1], v3.d[1], v3.d[0] +; uqxtn v0.8b, v3.8h ; ret function %uunarrow_i16x8(i16) -> i8x16 { @@ -224,9 +224,9 @@ block0(v0: i16): } ; block0: -; dup v6.8h, w0 -; uqxtn v0.8b, v6.8h -; uqxtn2 v0.16b, v0.16b, v6.8h +; dup v5.8h, w0 +; uqxtn v0.8b, v5.8h +; uqxtn2 v0.16b, v0.16b, v5.8h ; ret function %uunarrow_i32x2(i32) -> i16x4 { @@ -243,9 +243,9 @@ block0(v0: i32): } ; block0: -; dup v4.2s, w0 -; mov v4.d[1], v4.d[1], v4.d[0] -; uqxtn v0.4h, v4.4s +; dup v3.2s, w0 +; mov v3.d[1], v3.d[1], v3.d[0] +; uqxtn v0.4h, v3.4s ; ret function %uunarrow_i32x4(i32) -> i16x8 { @@ -262,9 +262,9 @@ block0(v0: i32): } ; block0: -; dup v6.4s, w0 -; uqxtn v0.4h, v6.4s -; uqxtn2 v0.8h, v0.8h, v6.4s +; dup v5.4s, w0 +; uqxtn v0.4h, v5.4s +; uqxtn2 v0.8h, v0.8h, v5.4s ; ret function %uunarrow_i64x2(i64) -> i32x4 { @@ -281,8 +281,8 @@ block0(v0: i64): } ; block0: -; dup v6.2d, x0 -; uqxtn v0.2s, v6.2d -; uqxtn2 v0.4s, v0.4s, v6.2d +; dup v5.2d, x0 +; uqxtn v0.2s, v5.2d +; uqxtn2 v0.4s, v0.4s, v5.2d ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-neon.clif b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-neon.clif index 412a3b75b3..70ae36742a 100644 --- a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-neon.clif +++ b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-neon.clif @@ -14,9 +14,9 @@ block0(v0: i8, v1: i8): } ; block0: -; dup v7.16b, w0 -; dup v16.16b, w1 -; add v0.16b, v7.16b, v16.16b +; dup v6.16b, w0 +; dup v7.16b, w1 +; add v0.16b, v6.16b, v7.16b ; ret function %i16x8_splat_add(i16, i16) -> i16x8 { @@ -32,9 +32,9 @@ block0(v0: i16, v1: i16): } ; block0: -; dup v7.8h, w0 -; dup v16.8h, w1 -; add v0.8h, v7.8h, v16.8h +; dup v6.8h, w0 +; dup v7.8h, w1 +; add v0.8h, v6.8h, v7.8h ; ret function %i32x4_splat_mul(i32, i32) -> i32x4 { @@ -50,9 +50,9 @@ block0(v0: i32, v1: i32): } ; block0: -; dup v7.4s, w0 -; dup v16.4s, w1 -; mul v0.4s, v7.4s, v16.4s +; dup v6.4s, w0 +; dup v7.4s, w1 +; mul v0.4s, v6.4s, v7.4s ; ret function %i64x2_splat_sub(i64, i64) -> i64x2 { @@ -68,9 +68,9 @@ block0(v0: i64, v1: i64): } ; block0: -; dup v7.2d, x0 -; dup v16.2d, x1 -; sub v0.2d, v7.2d, v16.2d +; dup v6.2d, x0 +; dup v7.2d, x1 +; sub v0.2d, v6.2d, v7.2d ; ret function %f32x4_splat_add(f32, f32) -> f32x4 { @@ -86,9 +86,9 @@ block0(v0: f32, v1: f32): } ; block0: -; dup v7.4s, v0.s[0] -; dup v16.4s, v1.s[0] -; fadd v0.4s, v7.4s, v16.4s +; dup v6.4s, v0.s[0] +; dup v7.4s, v1.s[0] +; fadd v0.4s, v6.4s, v7.4s ; ret function %f64x2_splat_sub(f64, f64) -> f64x2 { @@ -104,9 +104,9 @@ block0(v0: f64, v1: f64): } ; block0: -; dup v7.2d, v0.d[0] -; dup v16.2d, v1.d[0] -; fsub v0.2d, v7.2d, v16.2d +; dup v6.2d, v0.d[0] +; dup v7.2d, v1.d[0] +; fsub v0.2d, v6.2d, v7.2d ; ret function %f64x2_splat_mul(f64, f64) -> f64x2 { @@ -122,9 +122,9 @@ block0(v0: f64, v1: f64): } ; block0: -; dup v7.2d, v0.d[0] -; dup v16.2d, v1.d[0] -; fmul v0.2d, v7.2d, v16.2d +; dup v6.2d, v0.d[0] +; dup v7.2d, v1.d[0] +; fmul v0.2d, v6.2d, v7.2d ; ret function %f64x2_splat_div(f64, f64) -> f64x2 { @@ -140,9 +140,9 @@ block0(v0: f64, v1: f64): } ; block0: -; dup v7.2d, v0.d[0] -; dup v16.2d, v1.d[0] -; fdiv v0.2d, v7.2d, v16.2d +; dup v6.2d, v0.d[0] +; dup v7.2d, v1.d[0] +; fdiv v0.2d, v6.2d, v7.2d ; ret function %f64x2_splat_min(f64, f64) -> f64x2 { @@ -158,9 +158,9 @@ block0(v0: f64, v1: f64): } ; block0: -; dup v7.2d, v0.d[0] -; dup v16.2d, v1.d[0] -; fmin v0.2d, v7.2d, v16.2d +; dup v6.2d, v0.d[0] +; dup v7.2d, v1.d[0] +; fmin v0.2d, v6.2d, v7.2d ; ret function %f64x2_splat_max(f64, f64) -> f64x2 { @@ -176,9 +176,9 @@ block0(v0: f64, v1: f64): } ; block0: -; dup v7.2d, v0.d[0] -; dup v16.2d, v1.d[0] -; fmax v0.2d, v7.2d, v16.2d +; dup v6.2d, v0.d[0] +; dup v7.2d, v1.d[0] +; fmax v0.2d, v6.2d, v7.2d ; ret function %f64x2_splat_min_pseudo(f64, f64) -> f64x2 { @@ -194,10 +194,10 @@ block0(v0: f64, v1: f64): } ; block0: -; dup v16.2d, v0.d[0] -; dup v17.2d, v1.d[0] -; fcmgt v0.2d, v16.2d, v17.2d -; bsl v0.16b, v0.16b, v17.16b, v16.16b +; dup v7.2d, v0.d[0] +; dup v16.2d, v1.d[0] +; fcmgt v0.2d, v7.2d, v16.2d +; bsl v0.16b, v0.16b, v16.16b, v7.16b ; ret function %f64x2_splat_max_pseudo(f64, f64) -> f64x2 { @@ -213,9 +213,9 @@ block0(v0: f64, v1: f64): } ; block0: -; dup v16.2d, v0.d[0] -; dup v17.2d, v1.d[0] -; fcmgt v0.2d, v17.2d, v16.2d -; bsl v0.16b, v0.16b, v17.16b, v16.16b +; dup v7.2d, v0.d[0] +; dup v16.2d, v1.d[0] +; fcmgt v0.2d, v16.2d, v7.2d +; bsl v0.16b, v0.16b, v16.16b, v7.16b ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-widen.clif b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-widen.clif index 6fda772d85..71f40eb360 100644 --- a/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-widen.clif +++ b/cranelift/filetests/filetests/isa/aarch64/dynamic-simd-widen.clif @@ -15,8 +15,8 @@ block0(v0: i8): } ; block0: -; dup v5.16b, w0 -; sxtl2 v0.8h, v5.16b +; dup v4.16b, w0 +; sxtl2 v0.8h, v4.16b ; ret function %swidenhigh_i16x8(i16) -> i32x4 { @@ -33,8 +33,8 @@ block0(v0: i16): } ; block0: -; dup v5.8h, w0 -; sxtl2 v0.4s, v5.8h +; dup v4.8h, w0 +; sxtl2 v0.4s, v4.8h ; ret function %swidenhigh_i32x4(i32) -> i64x2 { @@ -51,8 +51,8 @@ block0(v0: i32): } ; block0: -; dup v5.4s, w0 -; sxtl2 v0.2d, v5.4s +; dup v4.4s, w0 +; sxtl2 v0.2d, v4.4s ; ret function %swidenlow_i8x16(i8) -> i16x8 { @@ -69,8 +69,8 @@ block0(v0: i8): } ; block0: -; dup v5.16b, w0 -; sxtl v0.8h, v5.8b +; dup v4.16b, w0 +; sxtl v0.8h, v4.8b ; ret function %swidenlow_i16x8(i16) -> i32x4 { @@ -87,8 +87,8 @@ block0(v0: i16): } ; block0: -; dup v5.8h, w0 -; sxtl v0.4s, v5.4h +; dup v4.8h, w0 +; sxtl v0.4s, v4.4h ; ret function %swidenlow_i32x4(i32) -> i64x2 { @@ -105,6 +105,7 @@ block0(v0: i32): } ; block0: -; dup v5.4s, w0 -; sxtl v0.2d, v5.2s +; dup v4.4s, w0 +; sxtl v0.2d, v4.2s ; ret + diff --git a/cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif b/cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif index 0072a2b146..e5cb3e5cb6 100644 --- a/cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif +++ b/cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif @@ -80,8 +80,8 @@ block0: ; mov fp, sp ; sub sp, sp, #16 ; block0: -; mov x3, sp -; ldr q0, [x3] +; mov x2, sp +; ldr q0, [x2] ; add sp, sp, #16 ; ldp fp, lr, [sp], #16 ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/extend-op.clif b/cranelift/filetests/filetests/isa/aarch64/extend-op.clif index 76fc191425..2c1bf039d3 100644 --- a/cranelift/filetests/filetests/isa/aarch64/extend-op.clif +++ b/cranelift/filetests/filetests/isa/aarch64/extend-op.clif @@ -11,8 +11,8 @@ block0(v0: i8): } ; block0: -; sxtb x4, w0 -; add x0, x4, #42 +; sxtb x3, w0 +; add x0, x3, #42 ; ret function %f2(i8, i64) -> i64 { diff --git a/cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif b/cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif index 8dbaf3e1c8..d932bf4f06 100644 --- a/cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif +++ b/cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif @@ -9,8 +9,8 @@ block0(v0: i8): } ; block0: -; uxtb w3, w0 -; ucvtf s0, w3 +; uxtb w2, w0 +; ucvtf s0, w2 ; ret function u0:0(i8) -> f64 { @@ -20,8 +20,8 @@ block0(v0: i8): } ; block0: -; uxtb w3, w0 -; ucvtf d0, w3 +; uxtb w2, w0 +; ucvtf d0, w2 ; ret function u0:0(i16) -> f32 { @@ -31,8 +31,8 @@ block0(v0: i16): } ; block0: -; uxth w3, w0 -; ucvtf s0, w3 +; uxth w2, w0 +; ucvtf s0, w2 ; ret function u0:0(i16) -> f64 { @@ -42,8 +42,8 @@ block0(v0: i16): } ; block0: -; uxth w3, w0 -; ucvtf d0, w3 +; uxth w2, w0 +; ucvtf d0, w2 ; ret function u0:0(f32) -> i8 { @@ -55,12 +55,12 @@ block0(v0: f32): ; block0: ; fcmp s0, s0 ; b.vc 8 ; udf -; fmov s5, #-1 -; fcmp s0, s5 +; fmov s4, #-1 +; fcmp s0, s4 ; b.gt 8 ; udf -; movz x10, #17280, LSL #16 -; fmov s18, w10 -; fcmp s0, s18 +; movz x9, #17280, LSL #16 +; fmov s17, w9 +; fcmp s0, s17 ; b.lt 8 ; udf ; fcvtzu w0, s0 ; ret @@ -74,12 +74,12 @@ block0(v0: f64): ; block0: ; fcmp d0, d0 ; b.vc 8 ; udf -; fmov d5, #-1 -; fcmp d0, d5 +; fmov d4, #-1 +; fcmp d0, d4 ; b.gt 8 ; udf -; movz x10, #16496, LSL #48 -; fmov d18, x10 -; fcmp d0, d18 +; movz x9, #16496, LSL #48 +; fmov d17, x9 +; fcmp d0, d17 ; b.lt 8 ; udf ; fcvtzu w0, d0 ; ret @@ -93,12 +93,12 @@ block0(v0: f32): ; block0: ; fcmp s0, s0 ; b.vc 8 ; udf -; fmov s5, #-1 -; fcmp s0, s5 +; fmov s4, #-1 +; fcmp s0, s4 ; b.gt 8 ; udf -; movz x10, #18304, LSL #16 -; fmov s18, w10 -; fcmp s0, s18 +; movz x9, #18304, LSL #16 +; fmov s17, w9 +; fcmp s0, s17 ; b.lt 8 ; udf ; fcvtzu w0, s0 ; ret @@ -112,12 +112,12 @@ block0(v0: f64): ; block0: ; fcmp d0, d0 ; b.vc 8 ; udf -; fmov d5, #-1 -; fcmp d0, d5 +; fmov d4, #-1 +; fcmp d0, d4 ; b.gt 8 ; udf -; movz x10, #16624, LSL #48 -; fmov d18, x10 -; fcmp d0, d18 +; movz x9, #16624, LSL #48 +; fmov d17, x9 +; fcmp d0, d17 ; b.lt 8 ; udf ; fcvtzu w0, d0 ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/fcvt.clif b/cranelift/filetests/filetests/isa/aarch64/fcvt.clif index b15edcd89c..7e9c337ea0 100644 --- a/cranelift/filetests/filetests/isa/aarch64/fcvt.clif +++ b/cranelift/filetests/filetests/isa/aarch64/fcvt.clif @@ -8,8 +8,8 @@ block0(v0: i8): } ; block0: -; sxtb w3, w0 -; scvtf s0, w3 +; sxtb w2, w0 +; scvtf s0, w2 ; ret function %f2(i16) -> f32 { @@ -19,8 +19,8 @@ block0(v0: i16): } ; block0: -; sxth w3, w0 -; scvtf s0, w3 +; sxth w2, w0 +; scvtf s0, w2 ; ret function %f3(i32) -> f32 { @@ -50,8 +50,8 @@ block0(v0: i8): } ; block0: -; sxtb w3, w0 -; scvtf d0, w3 +; sxtb w2, w0 +; scvtf d0, w2 ; ret function %f6(i16) -> f64 { @@ -61,8 +61,8 @@ block0(v0: i16): } ; block0: -; sxth w3, w0 -; scvtf d0, w3 +; sxth w2, w0 +; scvtf d0, w2 ; ret function %f7(i32) -> f64 { @@ -92,8 +92,8 @@ block0(v0: i32x4): } ; block0: -; sxtl v3.2d, v0.2s -; scvtf v0.2d, v3.2d +; sxtl v2.2d, v0.2s +; scvtf v0.2d, v2.2d ; ret function %f10(i8, i16, i32, i64) -> f32 { @@ -109,15 +109,15 @@ block0(v0: i8, v1: i16, v2: i32, v3: i64): } ; block0: -; uxtb w13, w0 -; ucvtf s23, w13 -; uxth w13, w1 -; ucvtf s24, w13 -; ucvtf s22, w2 -; ucvtf s25, x3 -; fadd s23, s23, s24 -; fadd s22, s23, s22 -; fadd s0, s22, s25 +; uxtb w12, w0 +; ucvtf s22, w12 +; uxth w12, w1 +; ucvtf s23, w12 +; ucvtf s21, w2 +; ucvtf s24, x3 +; fadd s22, s22, s23 +; fadd s21, s22, s21 +; fadd s0, s21, s24 ; ret function %f11(i32x4) -> f64x2 { @@ -128,8 +128,8 @@ block0(v0: i32x4): } ; block0: -; uxtl v4.2d, v0.2s -; ucvtf v0.2d, v4.2d +; uxtl v3.2d, v0.2s +; ucvtf v0.2d, v3.2d ; ret function %f12(i32x4) -> f32x4 { @@ -151,12 +151,12 @@ block0(v0: f32): ; block0: ; fcmp s0, s0 ; b.vc 8 ; udf -; fmov s5, #-1 -; fcmp s0, s5 +; fmov s4, #-1 +; fcmp s0, s4 ; b.gt 8 ; udf -; movz x10, #20352, LSL #16 -; fmov s18, w10 -; fcmp s0, s18 +; movz x9, #20352, LSL #16 +; fmov s17, w9 +; fcmp s0, s17 ; b.lt 8 ; udf ; fcvtzu w0, s0 ; ret @@ -170,12 +170,12 @@ block0(v0: f32): ; block0: ; fcmp s0, s0 ; b.vc 8 ; udf -; fmov s5, #-1 -; fcmp s0, s5 +; fmov s4, #-1 +; fcmp s0, s4 ; b.gt 8 ; udf -; movz x10, #24448, LSL #16 -; fmov s18, w10 -; fcmp s0, s18 +; movz x9, #24448, LSL #16 +; fmov s17, w9 +; fcmp s0, s17 ; b.lt 8 ; udf ; fcvtzu x0, s0 ; ret @@ -189,12 +189,12 @@ block0(v0: f64): ; block0: ; fcmp d0, d0 ; b.vc 8 ; udf -; fmov d5, #-1 -; fcmp d0, d5 +; fmov d4, #-1 +; fcmp d0, d4 ; b.gt 8 ; udf -; movz x10, #16880, LSL #48 -; fmov d18, x10 -; fcmp d0, d18 +; movz x9, #16880, LSL #48 +; fmov d17, x9 +; fcmp d0, d17 ; b.lt 8 ; udf ; fcvtzu w0, d0 ; ret @@ -208,12 +208,12 @@ block0(v0: f64): ; block0: ; fcmp d0, d0 ; b.vc 8 ; udf -; fmov d5, #-1 -; fcmp d0, d5 +; fmov d4, #-1 +; fcmp d0, d4 ; b.gt 8 ; udf -; movz x10, #17392, LSL #48 -; fmov d18, x10 -; fcmp d0, d18 +; movz x9, #17392, LSL #48 +; fmov d17, x9 +; fcmp d0, d17 ; b.lt 8 ; udf ; fcvtzu x0, d0 ; ret @@ -267,13 +267,13 @@ block0(v0: f32): ; block0: ; fcmp s0, s0 ; b.vc 8 ; udf -; movz x6, #52992, LSL #16 -; fmov s6, w6 -; fcmp s0, s6 +; movz x5, #52992, LSL #16 +; fmov s5, w5 +; fcmp s0, s5 ; b.ge 8 ; udf -; movz x12, #20224, LSL #16 -; fmov s20, w12 -; fcmp s0, s20 +; movz x11, #20224, LSL #16 +; fmov s19, w11 +; fcmp s0, s19 ; b.lt 8 ; udf ; fcvtzs w0, s0 ; ret @@ -287,13 +287,13 @@ block0(v0: f32): ; block0: ; fcmp s0, s0 ; b.vc 8 ; udf -; movz x6, #57088, LSL #16 -; fmov s6, w6 -; fcmp s0, s6 +; movz x5, #57088, LSL #16 +; fmov s5, w5 +; fcmp s0, s5 ; b.ge 8 ; udf -; movz x12, #24320, LSL #16 -; fmov s20, w12 -; fcmp s0, s20 +; movz x11, #24320, LSL #16 +; fmov s19, w11 +; fcmp s0, s19 ; b.lt 8 ; udf ; fcvtzs x0, s0 ; ret @@ -307,12 +307,12 @@ block0(v0: f64): ; block0: ; fcmp d0, d0 ; b.vc 8 ; udf -; ldr d5, pc+8 ; b 12 ; data.f64 -2147483649 -; fcmp d0, d5 +; ldr d4, pc+8 ; b 12 ; data.f64 -2147483649 +; fcmp d0, d4 ; b.gt 8 ; udf -; movz x10, #16864, LSL #48 -; fmov d18, x10 -; fcmp d0, d18 +; movz x9, #16864, LSL #48 +; fmov d17, x9 +; fcmp d0, d17 ; b.lt 8 ; udf ; fcvtzs w0, d0 ; ret @@ -326,13 +326,13 @@ block0(v0: f64): ; block0: ; fcmp d0, d0 ; b.vc 8 ; udf -; movz x6, #50144, LSL #48 -; fmov d6, x6 -; fcmp d0, d6 +; movz x5, #50144, LSL #48 +; fmov d5, x5 +; fcmp d0, d5 ; b.ge 8 ; udf -; movz x12, #17376, LSL #48 -; fmov d20, x12 -; fcmp d0, d20 +; movz x11, #17376, LSL #48 +; fmov d19, x11 +; fcmp d0, d19 ; b.lt 8 ; udf ; fcvtzs x0, d0 ; ret @@ -404,10 +404,10 @@ block0(v0: f32): } ; block0: -; fcvtzu w3, s0 -; movz w5, #255 -; subs wzr, w3, w5 -; csel x0, x5, x3, hi +; fcvtzu w2, s0 +; movz w4, #255 +; subs wzr, w2, w4 +; csel x0, x4, x2, hi ; ret function %f32(f32) -> i8 { @@ -417,13 +417,13 @@ block0(v0: f32): } ; block0: -; fcvtzs w3, s0 -; movz w5, #127 -; movn x7, #127 -; subs wzr, w3, w5 -; csel x10, x5, x3, gt -; subs wzr, w10, w7 -; csel x0, x7, x10, lt +; fcvtzs w2, s0 +; movz w4, #127 +; movn x6, #127 +; subs wzr, w2, w4 +; csel x9, x4, x2, gt +; subs wzr, w9, w6 +; csel x0, x6, x9, lt ; ret function %f33(f32) -> i16 { @@ -433,10 +433,10 @@ block0(v0: f32): } ; block0: -; fcvtzu w3, s0 -; movz w5, #65535 -; subs wzr, w3, w5 -; csel x0, x5, x3, hi +; fcvtzu w2, s0 +; movz w4, #65535 +; subs wzr, w2, w4 +; csel x0, x4, x2, hi ; ret function %f34(f32) -> i16 { @@ -446,13 +446,13 @@ block0(v0: f32): } ; block0: -; fcvtzs w3, s0 -; movz w5, #32767 -; movn x7, #32767 -; subs wzr, w3, w5 -; csel x10, x5, x3, gt -; subs wzr, w10, w7 -; csel x0, x7, x10, lt +; fcvtzs w2, s0 +; movz w4, #32767 +; movn x6, #32767 +; subs wzr, w2, w4 +; csel x9, x4, x2, gt +; subs wzr, w9, w6 +; csel x0, x6, x9, lt ; ret function %f35(f64) -> i8 { @@ -462,10 +462,10 @@ block0(v0: f64): } ; block0: -; fcvtzu w3, d0 -; movz w5, #255 -; subs wzr, w3, w5 -; csel x0, x5, x3, hi +; fcvtzu w2, d0 +; movz w4, #255 +; subs wzr, w2, w4 +; csel x0, x4, x2, hi ; ret function %f36(f64) -> i8 { @@ -475,13 +475,13 @@ block0(v0: f64): } ; block0: -; fcvtzs w3, d0 -; movz w5, #127 -; movn x7, #127 -; subs wzr, w3, w5 -; csel x10, x5, x3, gt -; subs wzr, w10, w7 -; csel x0, x7, x10, lt +; fcvtzs w2, d0 +; movz w4, #127 +; movn x6, #127 +; subs wzr, w2, w4 +; csel x9, x4, x2, gt +; subs wzr, w9, w6 +; csel x0, x6, x9, lt ; ret function %f37(f64) -> i16 { @@ -491,10 +491,10 @@ block0(v0: f64): } ; block0: -; fcvtzu w3, d0 -; movz w5, #65535 -; subs wzr, w3, w5 -; csel x0, x5, x3, hi +; fcvtzu w2, d0 +; movz w4, #65535 +; subs wzr, w2, w4 +; csel x0, x4, x2, hi ; ret function %f38(f64) -> i16 { @@ -504,12 +504,12 @@ block0(v0: f64): } ; block0: -; fcvtzs w3, d0 -; movz w5, #32767 -; movn x7, #32767 -; subs wzr, w3, w5 -; csel x10, x5, x3, gt -; subs wzr, w10, w7 -; csel x0, x7, x10, lt +; fcvtzs w2, d0 +; movz w4, #32767 +; movn x6, #32767 +; subs wzr, w2, w4 +; csel x9, x4, x2, gt +; subs wzr, w9, w6 +; csel x0, x6, x9, lt ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/floating-point.clif b/cranelift/filetests/filetests/isa/aarch64/floating-point.clif index 3c6901ddf5..78201ebb93 100644 --- a/cranelift/filetests/filetests/isa/aarch64/floating-point.clif +++ b/cranelift/filetests/filetests/isa/aarch64/floating-point.clif @@ -309,8 +309,8 @@ block0(v0: f32, v1: f32): } ; block0: -; ushr v5.2s, v1.2s, #31 -; sli v0.2s, v0.2s, v5.2s, #31 +; ushr v4.2s, v1.2s, #31 +; sli v0.2s, v0.2s, v4.2s, #31 ; ret function %f32(f64, f64) -> f64 { @@ -320,8 +320,8 @@ block0(v0: f64, v1: f64): } ; block0: -; ushr d5, d1, #63 -; sli d0, d0, d5, #63 +; ushr d4, d1, #63 +; sli d0, d0, d4, #63 ; ret function %f33(f32) -> i32 { @@ -333,12 +333,12 @@ block0(v0: f32): ; block0: ; fcmp s0, s0 ; b.vc 8 ; udf -; fmov s5, #-1 -; fcmp s0, s5 +; fmov s4, #-1 +; fcmp s0, s4 ; b.gt 8 ; udf -; movz x10, #20352, LSL #16 -; fmov s18, w10 -; fcmp s0, s18 +; movz x9, #20352, LSL #16 +; fmov s17, w9 +; fcmp s0, s17 ; b.lt 8 ; udf ; fcvtzu w0, s0 ; ret @@ -352,13 +352,13 @@ block0(v0: f32): ; block0: ; fcmp s0, s0 ; b.vc 8 ; udf -; movz x6, #52992, LSL #16 -; fmov s6, w6 -; fcmp s0, s6 +; movz x5, #52992, LSL #16 +; fmov s5, w5 +; fcmp s0, s5 ; b.ge 8 ; udf -; movz x12, #20224, LSL #16 -; fmov s20, w12 -; fcmp s0, s20 +; movz x11, #20224, LSL #16 +; fmov s19, w11 +; fcmp s0, s19 ; b.lt 8 ; udf ; fcvtzs w0, s0 ; ret @@ -372,12 +372,12 @@ block0(v0: f32): ; block0: ; fcmp s0, s0 ; b.vc 8 ; udf -; fmov s5, #-1 -; fcmp s0, s5 +; fmov s4, #-1 +; fcmp s0, s4 ; b.gt 8 ; udf -; movz x10, #24448, LSL #16 -; fmov s18, w10 -; fcmp s0, s18 +; movz x9, #24448, LSL #16 +; fmov s17, w9 +; fcmp s0, s17 ; b.lt 8 ; udf ; fcvtzu x0, s0 ; ret @@ -391,13 +391,13 @@ block0(v0: f32): ; block0: ; fcmp s0, s0 ; b.vc 8 ; udf -; movz x6, #57088, LSL #16 -; fmov s6, w6 -; fcmp s0, s6 +; movz x5, #57088, LSL #16 +; fmov s5, w5 +; fcmp s0, s5 ; b.ge 8 ; udf -; movz x12, #24320, LSL #16 -; fmov s20, w12 -; fcmp s0, s20 +; movz x11, #24320, LSL #16 +; fmov s19, w11 +; fcmp s0, s19 ; b.lt 8 ; udf ; fcvtzs x0, s0 ; ret @@ -411,12 +411,12 @@ block0(v0: f64): ; block0: ; fcmp d0, d0 ; b.vc 8 ; udf -; fmov d5, #-1 -; fcmp d0, d5 +; fmov d4, #-1 +; fcmp d0, d4 ; b.gt 8 ; udf -; movz x10, #16880, LSL #48 -; fmov d18, x10 -; fcmp d0, d18 +; movz x9, #16880, LSL #48 +; fmov d17, x9 +; fcmp d0, d17 ; b.lt 8 ; udf ; fcvtzu w0, d0 ; ret @@ -430,12 +430,12 @@ block0(v0: f64): ; block0: ; fcmp d0, d0 ; b.vc 8 ; udf -; ldr d5, pc+8 ; b 12 ; data.f64 -2147483649 -; fcmp d0, d5 +; ldr d4, pc+8 ; b 12 ; data.f64 -2147483649 +; fcmp d0, d4 ; b.gt 8 ; udf -; movz x10, #16864, LSL #48 -; fmov d18, x10 -; fcmp d0, d18 +; movz x9, #16864, LSL #48 +; fmov d17, x9 +; fcmp d0, d17 ; b.lt 8 ; udf ; fcvtzs w0, d0 ; ret @@ -449,12 +449,12 @@ block0(v0: f64): ; block0: ; fcmp d0, d0 ; b.vc 8 ; udf -; fmov d5, #-1 -; fcmp d0, d5 +; fmov d4, #-1 +; fcmp d0, d4 ; b.gt 8 ; udf -; movz x10, #17392, LSL #48 -; fmov d18, x10 -; fcmp d0, d18 +; movz x9, #17392, LSL #48 +; fmov d17, x9 +; fcmp d0, d17 ; b.lt 8 ; udf ; fcvtzu x0, d0 ; ret @@ -468,13 +468,13 @@ block0(v0: f64): ; block0: ; fcmp d0, d0 ; b.vc 8 ; udf -; movz x6, #50144, LSL #48 -; fmov d6, x6 -; fcmp d0, d6 +; movz x5, #50144, LSL #48 +; fmov d5, x5 +; fcmp d0, d5 ; b.ge 8 ; udf -; movz x12, #17376, LSL #48 -; fmov d20, x12 -; fcmp d0, d20 +; movz x11, #17376, LSL #48 +; fmov d19, x11 +; fcmp d0, d19 ; b.lt 8 ; udf ; fcvtzs x0, d0 ; ret @@ -776,9 +776,9 @@ block0(v0: f32x4, v1: f32x4, v2: f32x4): } ; block0: -; mov v5.16b, v2.16b -; fmla v5.4s, v5.4s, v0.4s, v1.4s -; mov v0.16b, v5.16b +; mov v5.16b, v0.16b +; mov v0.16b, v2.16b +; fmla v0.4s, v0.4s, v5.4s, v1.4s ; ret function %f71(f32x2, f32x2, f32x2) -> f32x2 { @@ -788,9 +788,9 @@ block0(v0: f32x2, v1: f32x2, v2: f32x2): } ; block0: -; mov v5.16b, v2.16b -; fmla v5.2s, v5.2s, v0.2s, v1.2s -; mov v0.16b, v5.16b +; mov v5.16b, v0.16b +; mov v0.16b, v2.16b +; fmla v0.2s, v0.2s, v5.2s, v1.2s ; ret function %f72(f64x2, f64x2, f64x2) -> f64x2 { @@ -800,9 +800,9 @@ block0(v0: f64x2, v1: f64x2, v2: f64x2): } ; block0: -; mov v5.16b, v2.16b -; fmla v5.2d, v5.2d, v0.2d, v1.2d -; mov v0.16b, v5.16b +; mov v5.16b, v0.16b +; mov v0.16b, v2.16b +; fmla v0.2d, v0.2d, v5.2d, v1.2d ; ret function %f73(f32x2, f32x2) -> f32x2 { @@ -812,8 +812,8 @@ block0(v0: f32x2, v1: f32x2): } ; block0: -; ushr v5.2s, v1.2s, #31 -; sli v0.2s, v0.2s, v5.2s, #31 +; ushr v4.2s, v1.2s, #31 +; sli v0.2s, v0.2s, v4.2s, #31 ; ret function %f74(f32x4, f32x4) -> f32x4 { @@ -823,8 +823,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; ushr v5.4s, v1.4s, #31 -; sli v0.4s, v0.4s, v5.4s, #31 +; ushr v4.4s, v1.4s, #31 +; sli v0.4s, v0.4s, v4.4s, #31 ; ret function %f75(f64x2, f64x2) -> f64x2 { @@ -834,6 +834,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; ushr v5.2d, v1.2d, #63 -; sli v0.2d, v0.2d, v5.2d, #63 +; ushr v4.2d, v1.2d, #63 +; sli v0.2d, v0.2d, v4.2d, #63 ; ret + diff --git a/cranelift/filetests/filetests/isa/aarch64/heap_addr.clif b/cranelift/filetests/filetests/isa/aarch64/heap_addr.clif index 0c81d67829..f6b69d7c0c 100644 --- a/cranelift/filetests/filetests/isa/aarch64/heap_addr.clif +++ b/cranelift/filetests/filetests/isa/aarch64/heap_addr.clif @@ -14,16 +14,16 @@ block0(v0: i64, v1: i32): } ; block0: -; mov w9, w1 -; ldr x10, [x0] -; mov x10, x10 -; subs xzr, x9, x10 +; mov w8, w1 +; ldr x9, [x0] +; mov x9, x9 +; subs xzr, x8, x9 ; b.ls label1 ; b label2 ; block1: -; add x11, x0, x1, UXTW -; movz x12, #0 -; subs xzr, x9, x10 -; csel x0, x12, x11, hi +; add x10, x0, x1, UXTW +; movz x11, #0 +; subs xzr, x8, x9 +; csel x0, x11, x10, hi ; csdb ; ret ; block2: @@ -39,14 +39,14 @@ block0(v0: i64, v1: i32): } ; block0: -; mov w7, w1 -; subs xzr, x7, #65536 +; mov w6, w1 +; subs xzr, x6, #65536 ; b.ls label1 ; b label2 ; block1: -; add x9, x0, x1, UXTW -; movz x8, #0 -; subs xzr, x7, #65536 -; csel x0, x8, x9, hi +; add x8, x0, x1, UXTW +; movz x7, #0 +; subs xzr, x6, #65536 +; csel x0, x7, x8, hi ; csdb ; ret ; block2: diff --git a/cranelift/filetests/filetests/isa/aarch64/i128-bmask.clif b/cranelift/filetests/filetests/isa/aarch64/i128-bmask.clif index f6bff3ae4c..6e59708343 100644 --- a/cranelift/filetests/filetests/isa/aarch64/i128-bmask.clif +++ b/cranelift/filetests/filetests/isa/aarch64/i128-bmask.clif @@ -8,8 +8,8 @@ block0(v0: i128): } ; block0: -; orr x5, x0, x1 -; subs xzr, x5, #0 +; orr x3, x0, x1 +; subs xzr, x3, #0 ; csetm x1, ne ; mov x0, x1 ; ret @@ -21,8 +21,8 @@ block0(v0: i128): } ; block0: -; orr x4, x0, x1 -; subs xzr, x4, #0 +; orr x3, x0, x1 +; subs xzr, x3, #0 ; csetm x0, ne ; ret @@ -33,8 +33,8 @@ block0(v0: i128): } ; block0: -; orr x4, x0, x1 -; subs xzr, x4, #0 +; orr x3, x0, x1 +; subs xzr, x3, #0 ; csetm x0, ne ; ret @@ -45,8 +45,8 @@ block0(v0: i128): } ; block0: -; orr x4, x0, x1 -; subs xzr, x4, #0 +; orr x3, x0, x1 +; subs xzr, x3, #0 ; csetm x0, ne ; ret @@ -57,8 +57,8 @@ block0(v0: i128): } ; block0: -; orr x4, x0, x1 -; subs xzr, x4, #0 +; orr x3, x0, x1 +; subs xzr, x3, #0 ; csetm x0, ne ; ret @@ -93,8 +93,8 @@ block0(v0: i16): } ; block0: -; and w4, w0, #65535 -; subs wzr, w4, #0 +; and w2, w0, #65535 +; subs wzr, w2, #0 ; csetm x1, ne ; mov x0, x1 ; ret @@ -106,8 +106,8 @@ block0(v0: i8): } ; block0: -; and w4, w0, #255 -; subs wzr, w4, #0 +; and w2, w0, #255 +; subs wzr, w2, #0 ; csetm x1, ne ; mov x0, x1 ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/iabs.clif b/cranelift/filetests/filetests/isa/aarch64/iabs.clif index bfbf0e45b9..8c50cc4562 100644 --- a/cranelift/filetests/filetests/isa/aarch64/iabs.clif +++ b/cranelift/filetests/filetests/isa/aarch64/iabs.clif @@ -79,9 +79,9 @@ block0(v0: i8): } ; block0: -; sxtb w3, w0 -; subs wzr, w3, #0 -; csneg x0, x3, x3, gt +; sxtb w2, w0 +; subs wzr, w2, #0 +; csneg x0, x2, x2, gt ; ret function %f9(i16) -> i16 { @@ -91,9 +91,9 @@ block0(v0: i16): } ; block0: -; sxth w3, w0 -; subs wzr, w3, #0 -; csneg x0, x3, x3, gt +; sxth w2, w0 +; subs wzr, w2, #0 +; csneg x0, x2, x2, gt ; ret function %f10(i32) -> i32 { diff --git a/cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif b/cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif index c66f4c196a..6e2890034d 100644 --- a/cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif +++ b/cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif @@ -14,10 +14,10 @@ block0: } ; block0: -; movz x1, #56780 -; uxth w3, w1 -; movz x5, #56780 -; subs wzr, w3, w5, UXTH +; movz x0, #56780 +; uxth w2, w0 +; movz x4, #56780 +; subs wzr, w2, w4, UXTH ; cset x0, ne ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/jumptable.clif b/cranelift/filetests/filetests/isa/aarch64/jumptable.clif index 37f3798e46..e721c369aa 100644 --- a/cranelift/filetests/filetests/isa/aarch64/jumptable.clif +++ b/cranelift/filetests/filetests/isa/aarch64/jumptable.clif @@ -32,7 +32,7 @@ block5(v5: i32): ; block0: ; emit_island 44 ; subs wzr, w0, #3 -; b.hs label1 ; csel x1, xzr, x0, hs ; csdb ; adr x15, pc+16 ; ldrsw x1, [x15, x1, uxtw #2] ; add x15, x15, x1 ; br x15 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))] +; b.hs label1 ; csel x15, xzr, x0, hs ; csdb ; adr x14, pc+16 ; ldrsw x15, [x14, x15, uxtw #2] ; add x14, x14, x15 ; br x14 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))] ; block1: ; movz x5, #4 ; b label2 @@ -56,3 +56,4 @@ block5(v5: i32): ; block9: ; add w0, w0, w5 ; ret + diff --git a/cranelift/filetests/filetests/isa/aarch64/prologue.clif b/cranelift/filetests/filetests/isa/aarch64/prologue.clif index 519a3970f8..28845df1a1 100644 --- a/cranelift/filetests/filetests/isa/aarch64/prologue.clif +++ b/cranelift/filetests/filetests/isa/aarch64/prologue.clif @@ -82,6 +82,7 @@ block0(v0: f64): ; stp d10, d11, [sp, #-16]! ; stp d8, d9, [sp, #-16]! ; block0: +; fadd d23, d0, d0 ; fadd d24, d0, d0 ; fadd d25, d0, d0 ; fadd d26, d0, d0 @@ -104,7 +105,7 @@ block0(v0: f64): ; fadd d20, d0, d0 ; fadd d21, d0, d0 ; fadd d22, d0, d0 -; fadd d23, d0, d0 +; fadd d15, d0, d0 ; fadd d8, d0, d0 ; fadd d9, d0, d0 ; fadd d10, d0, d0 @@ -112,38 +113,37 @@ block0(v0: f64): ; fadd d12, d0, d0 ; fadd d13, d0, d0 ; fadd d14, d0, d0 -; fadd d15, d0, d0 -; fadd d24, d0, d24 -; fadd d25, d25, d26 -; fadd d26, d27, d28 -; fadd d27, d29, d30 -; fadd d28, d31, d1 -; fadd d29, d2, d3 -; fadd d30, d4, d5 -; fadd d31, d6, d7 -; fadd d0, d16, d17 -; fadd d1, d18, d19 -; fadd d2, d20, d21 -; fadd d3, d22, d23 -; fadd d4, d8, d9 -; fadd d5, d10, d11 -; fadd d6, d12, d13 -; fadd d7, d14, d15 +; fadd d23, d0, d23 ; fadd d24, d24, d25 ; fadd d25, d26, d27 ; fadd d26, d28, d29 ; fadd d27, d30, d31 -; fadd d28, d0, d1 -; fadd d29, d2, d3 -; fadd d30, d4, d5 -; fadd d31, d6, d7 -; fadd d24, d24, d25 -; fadd d25, d26, d27 -; fadd d26, d28, d29 -; fadd d27, d30, d31 -; fadd d24, d24, d25 -; fadd d25, d26, d27 -; fadd d0, d24, d25 +; fadd d28, d1, d2 +; fadd d29, d3, d4 +; fadd d30, d5, d6 +; fadd d31, d7, d16 +; fadd d0, d17, d18 +; fadd d1, d19, d20 +; fadd d2, d21, d22 +; fadd d3, d15, d8 +; fadd d4, d9, d10 +; fadd d5, d11, d12 +; fadd d6, d13, d14 +; fadd d23, d23, d24 +; fadd d24, d25, d26 +; fadd d25, d27, d28 +; fadd d26, d29, d30 +; fadd d27, d31, d0 +; fadd d28, d1, d2 +; fadd d29, d3, d4 +; fadd d30, d5, d6 +; fadd d23, d23, d24 +; fadd d24, d25, d26 +; fadd d25, d27, d28 +; fadd d26, d29, d30 +; fadd d23, d23, d24 +; fadd d24, d25, d26 +; fadd d0, d23, d24 ; ldp d8, d9, [sp], #16 ; ldp d10, d11, [sp], #16 ; ldp d12, d13, [sp], #16 @@ -200,9 +200,10 @@ block0(v0: i64): ; stp fp, lr, [sp, #-16]! ; mov fp, sp ; str x28, [sp, #-16]! -; stp x19, x21, [sp, #-16]! +; stp x21, x27, [sp, #-16]! ; block0: -; add x6, x0, x0 +; add x5, x0, x0 +; add x6, x0, x5 ; add x7, x0, x6 ; add x8, x0, x7 ; add x9, x0, x8 @@ -216,29 +217,29 @@ block0(v0: i64): ; add x2, x0, x1 ; add x3, x0, x2 ; add x4, x0, x3 -; add x5, x0, x4 -; add x28, x0, x5 +; add x27, x0, x4 +; add x28, x0, x27 ; add x21, x0, x28 -; add x19, x0, x21 -; add x6, x0, x6 -; add x7, x7, x8 -; add x8, x9, x10 -; add x9, x11, x12 -; add x10, x13, x14 -; add x11, x15, x1 -; add x12, x2, x3 -; add x13, x4, x5 -; add x14, x28, x21 -; add x6, x19, x6 -; add x7, x7, x8 -; add x8, x9, x10 -; add x9, x11, x12 -; add x10, x13, x14 +; add x5, x0, x5 ; add x6, x6, x7 ; add x7, x8, x9 -; add x6, x10, x6 -; add x0, x7, x6 -; ldp x19, x21, [sp], #16 +; add x8, x10, x11 +; add x9, x12, x13 +; add x10, x14, x15 +; add x11, x1, x2 +; add x12, x3, x4 +; add x13, x27, x28 +; add x5, x21, x5 +; add x6, x6, x7 +; add x7, x8, x9 +; add x8, x10, x11 +; add x9, x12, x13 +; add x5, x5, x6 +; add x6, x7, x8 +; add x5, x9, x5 +; add x0, x6, x5 +; ldp x21, x27, [sp], #16 ; ldr x28, [sp], #16 ; ldp fp, lr, [sp], #16 ; ret + diff --git a/cranelift/filetests/filetests/isa/aarch64/reftypes.clif b/cranelift/filetests/filetests/isa/aarch64/reftypes.clif index cc2dc49b48..3a90970bc2 100644 --- a/cranelift/filetests/filetests/isa/aarch64/reftypes.clif +++ b/cranelift/filetests/filetests/isa/aarch64/reftypes.clif @@ -69,28 +69,28 @@ block3(v7: r64, v8: r64): ; block0: ; str x0, [sp, #8] ; str x1, [sp, #16] -; ldr x3, 8 ; b 12 ; data TestCase(%f) + 0 -; blr x3 -; mov x2, sp -; ldr x9, [sp, #8] -; str x9, [x2] -; uxtb w3, w0 -; cbz x3, label1 ; b label3 +; ldr x1, 8 ; b 12 ; data TestCase(%f) + 0 +; blr x1 +; mov x15, sp +; ldr x6, [sp, #8] +; str x6, [x15] +; uxtb w0, w0 +; cbz x0, label1 ; b label3 ; block1: ; b label2 ; block2: -; mov x1, x9 +; mov x1, x6 ; ldr x0, [sp, #16] ; b label5 ; block3: ; b label4 ; block4: -; mov x0, x9 +; mov x0, x6 ; ldr x1, [sp, #16] ; b label5 ; block5: -; mov x4, sp -; ldr x2, [x4] +; mov x2, sp +; ldr x2, [x2] ; add sp, sp, #32 ; ldp fp, lr, [sp], #16 ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif b/cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif index 6009c9f92c..488a887ddd 100644 --- a/cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif +++ b/cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif @@ -13,28 +13,28 @@ block0(v0: i128, v1: i128): } ; block0: -; orr x7, xzr, #128 -; sub x9, x7, x2 -; lsr x11, x0, x2 -; lsr x13, x1, x2 -; orn w15, wzr, w2 -; lsl x3, x1, #1 -; lsl x3, x3, x15 -; orr x5, x11, x3 +; orr x5, xzr, #128 +; sub x7, x5, x2 +; lsr x9, x0, x2 +; lsr x11, x1, x2 +; orn w13, wzr, w2 +; lsl x15, x1, #1 +; lsl x3, x15, x13 +; orr x3, x9, x3 ; ands xzr, x2, #64 -; csel x8, x13, x5, ne -; csel x10, xzr, x13, ne -; lsl x12, x0, x9 -; lsl x14, x1, x9 -; orn w1, wzr, w9 -; lsr x2, x0, #1 -; lsr x4, x2, x1 -; orr x6, x14, x4 -; ands xzr, x9, #64 -; csel x9, xzr, x12, ne -; csel x11, x12, x6, ne -; orr x1, x10, x11 -; orr x0, x8, x9 +; csel x6, x11, x3, ne +; csel x8, xzr, x11, ne +; lsl x10, x0, x7 +; lsl x12, x1, x7 +; orn w14, wzr, w7 +; lsr x0, x0, #1 +; lsr x2, x0, x14 +; orr x4, x12, x2 +; ands xzr, x7, #64 +; csel x7, xzr, x10, ne +; csel x9, x10, x4, ne +; orr x1, x8, x9 +; orr x0, x6, x7 ; ret function %f0(i64, i64) -> i64 { @@ -64,13 +64,13 @@ block0(v0: i16, v1: i16): } ; block0: -; uxth w4, w0 -; and w6, w1, #15 -; sub w8, w6, #16 -; sub w10, wzr, w8 -; lsr w12, w4, w6 -; lsl w14, w4, w10 -; orr w0, w14, w12 +; uxth w3, w0 +; and w5, w1, #15 +; sub w7, w5, #16 +; sub w9, wzr, w7 +; lsr w11, w3, w5 +; lsl w13, w3, w9 +; orr w0, w13, w11 ; ret function %f3(i8, i8) -> i8 { @@ -80,13 +80,13 @@ block0(v0: i8, v1: i8): } ; block0: -; uxtb w4, w0 -; and w6, w1, #7 -; sub w8, w6, #8 -; sub w10, wzr, w8 -; lsr w12, w4, w6 -; lsl w14, w4, w10 -; orr w0, w14, w12 +; uxtb w3, w0 +; and w5, w1, #7 +; sub w7, w5, #8 +; sub w9, wzr, w7 +; lsr w11, w3, w5 +; lsl w13, w3, w9 +; orr w0, w13, w11 ; ret function %i128_rotl(i128, i128) -> i128 { @@ -96,28 +96,28 @@ block0(v0: i128, v1: i128): } ; block0: -; orr x7, xzr, #128 -; sub x9, x7, x2 -; lsl x11, x0, x2 -; lsl x13, x1, x2 -; orn w15, wzr, w2 -; lsr x3, x0, #1 -; lsr x3, x3, x15 -; orr x5, x13, x3 +; orr x5, xzr, #128 +; sub x7, x5, x2 +; lsl x9, x0, x2 +; lsl x11, x1, x2 +; orn w13, wzr, w2 +; lsr x15, x0, #1 +; lsr x3, x15, x13 +; orr x3, x11, x3 ; ands xzr, x2, #64 -; csel x8, xzr, x11, ne -; csel x10, x11, x5, ne -; lsr x12, x0, x9 -; lsr x14, x1, x9 -; orn w0, wzr, w9 -; lsl x2, x1, #1 -; lsl x4, x2, x0 -; orr x6, x12, x4 -; ands xzr, x9, #64 -; csel x9, x14, x6, ne -; csel x11, xzr, x14, ne -; orr x0, x8, x9 -; orr x1, x10, x11 +; csel x6, xzr, x9, ne +; csel x8, x9, x3, ne +; lsr x10, x0, x7 +; lsr x12, x1, x7 +; orn w14, wzr, w7 +; lsl x0, x1, #1 +; lsl x2, x0, x14 +; orr x4, x10, x2 +; ands xzr, x7, #64 +; csel x7, x12, x4, ne +; csel x9, xzr, x12, ne +; orr x0, x6, x7 +; orr x1, x8, x9 ; ret function %f4(i64, i64) -> i64 { @@ -127,8 +127,8 @@ block0(v0: i64, v1: i64): } ; block0: -; sub x4, xzr, x1 -; ror x0, x0, x4 +; sub x3, xzr, x1 +; ror x0, x0, x3 ; ret function %f5(i32, i32) -> i32 { @@ -138,8 +138,8 @@ block0(v0: i32, v1: i32): } ; block0: -; sub w4, wzr, w1 -; ror w0, w0, w4 +; sub w3, wzr, w1 +; ror w0, w0, w3 ; ret function %f6(i16, i16) -> i16 { @@ -149,14 +149,14 @@ block0(v0: i16, v1: i16): } ; block0: -; sub w4, wzr, w1 -; uxth w6, w0 -; and w8, w4, #15 -; sub w10, w8, #16 -; sub w12, wzr, w10 -; lsr w14, w6, w8 -; lsl w0, w6, w12 -; orr w0, w0, w14 +; sub w3, wzr, w1 +; uxth w5, w0 +; and w7, w3, #15 +; sub w9, w7, #16 +; sub w11, wzr, w9 +; lsr w13, w5, w7 +; lsl w15, w5, w11 +; orr w0, w15, w13 ; ret function %f7(i8, i8) -> i8 { @@ -166,14 +166,14 @@ block0(v0: i8, v1: i8): } ; block0: -; sub w4, wzr, w1 -; uxtb w6, w0 -; and w8, w4, #7 -; sub w10, w8, #8 -; sub w12, wzr, w10 -; lsr w14, w6, w8 -; lsl w0, w6, w12 -; orr w0, w0, w14 +; sub w3, wzr, w1 +; uxtb w5, w0 +; and w7, w3, #7 +; sub w9, w7, #8 +; sub w11, wzr, w9 +; lsr w13, w5, w7 +; lsl w15, w5, w11 +; orr w0, w15, w13 ; ret function %f8(i64, i64) -> i64 { @@ -203,9 +203,9 @@ block0(v0: i16, v1: i16): } ; block0: -; uxth w4, w0 -; and w6, w1, #15 -; lsr w0, w4, w6 +; uxth w3, w0 +; and w5, w1, #15 +; lsr w0, w3, w5 ; ret function %f11(i8, i8) -> i8 { @@ -215,9 +215,9 @@ block0(v0: i8, v1: i8): } ; block0: -; uxtb w4, w0 -; and w6, w1, #7 -; lsr w0, w4, w6 +; uxtb w3, w0 +; and w5, w1, #7 +; lsr w0, w3, w5 ; ret function %f12(i64, i64) -> i64 { @@ -247,8 +247,8 @@ block0(v0: i16, v1: i16): } ; block0: -; and w4, w1, #15 -; lsl w0, w0, w4 +; and w3, w1, #15 +; lsl w0, w0, w3 ; ret function %f15(i8, i8) -> i8 { @@ -258,8 +258,8 @@ block0(v0: i8, v1: i8): } ; block0: -; and w4, w1, #7 -; lsl w0, w0, w4 +; and w3, w1, #7 +; lsl w0, w0, w3 ; ret function %f16(i64, i64) -> i64 { @@ -289,9 +289,9 @@ block0(v0: i16, v1: i16): } ; block0: -; sxth w4, w0 -; and w6, w1, #15 -; asr w0, w4, w6 +; sxth w3, w0 +; and w5, w1, #15 +; asr w0, w3, w5 ; ret function %f19(i8, i8) -> i8 { @@ -301,9 +301,9 @@ block0(v0: i8, v1: i8): } ; block0: -; sxtb w4, w0 -; and w6, w1, #7 -; asr w0, w4, w6 +; sxtb w3, w0 +; and w5, w1, #7 +; asr w0, w3, w5 ; ret function %f20(i64) -> i64 { @@ -347,10 +347,10 @@ block0(v0: i16): } ; block0: -; uxth w3, w0 -; lsr w5, w3, #6 -; lsl w7, w3, #10 -; orr w0, w7, w5 +; uxth w2, w0 +; lsr w4, w2, #6 +; lsl w6, w2, #10 +; orr w0, w6, w4 ; ret function %f24(i8) -> i8 { @@ -361,10 +361,10 @@ block0(v0: i8): } ; block0: -; uxtb w3, w0 -; lsr w5, w3, #5 -; lsl w7, w3, #3 -; orr w0, w7, w5 +; uxtb w2, w0 +; lsr w4, w2, #5 +; lsl w6, w2, #3 +; orr w0, w6, w4 ; ret function %f25(i64) -> i64 { diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif b/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif index 31d6ec910f..bae5a4f5c4 100644 --- a/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif +++ b/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif @@ -69,13 +69,13 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; movz x5, #1 -; dup v5.2d, x5 -; orr v16.16b, v0.16b, v1.16b -; and v18.16b, v16.16b, v5.16b -; ushr v20.2d, v0.2d, #1 -; ushr v22.2d, v1.2d, #1 -; add v24.2d, v20.2d, v22.2d -; add v0.2d, v18.2d, v24.2d +; movz x4, #1 +; dup v4.2d, x4 +; orr v7.16b, v0.16b, v1.16b +; and v17.16b, v7.16b, v4.16b +; ushr v19.2d, v0.2d, #1 +; ushr v21.2d, v1.2d, #1 +; add v23.2d, v19.2d, v21.2d +; add v0.2d, v17.2d, v23.2d ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif b/cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif index 49f36e18a6..06344fc59e 100644 --- a/cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif +++ b/cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif @@ -103,9 +103,9 @@ block0: ; block0: ; movi v0.16b, #0 +; movi v3.16b, #0 ; movi v4.16b, #0 -; movi v5.16b, #0 -; bsl v0.16b, v0.16b, v4.16b, v5.16b +; bsl v0.16b, v0.16b, v3.16b, v4.16b ; ret function %vselect_i16x8(i16x8, i16x8, i16x8) -> i16x8 { @@ -146,10 +146,10 @@ block0(v0: i32): } ; block0: -; ldr q6, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100 -; and w4, w0, #7 -; dup v7.16b, w4 -; sshl v0.16b, v6.16b, v7.16b +; ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100 +; and w3, w0, #7 +; dup v6.16b, w3 +; sshl v0.16b, v5.16b, v6.16b ; ret function %ushr_i8x16_imm() -> i8x16 { @@ -161,12 +161,12 @@ block0: } ; block0: -; ldr q6, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100 -; movz x2, #1 -; and w4, w2, #7 -; sub x6, xzr, x4 -; dup v16.16b, w6 -; ushl v0.16b, v6.16b, v16.16b +; ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100 +; movz x1, #1 +; and w3, w1, #7 +; sub x5, xzr, x3 +; dup v7.16b, w5 +; ushl v0.16b, v5.16b, v7.16b ; ret function %sshr_i8x16(i32) -> i8x16 { @@ -177,11 +177,11 @@ block0(v0: i32): } ; block0: -; ldr q7, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100 -; and w4, w0, #7 -; sub x6, xzr, x4 -; dup v16.16b, w6 -; sshl v0.16b, v7.16b, v16.16b +; ldr q6, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100 +; and w3, w0, #7 +; sub x5, xzr, x3 +; dup v7.16b, w5 +; sshl v0.16b, v6.16b, v7.16b ; ret function %sshr_i8x16_imm(i8x16, i32) -> i8x16 { @@ -191,11 +191,11 @@ block0(v0: i8x16, v1: i32): } ; block0: -; movz x4, #3 -; and w6, w4, #7 -; sub x8, xzr, x6 -; dup v18.16b, w8 -; sshl v0.16b, v0.16b, v18.16b +; movz x3, #3 +; and w5, w3, #7 +; sub x7, xzr, x5 +; dup v17.16b, w7 +; sshl v0.16b, v0.16b, v17.16b ; ret function %sshr_i64x2(i64x2, i32) -> i64x2 { @@ -205,9 +205,9 @@ block0(v0: i64x2, v1: i32): } ; block0: -; and w4, w0, #63 -; sub x6, xzr, x4 -; dup v16.2d, x6 -; sshl v0.2d, v0.2d, v16.2d +; and w3, w0, #63 +; sub x5, xzr, x3 +; dup v7.2d, x5 +; sshl v0.2d, v0.2d, v7.2d ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif b/cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif index 05b98bb643..03a609296f 100644 --- a/cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif +++ b/cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif @@ -9,8 +9,8 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; cmeq v4.4s, v0.4s, v1.4s -; mvn v0.16b, v4.16b +; cmeq v3.4s, v0.4s, v1.4s +; mvn v0.16b, v3.16b ; ret function %icmp_ugt_i32x4(i32x4, i32x4) -> i32x4 { diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif b/cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif index f1a8e1a0bf..3f725cae58 100644 --- a/cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif +++ b/cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif @@ -14,10 +14,10 @@ block0: ; block0: ; movi v30.16b, #0 -; movz x5, #1 -; fmov s31, w5 -; ldr q4, pc+8 ; b 20 ; data.f128 0x11000000000000000000000000000000 -; tbl v0.16b, { v30.16b, v31.16b }, v4.16b +; movz x4, #1 +; fmov s31, w4 +; ldr q3, pc+8 ; b 20 ; data.f128 0x11000000000000000000000000000000 +; tbl v0.16b, { v30.16b, v31.16b }, v3.16b ; ret function %shuffle_same_ssa_value() -> i8x16 { @@ -28,11 +28,11 @@ block0: } ; block0: -; movz x4, #1 -; fmov s31, w4 -; ldr q3, pc+8 ; b 20 ; data.f128 0x13000000000000000000000000000000 +; movz x3, #1 +; fmov s31, w3 +; ldr q2, pc+8 ; b 20 ; data.f128 0x13000000000000000000000000000000 ; mov v30.16b, v31.16b -; tbl v0.16b, { v30.16b, v31.16b }, v3.16b +; tbl v0.16b, { v30.16b, v31.16b }, v2.16b ; ret function %swizzle() -> i8x16 { @@ -44,9 +44,9 @@ block0: } ; block0: +; ldr q2, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100 ; ldr q3, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100 -; ldr q4, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100 -; tbl v0.16b, { v3.16b }, v4.16b +; tbl v0.16b, { v2.16b }, v3.16b ; ret function %splat_i8(i8) -> i8x16 { @@ -98,8 +98,8 @@ block0(v0: i64): } ; block0: -; ldr w4, [x0] -; fmov s0, w4 +; ldr w3, [x0] +; fmov s0, w3 ; ret function %load32_zero_int(i32) -> i32x4 { diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif b/cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif index 654fcb2bef..4a2486bffe 100644 --- a/cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif +++ b/cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif @@ -19,9 +19,9 @@ block0(v0: i32x4): } ; block0: -; umaxp v3.4s, v0.4s, v0.4s -; mov x5, v3.d[0] -; subs xzr, x5, #0 +; umaxp v2.4s, v0.4s, v0.4s +; mov x4, v2.d[0] +; subs xzr, x4, #0 ; cset x0, ne ; ret @@ -32,9 +32,9 @@ block0(v0: i64x2): } ; block0: -; cmeq v3.2d, v0.2d, #0 -; addp v5.2d, v3.2d, v3.2d -; fcmp d5, d5 +; cmeq v2.2d, v0.2d, #0 +; addp v4.2d, v2.2d, v2.2d +; fcmp d4, d4 ; cset x0, eq ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-narrow.clif b/cranelift/filetests/filetests/isa/aarch64/simd-narrow.clif index b5940c2d64..cd0e38d70d 100644 --- a/cranelift/filetests/filetests/isa/aarch64/simd-narrow.clif +++ b/cranelift/filetests/filetests/isa/aarch64/simd-narrow.clif @@ -9,9 +9,9 @@ block0(v0: i16x4, v1: i16x4): } ; block0: -; mov v4.16b, v0.16b -; mov v4.d[1], v4.d[1], v1.d[0] -; sqxtn v0.8b, v4.8h +; mov v3.16b, v0.16b +; mov v3.d[1], v3.d[1], v1.d[0] +; sqxtn v0.8b, v3.8h ; ret function %snarrow_i16x8(i16x8, i16x8) -> i8x16 { @@ -32,9 +32,9 @@ block0(v0: i32x2, v1: i32x2): } ; block0: -; mov v4.16b, v0.16b -; mov v4.d[1], v4.d[1], v1.d[0] -; sqxtn v0.4h, v4.4s +; mov v3.16b, v0.16b +; mov v3.d[1], v3.d[1], v1.d[0] +; sqxtn v0.4h, v3.4s ; ret function %snarrow_i32x4(i32x4, i32x4) -> i16x8 { @@ -66,9 +66,9 @@ block0(v0: i16x4, v1: i16x4): } ; block0: -; mov v4.16b, v0.16b -; mov v4.d[1], v4.d[1], v1.d[0] -; sqxtun v0.8b, v4.8h +; mov v3.16b, v0.16b +; mov v3.d[1], v3.d[1], v1.d[0] +; sqxtun v0.8b, v3.8h ; ret function %unarrow_i16x8(i16x8, i16x8) -> i8x16 { @@ -89,9 +89,9 @@ block0(v0: i32x2, v1: i32x2): } ; block0: -; mov v4.16b, v0.16b -; mov v4.d[1], v4.d[1], v1.d[0] -; sqxtun v0.4h, v4.4s +; mov v3.16b, v0.16b +; mov v3.d[1], v3.d[1], v1.d[0] +; sqxtun v0.4h, v3.4s ; ret function %unarrow_i32x4(i32x4, i32x4) -> i16x8 { @@ -123,9 +123,9 @@ block0(v0: i16x4, v1: i16x4): } ; block0: -; mov v4.16b, v0.16b -; mov v4.d[1], v4.d[1], v1.d[0] -; uqxtn v0.8b, v4.8h +; mov v3.16b, v0.16b +; mov v3.d[1], v3.d[1], v1.d[0] +; uqxtn v0.8b, v3.8h ; ret function %uunarrow_i16x8(i16x8, i16x8) -> i8x16 { @@ -146,9 +146,9 @@ block0(v0: i32x2, v1: i32x2): } ; block0: -; mov v4.16b, v0.16b -; mov v4.d[1], v4.d[1], v1.d[0] -; uqxtn v0.4h, v4.4s +; mov v3.16b, v0.16b +; mov v3.d[1], v3.d[1], v1.d[0] +; uqxtn v0.4h, v3.4s ; ret function %uunarrow_i32x4(i32x4, i32x4) -> i16x8 { diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif b/cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif index 19a9f0455d..459ca00063 100644 --- a/cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif +++ b/cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif @@ -9,9 +9,9 @@ block0(v0: i8x8): } ; block0: -; uminv b3, v0.8b -; mov x5, v3.d[0] -; subs xzr, x5, #0 +; uminv b2, v0.8b +; mov x4, v2.d[0] +; subs xzr, x4, #0 ; cset x0, ne ; ret @@ -22,9 +22,9 @@ block0(v0: i8x16): } ; block0: -; uminv b3, v0.16b -; mov x5, v3.d[0] -; subs xzr, x5, #0 +; uminv b2, v0.16b +; mov x4, v2.d[0] +; subs xzr, x4, #0 ; cset x0, ne ; ret @@ -35,9 +35,9 @@ block0(v0: i16x4): } ; block0: -; uminv h3, v0.4h -; mov x5, v3.d[0] -; subs xzr, x5, #0 +; uminv h2, v0.4h +; mov x4, v2.d[0] +; subs xzr, x4, #0 ; cset x0, ne ; ret @@ -48,9 +48,9 @@ block0(v0: i16x8): } ; block0: -; uminv h3, v0.8h -; mov x5, v3.d[0] -; subs xzr, x5, #0 +; uminv h2, v0.8h +; mov x4, v2.d[0] +; subs xzr, x4, #0 ; cset x0, ne ; ret @@ -61,9 +61,9 @@ block0(v0: i32x2): } ; block0: -; mov x3, v0.d[0] -; subs xzr, xzr, x3, LSR 32 -; ccmp w3, #0, #nZcv, ne +; mov x2, v0.d[0] +; subs xzr, xzr, x2, LSR 32 +; ccmp w2, #0, #nZcv, ne ; cset x0, ne ; ret @@ -74,9 +74,9 @@ block0(v0: i32x4): } ; block0: -; uminv s3, v0.4s -; mov x5, v3.d[0] -; subs xzr, x5, #0 +; uminv s2, v0.4s +; mov x4, v2.d[0] +; subs xzr, x4, #0 ; cset x0, ne ; ret @@ -87,9 +87,9 @@ block0(v0: i64x2): } ; block0: -; cmeq v3.2d, v0.2d, #0 -; addp v5.2d, v3.2d, v3.2d -; fcmp d5, d5 +; cmeq v2.2d, v0.2d, #0 +; addp v4.2d, v2.2d, v2.2d +; fcmp d4, d4 ; cset x0, eq ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/simd.clif b/cranelift/filetests/filetests/isa/aarch64/simd.clif index 087a26269a..b21ec65304 100644 --- a/cranelift/filetests/filetests/isa/aarch64/simd.clif +++ b/cranelift/filetests/filetests/isa/aarch64/simd.clif @@ -10,9 +10,9 @@ block0: } ; block0: -; movz x2, #1 -; movk x2, x2, #1, LSL #48 -; dup v0.2d, x2 +; movz x1, #1 +; movk x1, x1, #1, LSL #48 +; dup v0.2d, x1 ; ret function %f2() -> i16x8 { @@ -24,8 +24,8 @@ block0: } ; block0: -; movz x2, #42679 -; dup v0.8h, w2 +; movz x1, #42679 +; dup v0.8h, w1 ; ret function %f4(i32, i8x16, i8x16) -> i8x16 { @@ -74,9 +74,9 @@ block0(v0: i64, v1: i64): } ; block0: -; ldrb w7, [x0] +; ldrb w5, [x0] ; ld1r { v0.16b }, [x1] -; dup v1.16b, w7 +; dup v1.16b, w5 ; ret function %f8(i64, i64) -> i8x16, i8x16 { @@ -88,9 +88,9 @@ block0(v0: i64, v1: i64): } ; block0: -; ldrb w7, [x0] -; dup v0.16b, w7 -; dup v1.16b, w7 +; ldrb w5, [x0] +; dup v0.16b, w5 +; dup v1.16b, w5 ; ret function %f9() -> i32x2 { diff --git a/cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif b/cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif index 388168c5e2..3d4e953559 100644 --- a/cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif +++ b/cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif @@ -10,9 +10,9 @@ block0: } ; block0: -; movz x1, #1 -; movk x1, x1, #1, LSL #48 -; fmov d0, x1 +; movz x0, #1 +; movk x0, x0, #1, LSL #48 +; fmov d0, x0 ; ret function %f2() -> i32x4 { @@ -23,8 +23,8 @@ block0: } ; block0: -; movz x1, #42679 -; fmov s0, w1 +; movz x0, #42679 +; fmov s0, w0 ; ret function %f3() -> f32x4 { @@ -35,8 +35,8 @@ block0: } ; block0: -; fmov s1, #1 -; fmov s0, s1 +; fmov s0, #1 +; fmov s0, s0 ; ret function %f4() -> f64x2 { @@ -47,7 +47,7 @@ block0: } ; block0: -; fmov d1, #1 -; fmov d0, d1 +; fmov d0, #1 +; fmov d0, d0 ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/stack.clif b/cranelift/filetests/filetests/isa/aarch64/stack.clif index 0969956a8f..1bb9a205a2 100644 --- a/cranelift/filetests/filetests/isa/aarch64/stack.clif +++ b/cranelift/filetests/filetests/isa/aarch64/stack.clif @@ -53,8 +53,8 @@ block0: ; mov fp, sp ; sub sp, sp, #16 ; block0: -; mov x2, sp -; ldr x0, [x2] +; mov x1, sp +; ldr x0, [x1] ; add sp, sp, #16 ; ldp fp, lr, [sp], #16 ; ret @@ -74,8 +74,8 @@ block0: ; movk w16, w16, #1, LSL #16 ; sub sp, sp, x16, UXTX ; block0: -; mov x2, sp -; ldr x0, [x2] +; mov x1, sp +; ldr x0, [x1] ; movz w16, #34480 ; movk w16, w16, #1, LSL #16 ; add sp, sp, x16, UXTX @@ -284,142 +284,142 @@ block0(v0: i8): ; sub sp, sp, #1152 ; block0: ; str x0, [sp, #1000] -; movz x8, #2 -; add x11, x8, #1 -; str x11, [sp, #1136] -; movz x8, #4 -; add x12, x8, #3 -; str x12, [sp, #1128] -; movz x8, #6 -; add x13, x8, #5 -; str x13, [sp, #1120] -; movz x8, #8 -; add x14, x8, #7 -; str x14, [sp, #1112] -; movz x8, #10 -; add x15, x8, #9 -; str x15, [sp, #1104] -; movz x8, #12 -; add x1, x8, #11 -; str x1, [sp, #1096] -; movz x8, #14 -; add x2, x8, #13 -; str x2, [sp, #1088] -; movz x8, #16 -; add x3, x8, #15 -; str x3, [sp, #1080] -; movz x8, #18 -; add x4, x8, #17 -; str x4, [sp, #1072] -; movz x8, #20 -; add x5, x8, #19 -; str x5, [sp, #1064] -; movz x8, #22 -; add x6, x8, #21 -; str x6, [sp, #1056] -; movz x8, #24 -; add x7, x8, #23 -; str x7, [sp, #1048] -; movz x8, #26 -; add x8, x8, #25 -; str x8, [sp, #1040] -; movz x8, #28 -; add x9, x8, #27 -; str x9, [sp, #1032] -; movz x8, #30 -; add x26, x8, #29 -; str x26, [sp, #1024] -; movz x8, #32 -; add x27, x8, #31 -; str x27, [sp, #1016] -; movz x8, #34 -; add x28, x8, #33 -; movz x8, #36 -; add x21, x8, #35 -; str x21, [sp, #1008] -; movz x8, #38 -; add x21, x8, #37 -; movz x8, #30 -; add x19, x8, #39 -; movz x8, #32 -; add x20, x8, #31 -; movz x8, #34 -; add x22, x8, #33 -; movz x8, #36 -; add x23, x8, #35 -; movz x8, #38 -; add x24, x8, #37 -; movz x8, #30 -; add x25, x8, #39 -; movz x8, #32 -; add x0, x8, #31 -; movz x8, #34 -; add x10, x8, #33 -; movz x8, #36 -; add x11, x8, #35 -; movz x8, #38 -; add x12, x8, #37 -; movz x8, #30 -; add x13, x8, #39 -; movz x8, #32 -; add x14, x8, #31 -; movz x8, #34 -; add x15, x8, #33 -; movz x8, #36 -; add x1, x8, #35 -; movz x8, #38 -; add x2, x8, #37 -; ldr x3, [sp, #1136] -; add x3, x3, #39 -; ldr x5, [sp, #1120] -; ldr x4, [sp, #1128] -; add x4, x4, x5 -; ldr x5, [sp, #1104] -; ldr x8, [sp, #1112] -; add x5, x8, x5 -; ldr x6, [sp, #1088] -; ldr x7, [sp, #1096] -; add x6, x7, x6 -; ldr x7, [sp, #1072] -; ldr x8, [sp, #1080] -; add x7, x8, x7 -; ldr x9, [sp, #1056] -; ldr x8, [sp, #1064] +; movz x6, #2 +; add x9, x6, #1 +; str x9, [sp, #1136] +; movz x6, #4 +; add x10, x6, #3 +; str x10, [sp, #1128] +; movz x6, #6 +; add x11, x6, #5 +; str x11, [sp, #1120] +; movz x6, #8 +; add x12, x6, #7 +; str x12, [sp, #1112] +; movz x6, #10 +; add x13, x6, #9 +; str x13, [sp, #1104] +; movz x6, #12 +; add x14, x6, #11 +; str x14, [sp, #1096] +; movz x6, #14 +; add x15, x6, #13 +; str x15, [sp, #1088] +; movz x6, #16 +; add x1, x6, #15 +; str x1, [sp, #1080] +; movz x6, #18 +; add x2, x6, #17 +; str x2, [sp, #1072] +; movz x6, #20 +; add x3, x6, #19 +; str x3, [sp, #1064] +; movz x6, #22 +; add x4, x6, #21 +; str x4, [sp, #1056] +; movz x6, #24 +; add x5, x6, #23 +; str x5, [sp, #1048] +; movz x6, #26 +; add x6, x6, #25 +; str x6, [sp, #1040] +; movz x6, #28 +; add x7, x6, #27 +; str x7, [sp, #1032] +; movz x6, #30 +; add x24, x6, #29 +; str x24, [sp, #1024] +; movz x6, #32 +; add x25, x6, #31 +; str x25, [sp, #1016] +; movz x6, #34 +; add x26, x6, #33 +; movz x6, #36 +; add x27, x6, #35 +; str x27, [sp, #1008] +; movz x6, #38 +; add x27, x6, #37 +; movz x6, #30 +; add x28, x6, #39 +; movz x6, #32 +; add x21, x6, #31 +; movz x6, #34 +; add x19, x6, #33 +; movz x6, #36 +; add x20, x6, #35 +; movz x6, #38 +; add x22, x6, #37 +; movz x6, #30 +; add x23, x6, #39 +; movz x6, #32 +; add x0, x6, #31 +; movz x6, #34 +; add x8, x6, #33 +; movz x6, #36 +; add x9, x6, #35 +; movz x6, #38 +; add x10, x6, #37 +; movz x6, #30 +; add x11, x6, #39 +; movz x6, #32 +; add x12, x6, #31 +; movz x6, #34 +; add x13, x6, #33 +; movz x6, #36 +; add x14, x6, #35 +; movz x6, #38 +; add x15, x6, #37 +; ldr x1, [sp, #1136] +; add x1, x1, #39 +; ldr x3, [sp, #1120] +; ldr x2, [sp, #1128] +; add x2, x2, x3 +; ldr x3, [sp, #1104] +; ldr x6, [sp, #1112] +; add x3, x6, x3 +; ldr x4, [sp, #1088] +; ldr x5, [sp, #1096] +; add x4, x5, x4 +; ldr x5, [sp, #1072] +; ldr x6, [sp, #1080] +; add x5, x6, x5 +; ldr x7, [sp, #1056] +; ldr x6, [sp, #1064] +; add x6, x6, x7 +; ldr x7, [sp, #1040] +; ldr x24, [sp, #1048] +; add x7, x24, x7 +; ldr x24, [sp, #1024] +; ldr x25, [sp, #1032] +; add x24, x25, x24 +; ldr x25, [sp, #1016] +; add x25, x25, x26 +; ldr x26, [sp, #1008] +; add x26, x26, x27 +; add x27, x28, x21 +; add x28, x19, x20 +; add x23, x22, x23 +; add x8, x0, x8 +; add x9, x9, x10 +; add x10, x11, x12 +; add x11, x13, x14 +; add x12, x15, x1 +; add x13, x2, x3 +; add x14, x4, x5 +; add x7, x6, x7 +; add x15, x24, x25 +; add x0, x26, x27 +; add x1, x28, x23 ; add x8, x8, x9 -; ldr x9, [sp, #1040] -; ldr x26, [sp, #1048] -; add x9, x26, x9 -; ldr x26, [sp, #1024] -; ldr x27, [sp, #1032] -; add x26, x27, x26 -; ldr x27, [sp, #1016] -; add x27, x27, x28 -; ldr x28, [sp, #1008] -; add x28, x28, x21 -; add x21, x19, x20 -; add x19, x22, x23 -; add x25, x24, x25 -; add x10, x0, x10 -; add x11, x11, x12 -; add x12, x13, x14 -; add x13, x15, x1 -; add x14, x2, x3 -; add x15, x4, x5 -; add x0, x6, x7 -; add x9, x8, x9 -; add x1, x26, x27 -; add x2, x28, x21 -; add x3, x19, x25 -; add x10, x10, x11 -; add x11, x12, x13 -; add x12, x14, x15 -; add x9, x0, x9 -; add x13, x1, x2 -; add x10, x3, x10 -; add x11, x11, x12 -; add x9, x9, x13 -; add x10, x10, x11 -; add x1, x9, x10 +; add x9, x10, x11 +; add x10, x12, x13 +; add x7, x14, x7 +; add x11, x15, x0 +; add x8, x1, x8 +; add x9, x9, x10 +; add x7, x7, x11 +; add x8, x8, x9 +; add x1, x7, x8 ; ldr x0, [sp, #1000] ; add sp, sp, #1152 ; ldp x19, x20, [sp], #16 @@ -502,8 +502,8 @@ block0: ; mov fp, sp ; sub sp, sp, #16 ; block0: -; mov x5, sp -; ldp x0, x1, [x5] +; mov x3, sp +; ldp x0, x1, [x3] ; add sp, sp, #16 ; ldp fp, lr, [sp], #16 ; ret @@ -521,8 +521,8 @@ block0: ; mov fp, sp ; sub sp, sp, #32 ; block0: -; add x5, sp, #32 -; ldp x0, x1, [x5] +; add x3, sp, #32 +; ldp x0, x1, [x3] ; add sp, sp, #32 ; ldp fp, lr, [sp], #16 ; ret @@ -542,8 +542,8 @@ block0: ; movk w16, w16, #1, LSL #16 ; sub sp, sp, x16, UXTX ; block0: -; mov x5, sp -; ldp x0, x1, [x5] +; mov x3, sp +; ldp x0, x1, [x3] ; movz w16, #34480 ; movk w16, w16, #1, LSL #16 ; add sp, sp, x16, UXTX diff --git a/cranelift/filetests/filetests/isa/aarch64/tls-elf-gd.clif b/cranelift/filetests/filetests/isa/aarch64/tls-elf-gd.clif index d31db4da88..db46c96b30 100644 --- a/cranelift/filetests/filetests/isa/aarch64/tls-elf-gd.clif +++ b/cranelift/filetests/filetests/isa/aarch64/tls-elf-gd.clif @@ -12,22 +12,21 @@ block0(v0: i32): ; stp fp, lr, [sp, #-16]! ; mov fp, sp -; str x25, [sp, #-16]! +; str x24, [sp, #-16]! ; stp d14, d15, [sp, #-16]! ; stp d12, d13, [sp, #-16]! ; stp d10, d11, [sp, #-16]! ; stp d8, d9, [sp, #-16]! ; block0: -; mov x25, x0 +; mov x24, x0 ; elf_tls_get_addr x0, userextname0 -; mov x7, x25 ; mov x1, x0 -; mov x0, x7 +; mov x0, x24 ; ldp d8, d9, [sp], #16 ; ldp d10, d11, [sp], #16 ; ldp d12, d13, [sp], #16 ; ldp d14, d15, [sp], #16 -; ldr x25, [sp], #16 +; ldr x24, [sp], #16 ; ldp fp, lr, [sp], #16 ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif b/cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif index 4d4ad4d876..e3bfc8a784 100644 --- a/cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif +++ b/cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif @@ -9,8 +9,8 @@ block0(v0: i32): } ; block0: -; movz x3, #127 -; adds w0, w0, w3 +; movz x2, #127 +; adds w0, w0, w2 ; b.lo 8 ; udf ; ret @@ -22,8 +22,8 @@ block0(v0: i32): } ; block0: -; movz x3, #127 -; adds w0, w3, w0 +; movz x2, #127 +; adds w0, w2, w0 ; b.lo 8 ; udf ; ret @@ -46,8 +46,8 @@ block0(v0: i64): } ; block0: -; movz x3, #127 -; adds x0, x0, x3 +; movz x2, #127 +; adds x0, x0, x2 ; b.lo 8 ; udf ; ret @@ -59,8 +59,8 @@ block0(v0: i64): } ; block0: -; movz x3, #127 -; adds x0, x3, x0 +; movz x2, #127 +; adds x0, x2, x0 ; b.lo 8 ; udf ; ret diff --git a/cranelift/filetests/filetests/isa/aarch64/vhigh_bits.clif b/cranelift/filetests/filetests/isa/aarch64/vhigh_bits.clif index 75fc84903b..8f603a919e 100644 --- a/cranelift/filetests/filetests/isa/aarch64/vhigh_bits.clif +++ b/cranelift/filetests/filetests/isa/aarch64/vhigh_bits.clif @@ -8,17 +8,17 @@ block0(v0: i8x16): } ; block0: -; sshr v3.16b, v0.16b, #7 -; movz x6, #513 -; movk x6, x6, #2052, LSL #16 -; movk x6, x6, #8208, LSL #32 -; movk x6, x6, #32832, LSL #48 -; dup v17.2d, x6 -; and v20.16b, v3.16b, v17.16b -; ext v22.16b, v20.16b, v20.16b, #8 -; zip1 v24.16b, v20.16b, v22.16b -; addv h26, v24.8h -; umov w0, v26.h[0] +; sshr v2.16b, v0.16b, #7 +; movz x5, #513 +; movk x5, x5, #2052, LSL #16 +; movk x5, x5, #8208, LSL #32 +; movk x5, x5, #32832, LSL #48 +; dup v16.2d, x5 +; and v19.16b, v2.16b, v16.16b +; ext v21.16b, v19.16b, v19.16b, #8 +; zip1 v23.16b, v19.16b, v21.16b +; addv h25, v23.8h +; umov w0, v25.h[0] ; ret function %f2(i8x16) -> i16 { @@ -28,17 +28,17 @@ block0(v0: i8x16): } ; block0: -; sshr v3.16b, v0.16b, #7 -; movz x6, #513 -; movk x6, x6, #2052, LSL #16 -; movk x6, x6, #8208, LSL #32 -; movk x6, x6, #32832, LSL #48 -; dup v17.2d, x6 -; and v20.16b, v3.16b, v17.16b -; ext v22.16b, v20.16b, v20.16b, #8 -; zip1 v24.16b, v20.16b, v22.16b -; addv h26, v24.8h -; umov w0, v26.h[0] +; sshr v2.16b, v0.16b, #7 +; movz x5, #513 +; movk x5, x5, #2052, LSL #16 +; movk x5, x5, #8208, LSL #32 +; movk x5, x5, #32832, LSL #48 +; dup v16.2d, x5 +; and v19.16b, v2.16b, v16.16b +; ext v21.16b, v19.16b, v19.16b, #8 +; zip1 v23.16b, v19.16b, v21.16b +; addv h25, v23.8h +; umov w0, v25.h[0] ; ret function %f3(i16x8) -> i8 { @@ -48,11 +48,11 @@ block0(v0: i16x8): } ; block0: -; sshr v3.8h, v0.8h, #15 -; ldr q5, pc+8 ; b 20 ; data.f128 0x00800040002000100008000400020001 -; and v7.16b, v3.16b, v5.16b -; addv h17, v7.8h -; umov w0, v17.h[0] +; sshr v2.8h, v0.8h, #15 +; ldr q4, pc+8 ; b 20 ; data.f128 0x00800040002000100008000400020001 +; and v6.16b, v2.16b, v4.16b +; addv h16, v6.8h +; umov w0, v16.h[0] ; ret function %f4(i32x4) -> i8 { @@ -62,11 +62,11 @@ block0(v0: i32x4): } ; block0: -; sshr v3.4s, v0.4s, #31 -; ldr q5, pc+8 ; b 20 ; data.f128 0x00000008000000040000000200000001 -; and v7.16b, v3.16b, v5.16b -; addv s17, v7.4s -; mov w0, v17.s[0] +; sshr v2.4s, v0.4s, #31 +; ldr q4, pc+8 ; b 20 ; data.f128 0x00000008000000040000000200000001 +; and v6.16b, v2.16b, v4.16b +; addv s16, v6.4s +; mov w0, v16.s[0] ; ret function %f5(i64x2) -> i8 { @@ -76,10 +76,10 @@ block0(v0: i64x2): } ; block0: -; mov x3, v0.d[1] -; mov x5, v0.d[0] -; lsr x7, x3, #63 -; lsr x9, x5, #63 -; add x0, x9, x7, LSL 1 +; mov x2, v0.d[1] +; mov x4, v0.d[0] +; lsr x6, x2, #63 +; lsr x8, x4, #63 +; add x0, x8, x6, LSL 1 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/amodes.clif b/cranelift/filetests/filetests/isa/riscv64/amodes.clif index 3ec876a999..5b8e5a1aff 100644 --- a/cranelift/filetests/filetests/isa/riscv64/amodes.clif +++ b/cranelift/filetests/filetests/isa/riscv64/amodes.clif @@ -11,9 +11,9 @@ block0(v0: i64, v1: i32): } ; block0: -; sext.w a3,a1 -; add a3,a0,a3 -; lw a0,0(a3) +; sext.w a2,a1 +; add a2,a0,a2 +; lw a0,0(a2) ; ret function %f6(i64, i32) -> i32 { @@ -25,9 +25,9 @@ block0(v0: i64, v1: i32): } ; block0: -; sext.w a3,a1 -; add a3,a3,a0 -; lw a0,0(a3) +; sext.w a2,a1 +; add a2,a2,a0 +; lw a0,0(a2) ; ret function %f7(i32, i32) -> i32 { @@ -40,10 +40,10 @@ block0(v0: i32, v1: i32): } ; block0: -; uext.w a4,a0 -; uext.w a5,a1 -; add a4,a4,a5 -; lw a0,0(a4) +; uext.w a3,a0 +; uext.w a4,a1 +; add a3,a3,a4 +; lw a0,0(a3) ; ret function %f8(i64, i32) -> i32 { @@ -58,11 +58,11 @@ block0(v0: i64, v1: i32): } ; block0: -; sext.w a5,a1 -; addi a5,a5,32 -; add a5,a5,a0 -; add a5,a5,a5 -; lw a0,4(a5) +; sext.w a4,a1 +; addi a4,a4,32 +; add a4,a4,a0 +; add a4,a4,a4 +; lw a0,4(a4) ; ret function %f9(i64, i64, i64) -> i32 { @@ -76,10 +76,10 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; add a5,a0,a1 -; add a5,a5,a2 -; addi a5,a5,48 -; lw a0,0(a5) +; add a4,a0,a1 +; add a4,a4,a2 +; addi a4,a4,48 +; lw a0,0(a4) ; ret function %f10(i64, i64, i64) -> i32 { @@ -93,12 +93,12 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; add a6,a0,a1 -; add a6,a6,a2 -; lui a5,1 -; addi a5,a5,4 -; add t3,a6,a5 -; lw a0,0(t3) +; add a5,a0,a1 +; add a5,a5,a2 +; lui a4,1 +; addi a4,a4,4 +; add a7,a5,a4 +; lw a0,0(a7) ; ret function %f10() -> i32 { @@ -109,8 +109,8 @@ block0: } ; block0: -; li t1,1234 -; lw a0,0(t1) +; li t0,1234 +; lw a0,0(t0) ; ret function %f11(i64) -> i32 { @@ -123,8 +123,8 @@ block0(v0: i64): ; block0: ; lui a1,2048 -; add a3,a0,a1 -; lw a0,0(a3) +; add a2,a0,a1 +; lw a0,0(a2) ; ret function %f12(i64) -> i32 { @@ -136,8 +136,8 @@ block0(v0: i64): } ; block0: -; addi a1,a0,-4 -; lw a0,0(a1) +; addi a0,a0,-4 +; lw a0,0(a0) ; ret function %f13(i64) -> i32 { @@ -151,8 +151,8 @@ block0(v0: i64): ; block0: ; lui a1,244141 ; addi a1,a1,2560 -; add a4,a0,a1 -; lw a0,0(a4) +; add a3,a0,a1 +; lw a0,0(a3) ; ret function %f14(i32) -> i32 { @@ -163,8 +163,8 @@ block0(v0: i32): } ; block0: -; sext.w a1,a0 -; lw a0,0(a1) +; sext.w a0,a0 +; lw a0,0(a0) ; ret function %f15(i32, i32) -> i32 { @@ -177,10 +177,10 @@ block0(v0: i32, v1: i32): } ; block0: -; sext.w a4,a0 -; sext.w a5,a1 -; add a4,a4,a5 -; lw a0,0(a4) +; sext.w a3,a0 +; sext.w a4,a1 +; add a3,a3,a4 +; lw a0,0(a3) ; ret function %f18(i64, i64, i64) -> i32 { @@ -192,10 +192,10 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; lui a3,1048575 -; addi a3,a3,4094 -; uext.w a6,a3 -; lh a0,0(a6) +; lui a2,1048575 +; addi a2,a2,4094 +; uext.w a5,a2 +; lh a0,0(a5) ; ret function %f19(i64, i64, i64) -> i32 { @@ -207,10 +207,10 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; lui a3,1 -; addi a3,a3,2 -; uext.w a6,a3 -; lh a0,0(a6) +; lui a2,1 +; addi a2,a2,2 +; uext.w a5,a2 +; lh a0,0(a5) ; ret function %f20(i64, i64, i64) -> i32 { @@ -222,10 +222,10 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; lui a3,1048575 -; addi a3,a3,4094 -; sext.w a6,a3 -; lh a0,0(a6) +; lui a2,1048575 +; addi a2,a2,4094 +; sext.w a5,a2 +; lh a0,0(a5) ; ret function %f21(i64, i64, i64) -> i32 { @@ -237,10 +237,10 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; lui a3,1 -; addi a3,a3,2 -; sext.w a6,a3 -; lh a0,0(a6) +; lui a2,1 +; addi a2,a2,2 +; sext.w a5,a2 +; lh a0,0(a5) ; ret function %i128(i64) -> i128 { @@ -251,13 +251,13 @@ block0(v0: i64): } ; block0: -; ld a1,0(a0) -; mv a3,a1 +; ld t2,0(a0) +; mv a2,t2 ; ld a1,8(a0) -; mv a5,a3 -; sd a5,0(a0) +; mv a3,a2 +; sd a3,0(a0) ; sd a1,8(a0) -; mv a0,a3 +; mv a0,a2 ; ret function %i128_imm_offset(i64) -> i128 { @@ -268,13 +268,13 @@ block0(v0: i64): } ; block0: -; ld a1,16(a0) -; mv a3,a1 +; ld t2,16(a0) +; mv a2,t2 ; ld a1,24(a0) -; mv a5,a3 -; sd a5,16(a0) +; mv a3,a2 +; sd a3,16(a0) ; sd a1,24(a0) -; mv a0,a3 +; mv a0,a2 ; ret function %i128_imm_offset_large(i64) -> i128 { @@ -285,13 +285,13 @@ block0(v0: i64): } ; block0: -; ld a1,504(a0) -; mv a3,a1 +; ld t2,504(a0) +; mv a2,t2 ; ld a1,512(a0) -; mv a5,a3 -; sd a5,504(a0) +; mv a3,a2 +; sd a3,504(a0) ; sd a1,512(a0) -; mv a0,a3 +; mv a0,a2 ; ret function %i128_imm_offset_negative_large(i64) -> i128 { @@ -302,13 +302,13 @@ block0(v0: i64): } ; block0: -; ld a1,-512(a0) -; mv a3,a1 +; ld t2,-512(a0) +; mv a2,t2 ; ld a1,-504(a0) -; mv a5,a3 -; sd a5,-512(a0) +; mv a3,a2 +; sd a3,-512(a0) ; sd a1,-504(a0) -; mv a0,a3 +; mv a0,a2 ; ret function %i128_add_offset(i64) -> i128 { @@ -320,11 +320,11 @@ block0(v0: i64): } ; block0: -; addi a3,a0,32 -; ld a0,0(a3) -; ld a1,8(a3) -; sd a0,0(a3) -; sd a1,8(a3) +; addi a2,a0,32 +; ld a0,0(a2) +; ld a1,8(a2) +; sd a0,0(a2) +; sd a1,8(a2) ; ret function %i128_32bit_sextend_simple(i32) -> i128 { @@ -336,11 +336,11 @@ block0(v0: i32): } ; block0: -; sext.w a3,a0 -; ld a0,0(a3) -; ld a1,8(a3) -; sd a0,0(a3) -; sd a1,8(a3) +; sext.w a2,a0 +; ld a0,0(a2) +; ld a1,8(a2) +; sd a0,0(a2) +; sd a1,8(a2) ; ret function %i128_32bit_sextend(i64, i32) -> i128 { @@ -354,12 +354,12 @@ block0(v0: i64, v1: i32): } ; block0: -; sext.w a6,a1 -; add a6,a0,a6 -; addi a6,a6,24 -; ld a0,0(a6) -; ld a1,8(a6) -; sd a0,0(a6) -; sd a1,8(a6) +; sext.w a4,a1 +; add a4,a0,a4 +; addi a4,a4,24 +; ld a0,0(a4) +; ld a1,8(a4) +; sd a0,0(a4) +; sd a1,8(a4) ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif b/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif index 17c25a713c..0fca02ced9 100644 --- a/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif +++ b/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif @@ -61,11 +61,11 @@ block0(v0: i64, v1: i64): ; block0: ; li a2,-1 ; li a3,1 -; slli a5,a3,63 -; eq a7,a2,a1##ty=i64 -; eq t4,a5,a0##ty=i64 -; and t1,a7,t4 -; trap_if t1,int_ovf +; slli a4,a3,63 +; eq a6,a2,a1##ty=i64 +; eq t3,a4,a0##ty=i64 +; and t0,a6,t3 +; trap_if t0,int_ovf ; trap_ifc int_divz##(zero eq a1) ; div a0,a0,a1 ; ret @@ -78,18 +78,18 @@ block0(v0: i64): } ; block0: +; li t2,2 +; li a1,-1 +; li a3,1 +; slli a5,a3,63 +; eq a7,a1,t2##ty=i64 +; eq t4,a5,a0##ty=i64 +; and t1,a7,t4 +; trap_if t1,int_ovf ; li a1,2 -; li a2,-1 -; li a4,1 -; slli a6,a4,63 -; eq t3,a2,a1##ty=i64 -; eq t0,a6,a0##ty=i64 -; and t2,t3,t0 -; trap_if t2,int_ovf -; li a2,2 -; trap_ifc int_divz##(zero eq a2) -; li a5,2 -; div a0,a0,a5 +; trap_ifc int_divz##(zero eq a1) +; li a4,2 +; div a0,a0,a4 ; ret function %f8(i64, i64) -> i64 { @@ -111,10 +111,10 @@ block0(v0: i64): } ; block0: -; li a1,2 -; trap_ifc int_divz##(zero eq a1) -; li a3,2 -; divu a0,a0,a3 +; li t2,2 +; trap_ifc int_divz##(zero eq t2) +; li a2,2 +; divu a0,a0,a2 ; ret function %f10(i64, i64) -> i64 { @@ -146,18 +146,18 @@ block0(v0: i32, v1: i32): } ; block0: -; sext.w a2,a0 -; sext.w a3,a1 -; li a5,-1 -; li a7,1 -; slli t4,a7,63 -; slli t1,a2,32 -; eq a0,a5,a3##ty=i32 -; eq a4,t4,t1##ty=i32 -; and a4,a0,a4 -; trap_if a4,int_ovf -; trap_ifc int_divz##(zero eq a3) -; divw a0,a2,a3 +; sext.w a0,a0 +; sext.w a2,a1 +; li a4,-1 +; li a6,1 +; slli t3,a6,63 +; slli t0,a0,32 +; eq t2,a4,a2##ty=i32 +; eq a1,t3,t0##ty=i32 +; and a3,t2,a1 +; trap_if a3,int_ovf +; trap_ifc int_divz##(zero eq a2) +; divw a0,a0,a2 ; ret function %f13(i32) -> i32 { @@ -168,19 +168,19 @@ block0(v0: i32): } ; block0: -; sext.w a0,a0 -; li a2,2 -; sext.w a4,a2 -; li a6,-1 -; li t3,1 -; slli t0,t3,63 -; slli t2,a0,32 -; eq a1,a6,a4##ty=i32 -; eq a3,t0,t2##ty=i32 -; and a5,a1,a3 -; trap_if a5,int_ovf -; trap_ifc int_divz##(zero eq a4) -; divw a0,a0,a4 +; sext.w t2,a0 +; li a1,2 +; sext.w a3,a1 +; li a5,-1 +; li a7,1 +; slli t4,a7,63 +; slli t1,t2,32 +; eq a0,a5,a3##ty=i32 +; eq a2,t4,t1##ty=i32 +; and a4,a0,a2 +; trap_if a4,int_ovf +; trap_ifc int_divz##(zero eq a3) +; divw a0,t2,a3 ; ret function %f14(i32, i32) -> i32 { @@ -190,10 +190,11 @@ block0(v0: i32, v1: i32): } ; block0: -; uext.w a1,a1 -; trap_ifc int_divz##(zero eq a1) -; uext.w a4,a0 -; divuw a0,a4,a1 +; mv a5,a0 +; uext.w a0,a1 +; trap_ifc int_divz##(zero eq a0) +; uext.w a3,a5 +; divuw a0,a3,a0 ; ret function %f15(i32) -> i32 { @@ -204,11 +205,11 @@ block0(v0: i32): } ; block0: -; li a1,2 -; uext.w a2,a1 -; trap_ifc int_divz##(zero eq a2) -; uext.w a5,a0 -; divuw a0,a5,a2 +; li t2,2 +; uext.w a1,t2 +; trap_ifc int_divz##(zero eq a1) +; uext.w a4,a0 +; divuw a0,a4,a1 ; ret function %f16(i32, i32) -> i32 { @@ -340,8 +341,8 @@ block0(v0: i32): } ; block0: -; li a1,-1 -; subw a0,a0,a1 +; li t2,-1 +; subw a0,a0,t2 ; ret function %f28(i64) -> i64 { @@ -352,8 +353,8 @@ block0(v0: i64): } ; block0: -; li a1,-1 -; sub a0,a0,a1 +; li t2,-1 +; sub a0,a0,t2 ; ret function %f29(i64) -> i64 { @@ -364,8 +365,8 @@ block0(v0: i64): } ; block0: -; li a0,1 -; sub a0,zero,a0 +; li t2,1 +; sub a0,zero,t2 ; ret function %add_i128(i128, i128) -> i128 { @@ -376,9 +377,9 @@ block0(v0: i128, v1: i128): ; block0: ; add a0,a0,a2 -; sltu a6,a0,a2 -; add t3,a1,a3 -; add a1,t3,a6 +; sltu a4,a0,a2 +; add a6,a1,a3 +; add a1,a6,a4 ; ret function %sub_i128(i128, i128) -> i128 { @@ -388,12 +389,12 @@ block0(v0: i128, v1: i128): } ; block0: -; sub a4,a0,a2 -; mv t4,a4 -; sltu a6,a0,t4 -; sub t3,a1,a3 -; sub a1,t3,a6 -; mv a0,a4 +; sub a2,a0,a2 +; mv a7,a2 +; sltu a4,a0,a7 +; mv a0,a7 +; sub a6,a1,a3 +; sub a1,a6,a4 ; ret function %add_mul_2(i32, i32, i32) -> i32 { @@ -404,8 +405,8 @@ block0(v0: i32, v1: i32, v2: i32): } ; block0: -; mulw a3,a1,a2 -; addw a0,a3,a0 +; mulw a2,a1,a2 +; addw a0,a2,a0 ; ret function %msub_i32(i32, i32, i32) -> i32 { @@ -416,8 +417,8 @@ block0(v0: i32, v1: i32, v2: i32): } ; block0: -; mulw a3,a1,a2 -; subw a0,a0,a3 +; mulw a2,a1,a2 +; subw a0,a0,a2 ; ret function %msub_i64(i64, i64, i64) -> i64 { @@ -428,8 +429,8 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; mul a3,a1,a2 -; sub a0,a0,a3 +; mul a2,a1,a2 +; sub a0,a0,a2 ; ret function %imul_sub_i32(i32, i32, i32) -> i32 { @@ -440,8 +441,8 @@ block0(v0: i32, v1: i32, v2: i32): } ; block0: -; mulw a3,a1,a2 -; subw a0,a3,a0 +; mulw a2,a1,a2 +; subw a0,a2,a0 ; ret function %imul_sub_i64(i64, i64, i64) -> i64 { @@ -452,8 +453,8 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; mul a3,a1,a2 -; sub a0,a3,a0 +; mul a2,a1,a2 +; sub a0,a2,a0 ; ret function %srem_const (i64) -> i64 { @@ -464,10 +465,10 @@ block0(v0: i64): } ; block0: -; li a1,2 -; trap_ifc int_divz##(zero eq a1) -; li a3,2 -; rem a0,a0,a3 +; li t2,2 +; trap_ifc int_divz##(zero eq t2) +; li a2,2 +; rem a0,a0,a2 ; ret function %urem_const (i64) -> i64 { @@ -478,10 +479,10 @@ block0(v0: i64): } ; block0: -; li a1,2 -; trap_ifc int_divz##(zero eq a1) -; li a3,2 -; remu a0,a0,a3 +; li t2,2 +; trap_ifc int_divz##(zero eq t2) +; li a2,2 +; remu a0,a0,a2 ; ret function %sdiv_minus_one(i64) -> i64 { @@ -492,17 +493,17 @@ block0(v0: i64): } ; block0: +; li t2,-1 ; li a1,-1 -; li a2,-1 -; li a4,1 -; slli a6,a4,63 -; eq t3,a2,a1##ty=i64 -; eq t0,a6,a0##ty=i64 -; and t2,t3,t0 -; trap_if t2,int_ovf -; li a2,-1 -; trap_ifc int_divz##(zero eq a2) -; li a5,-1 -; div a0,a0,a5 +; li a3,1 +; slli a5,a3,63 +; eq a7,a1,t2##ty=i64 +; eq t4,a5,a0##ty=i64 +; and t1,a7,t4 +; trap_if t1,int_ovf +; li a1,-1 +; trap_ifc int_divz##(zero eq a1) +; li a4,-1 +; div a0,a0,a4 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/atomic_load.clif b/cranelift/filetests/filetests/isa/riscv64/atomic_load.clif index 0cfc646b70..d242816c1c 100644 --- a/cranelift/filetests/filetests/isa/riscv64/atomic_load.clif +++ b/cranelift/filetests/filetests/isa/riscv64/atomic_load.clif @@ -30,7 +30,7 @@ block0(v0: i64): } ; block0: -; atomic_load.i32 a1,(a0) -; uext.w a0,a1 +; atomic_load.i32 a0,(a0) +; uext.w a0,a0 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/bitops.clif b/cranelift/filetests/filetests/isa/riscv64/bitops.clif index 650e23e88f..8115cf5522 100644 --- a/cranelift/filetests/filetests/isa/riscv64/bitops.clif +++ b/cranelift/filetests/filetests/isa/riscv64/bitops.clif @@ -9,8 +9,8 @@ block0(v0: i8): } ; block0: -; brev8 a4,a0##tmp=a3 tmp2=a1 step=a2 ty=i8 -; mv a0,a4 +; mv a3,a0 +; brev8 a0,a3##tmp=t2 tmp2=a2 step=a1 ty=i8 ; ret function %a(i16) -> i16 { @@ -20,10 +20,10 @@ block0(v0: i16): } ; block0: -; mv t3,a0 -; brev8 a3,t3##tmp=a0 tmp2=a1 step=a2 ty=i16 -; rev8 a5,a3##step=a7 tmp=a6 -; srli a0,a5,48 +; mv a7,a0 +; brev8 a2,a7##tmp=t2 tmp2=a0 step=a1 ty=i16 +; rev8 a4,a2##step=a6 tmp=a5 +; srli a0,a4,48 ; ret function %a(i32) -> i32 { @@ -33,10 +33,10 @@ block0(v0: i32): } ; block0: -; mv t3,a0 -; brev8 a3,t3##tmp=a0 tmp2=a1 step=a2 ty=i32 -; rev8 a5,a3##step=a7 tmp=a6 -; srli a0,a5,32 +; mv a7,a0 +; brev8 a2,a7##tmp=t2 tmp2=a0 step=a1 ty=i32 +; rev8 a4,a2##step=a6 tmp=a5 +; srli a0,a4,32 ; ret function %a(i64) -> i64 { @@ -46,8 +46,9 @@ block0(v0: i64): } ; block0: -; rev8 a3,a0##step=a2 tmp=a1 -; brev8 a0,a3##tmp=a4 tmp2=a5 step=a6 ty=i64 +; mv a6,a0 +; rev8 t2,a6##step=a1 tmp=a0 +; brev8 a0,t2##tmp=a3 tmp2=a4 step=a5 ty=i64 ; ret function %a(i128) -> i128 { @@ -57,11 +58,13 @@ block0(v0: i128): } ; block0: -; rev8 a2,a0##step=a4 tmp=a3 -; brev8 t4,a2##tmp=a6 tmp2=a7 step=t3 ty=i64 -; rev8 t1,a1##step=a0 tmp=t2 -; brev8 a0,t1##tmp=a2 tmp2=a3 step=a4 ty=i64 -; mv a1,t4 +; mv a3,a0 +; mv a7,a1 +; rev8 a0,a3##step=a2 tmp=a1 +; brev8 a1,a0##tmp=a4 tmp2=a5 step=a6 ty=i64 +; mv a3,a7 +; rev8 t4,a3##step=t1 tmp=t0 +; brev8 a0,t4##tmp=a4 tmp2=a3 step=a2 ty=i64 ; ret function %b(i8) -> i8 { @@ -71,8 +74,8 @@ block0(v0: i8): } ; block0: -; clz a3,a0##ty=i8 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; clz a0,a2##ty=i8 tmp=t2 step=a1 ; ret function %b(i16) -> i16 { @@ -82,8 +85,8 @@ block0(v0: i16): } ; block0: -; clz a3,a0##ty=i16 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; clz a0,a2##ty=i16 tmp=t2 step=a1 ; ret function %b(i32) -> i32 { @@ -93,8 +96,8 @@ block0(v0: i32): } ; block0: -; clz a3,a0##ty=i32 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; clz a0,a2##ty=i32 tmp=t2 step=a1 ; ret function %b(i64) -> i64 { @@ -104,8 +107,8 @@ block0(v0: i64): } ; block0: -; clz a3,a0##ty=i64 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; clz a0,a2##ty=i64 tmp=t2 step=a1 ; ret function %b(i128) -> i128 { @@ -115,11 +118,12 @@ block0(v0: i128): } ; block0: -; clz a4,a1##ty=i64 tmp=a2 step=a3 -; clz t3,a0##ty=i64 tmp=a6 step=a7 -; li t0,64 -; select_reg t2,t3,zero##condition=(t0 eq a4) -; add a0,a4,t2 +; mv t0,a1 +; clz a2,t0##ty=i64 tmp=a3 step=a1 +; clz a6,a0##ty=i64 tmp=a4 step=a5 +; li t3,64 +; select_reg t0,a6,zero##condition=(t3 eq a2) +; add a0,a2,t0 ; li a1,0 ; ret @@ -130,11 +134,11 @@ block0(v0: i8): } ; block0: -; sext.b a1,a0 -; not a2,a0 -; select_reg a4,a2,a0##condition=(a1 slt zero) -; clz t3,a4##ty=i8 tmp=a6 step=a7 -; addi a0,t3,-1 +; sext.b t2,a0 +; not a1,a0 +; select_reg a3,a1,a0##condition=(t2 slt zero) +; clz a7,a3##ty=i8 tmp=a5 step=a6 +; addi a0,a7,-1 ; ret function %c(i16) -> i16 { @@ -144,11 +148,11 @@ block0(v0: i16): } ; block0: -; sext.h a1,a0 -; not a2,a0 -; select_reg a4,a2,a0##condition=(a1 slt zero) -; clz t3,a4##ty=i16 tmp=a6 step=a7 -; addi a0,t3,-1 +; sext.h t2,a0 +; not a1,a0 +; select_reg a3,a1,a0##condition=(t2 slt zero) +; clz a7,a3##ty=i16 tmp=a5 step=a6 +; addi a0,a7,-1 ; ret function %c(i32) -> i32 { @@ -158,11 +162,11 @@ block0(v0: i32): } ; block0: -; sext.w a1,a0 -; not a2,a0 -; select_reg a4,a2,a0##condition=(a1 slt zero) -; clz t3,a4##ty=i32 tmp=a6 step=a7 -; addi a0,t3,-1 +; sext.w t2,a0 +; not a1,a0 +; select_reg a3,a1,a0##condition=(t2 slt zero) +; clz a7,a3##ty=i32 tmp=a5 step=a6 +; addi a0,a7,-1 ; ret function %c(i64) -> i64 { @@ -172,10 +176,10 @@ block0(v0: i64): } ; block0: -; not a1,a0 -; select_reg a2,a1,a0##condition=(a0 slt zero) -; clz a6,a2##ty=i64 tmp=a4 step=a5 -; addi a0,a6,-1 +; not t2,a0 +; select_reg a1,t2,a0##condition=(a0 slt zero) +; clz a5,a1##ty=i64 tmp=a3 step=a4 +; addi a0,a5,-1 ; ret function %c(i128) -> i128 { @@ -186,16 +190,16 @@ block0(v0: i128): ; block0: ; not a2,a0 -; select_reg a4,a2,a0##condition=(a1 slt zero) -; not a6,a1 -; select_reg t3,a6,a1##condition=(a1 slt zero) -; clz t2,t3##ty=i64 tmp=t0 step=t1 -; clz a3,a4##ty=i64 tmp=a1 step=a2 -; li a5,64 -; select_reg a7,a3,zero##condition=(a5 eq t2) -; add t4,t2,a7 -; li t1,0 -; addi a0,t4,-1 +; select_reg a2,a2,a0##condition=(a1 slt zero) +; not a4,a1 +; select_reg a6,a4,a1##condition=(a1 slt zero) +; clz t0,a6##ty=i64 tmp=t3 step=t4 +; clz a1,a2##ty=i64 tmp=t2 step=a0 +; li a3,64 +; select_reg a5,a1,zero##condition=(a3 eq t0) +; add a7,t0,a5 +; li t4,0 +; addi a0,a7,-1 ; li a1,0 ; ret @@ -206,8 +210,8 @@ block0(v0: i8): } ; block0: -; ctz a3,a0##ty=i8 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; ctz a0,a2##ty=i8 tmp=t2 step=a1 ; ret function %d(i16) -> i16 { @@ -217,8 +221,8 @@ block0(v0: i16): } ; block0: -; ctz a3,a0##ty=i16 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; ctz a0,a2##ty=i16 tmp=t2 step=a1 ; ret function %d(i32) -> i32 { @@ -228,8 +232,8 @@ block0(v0: i32): } ; block0: -; ctz a3,a0##ty=i32 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; ctz a0,a2##ty=i32 tmp=t2 step=a1 ; ret function %d(i64) -> i64 { @@ -239,8 +243,8 @@ block0(v0: i64): } ; block0: -; ctz a3,a0##ty=i64 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; ctz a0,a2##ty=i64 tmp=t2 step=a1 ; ret function %d(i128) -> i128 { @@ -250,11 +254,12 @@ block0(v0: i128): } ; block0: -; ctz a4,a0##ty=i64 tmp=a2 step=a3 -; ctz t3,a1##ty=i64 tmp=a6 step=a7 -; li t0,64 -; select_reg t2,t3,zero##condition=(t0 eq a4) -; add a0,a4,t2 +; mv t0,a0 +; ctz a2,t0##ty=i64 tmp=a0 step=a3 +; ctz a6,a1##ty=i64 tmp=a4 step=a5 +; li t3,64 +; select_reg t0,a6,zero##condition=(t3 eq a2) +; add a0,a2,t0 ; li a1,0 ; ret @@ -265,9 +270,10 @@ block0(v0: i128): } ; block0: -; popcnt a4,a0##ty=i64 tmp=a2 step=a3 -; popcnt t3,a1##ty=i64 tmp=a6 step=a7 -; add a0,a4,t3 +; mv t3,a0 +; popcnt a2,t3##ty=i64 tmp=a0 step=a3 +; popcnt a6,a1##ty=i64 tmp=a4 step=a5 +; add a0,a2,a6 ; li a1,0 ; ret @@ -278,8 +284,8 @@ block0(v0: i64): } ; block0: -; popcnt a3,a0##ty=i64 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; popcnt a0,a2##ty=i64 tmp=t2 step=a1 ; ret function %d(i32) -> i32 { @@ -289,8 +295,8 @@ block0(v0: i32): } ; block0: -; popcnt a3,a0##ty=i32 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; popcnt a0,a2##ty=i32 tmp=t2 step=a1 ; ret function %d(i16) -> i16 { @@ -300,8 +306,8 @@ block0(v0: i16): } ; block0: -; popcnt a3,a0##ty=i16 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; popcnt a0,a2##ty=i16 tmp=t2 step=a1 ; ret function %d(i8) -> i8 { @@ -311,8 +317,8 @@ block0(v0: i8): } ; block0: -; popcnt a3,a0##ty=i8 tmp=a2 step=a1 -; mv a0,a3 +; mv a2,a0 +; popcnt a0,a2##ty=i8 tmp=t2 step=a1 ; ret function %bnot_i32(i32) -> i32 { @@ -344,8 +350,8 @@ block0(v0: i64): } ; block0: -; slli a1,a0,3 -; not a0,a1 +; slli a0,a0,3 +; not a0,a0 ; ret function %bnot_i128(i128) -> i128 { @@ -421,8 +427,8 @@ block0(v0: i64, v1: i64): } ; block0: -; slli a2,a1,3 -; and a0,a0,a2 +; slli a1,a1,3 +; and a0,a0,a1 ; ret function %band_i64_constant_shift2(i64, i64) -> i64 { @@ -434,8 +440,8 @@ block0(v0: i64, v1: i64): } ; block0: -; slli a2,a1,3 -; and a0,a2,a0 +; slli a1,a1,3 +; and a0,a1,a0 ; ret function %bor_i32(i32, i32) -> i32 { @@ -500,8 +506,8 @@ block0(v0: i64, v1: i64): } ; block0: -; slli a2,a1,3 -; or a0,a0,a2 +; slli a1,a1,3 +; or a0,a0,a1 ; ret function %bor_i64_constant_shift2(i64, i64) -> i64 { @@ -513,8 +519,8 @@ block0(v0: i64, v1: i64): } ; block0: -; slli a2,a1,3 -; or a0,a2,a0 +; slli a1,a1,3 +; or a0,a1,a0 ; ret function %bxor_i32(i32, i32) -> i32 { @@ -579,8 +585,8 @@ block0(v0: i64, v1: i64): } ; block0: -; slli a2,a1,3 -; xor a0,a0,a2 +; slli a1,a1,3 +; xor a0,a0,a1 ; ret function %bxor_i64_constant_shift2(i64, i64) -> i64 { @@ -592,8 +598,8 @@ block0(v0: i64, v1: i64): } ; block0: -; slli a2,a1,3 -; xor a0,a2,a0 +; slli a1,a1,3 +; xor a0,a1,a0 ; ret function %band_not_i32(i32, i32) -> i32 { @@ -625,10 +631,10 @@ block0(v0: i128, v1: i128): } ; block0: -; not a4,a2 -; and a0,a0,a4 -; not t3,a3 -; and a1,a1,t3 +; not a2,a2 +; and a0,a0,a2 +; not a6,a3 +; and a1,a1,a6 ; ret function %band_not_i64_constant(i64) -> i64 { @@ -639,9 +645,9 @@ block0(v0: i64): } ; block0: -; li a1,4 -; not a2,a1 -; and a0,a0,a2 +; li t2,4 +; not a1,t2 +; and a0,a0,a1 ; ret function %band_not_i64_constant_shift(i64, i64) -> i64 { @@ -653,9 +659,9 @@ block0(v0: i64, v1: i64): } ; block0: -; slli a3,a1,4 -; not a2,a3 -; and a0,a0,a2 +; slli a2,a1,4 +; not a1,a2 +; and a0,a0,a1 ; ret function %bor_not_i32(i32, i32) -> i32 { @@ -687,10 +693,10 @@ block0(v0: i128, v1: i128): } ; block0: -; not a4,a2 -; or a0,a0,a4 -; not t3,a3 -; or a1,a1,t3 +; not a2,a2 +; or a0,a0,a2 +; not a6,a3 +; or a1,a1,a6 ; ret function %bor_not_i64_constant(i64) -> i64 { @@ -701,9 +707,9 @@ block0(v0: i64): } ; block0: -; li a1,4 -; not a2,a1 -; or a0,a0,a2 +; li t2,4 +; not a1,t2 +; or a0,a0,a1 ; ret function %bor_not_i64_constant_shift(i64, i64) -> i64 { @@ -715,9 +721,9 @@ block0(v0: i64, v1: i64): } ; block0: -; slli a3,a1,4 -; not a2,a3 -; or a0,a0,a2 +; slli a2,a1,4 +; not a1,a2 +; or a0,a0,a1 ; ret function %bxor_not_i32(i32, i32) -> i32 { @@ -749,10 +755,10 @@ block0(v0: i128, v1: i128): } ; block0: -; not a4,a2 -; xor a0,a0,a4 -; not t3,a3 -; xor a1,a1,t3 +; not a2,a2 +; xor a0,a0,a2 +; not a6,a3 +; xor a1,a1,a6 ; ret function %bxor_not_i64_constant(i64) -> i64 { @@ -763,9 +769,9 @@ block0(v0: i64): } ; block0: -; li a1,4 -; not a2,a1 -; xor a0,a0,a2 +; li t2,4 +; not a1,t2 +; xor a0,a0,a1 ; ret function %bxor_not_i64_constant_shift(i64, i64) -> i64 { @@ -777,9 +783,9 @@ block0(v0: i64, v1: i64): } ; block0: -; slli a3,a1,4 -; not a2,a3 -; xor a0,a0,a2 +; slli a2,a1,4 +; not a1,a2 +; xor a0,a0,a1 ; ret function %ishl_i128_i8(i128, i8) -> i128 { @@ -789,17 +795,18 @@ block0(v0: i128, v1: i8): } ; block0: -; andi a3,a2,127 -; li a5,128 -; sub a5,a5,a3 -; sll t3,a0,a3 -; srl t0,a0,a5 -; select_reg t2,zero,t0##condition=(a3 eq zero) -; sll a1,a1,a3 -; or a4,t2,a1 -; li a5,64 -; select_reg a0,zero,t3##condition=(a3 uge a5) -; select_reg a1,t3,a4##condition=(a3 uge a5) +; mv a4,a1 +; andi a1,a2,127 +; li a3,128 +; sub a3,a3,a1 +; sll a6,a0,a1 +; srl t3,a0,a3 +; select_reg t0,zero,t3##condition=(a1 eq zero) +; sll t2,a4,a1 +; or a2,t0,t2 +; li a3,64 +; select_reg a0,zero,a6##condition=(a1 uge a3) +; select_reg a1,a6,a2##condition=(a1 uge a3) ; ret function %ishl_i128_i128(i128, i128) -> i128 { @@ -809,17 +816,17 @@ block0(v0: i128, v1: i128): } ; block0: -; andi a4,a2,127 -; li a6,128 -; sub a6,a6,a4 -; sll t4,a0,a4 -; srl t1,a0,a6 -; select_reg a0,zero,t1##condition=(a4 eq zero) -; sll a2,a1,a4 -; or a5,a0,a2 -; li a6,64 -; select_reg a0,zero,t4##condition=(a4 uge a6) -; select_reg a1,t4,a5##condition=(a4 uge a6) +; andi a2,a2,127 +; li a4,128 +; sub a4,a4,a2 +; sll a7,a0,a2 +; srl t4,a0,a4 +; select_reg t1,zero,t4##condition=(a2 eq zero) +; sll a0,a1,a2 +; or a3,t1,a0 +; li a4,64 +; select_reg a0,zero,a7##condition=(a2 uge a4) +; select_reg a1,a7,a3##condition=(a2 uge a4) ; ret function %ushr_i128_i8(i128, i8) -> i128 { @@ -829,17 +836,19 @@ block0(v0: i128, v1: i8): } ; block0: -; andi a3,a2,127 -; li a5,128 -; sub a5,a5,a3 -; sll t3,a1,a5 -; select_reg t0,zero,t3##condition=(a3 eq zero) -; srl t2,a0,a3 -; or a2,t0,t2 -; li a4,64 -; srl a5,a1,a3 -; select_reg a0,a5,a2##condition=(a3 uge a4) -; select_reg a1,zero,a5##condition=(a3 uge a4) +; mv t1,a1 +; andi a1,a2,127 +; li a3,128 +; sub a3,a3,a1 +; mv a2,t1 +; sll a6,a2,a3 +; select_reg t3,zero,a6##condition=(a1 eq zero) +; srl t0,a0,a1 +; or t2,t3,t0 +; li a3,64 +; srl a4,a2,a1 +; select_reg a0,a4,t2##condition=(a1 uge a3) +; select_reg a1,zero,a4##condition=(a1 uge a3) ; ret function %ushr_i128_i128(i128, i128) -> i128 { @@ -849,17 +858,17 @@ block0(v0: i128, v1: i128): } ; block0: -; andi a4,a2,127 -; li a6,128 -; sub a6,a6,a4 -; sll t4,a1,a6 -; select_reg t1,zero,t4##condition=(a4 eq zero) -; srl a0,a0,a4 -; or a2,t1,a0 -; li a5,64 -; srl a6,a1,a4 -; select_reg a0,a6,a2##condition=(a4 uge a5) -; select_reg a1,zero,a6##condition=(a4 uge a5) +; andi a2,a2,127 +; li a4,128 +; sub a4,a4,a2 +; sll a7,a1,a4 +; select_reg t4,zero,a7##condition=(a2 eq zero) +; srl t1,a0,a2 +; or a0,t4,t1 +; li a3,64 +; srl a4,a1,a2 +; select_reg a0,a4,a0##condition=(a2 uge a3) +; select_reg a1,zero,a4##condition=(a2 uge a3) ; ret function %sshr_i128_i8(i128, i8) -> i128 { @@ -869,19 +878,20 @@ block0(v0: i128, v1: i8): } ; block0: -; andi a3,a2,127 -; li a5,128 -; sub a5,a5,a3 -; sll t3,a1,a5 -; select_reg t0,zero,t3##condition=(a3 eq zero) -; srl t2,a0,a3 -; or a2,t0,t2 -; li a4,64 -; sra a5,a1,a3 -; li a7,-1 -; select_reg t4,a7,zero##condition=(a1 slt zero) -; select_reg a0,a5,a2##condition=(a3 uge a4) -; select_reg a1,t4,a5##condition=(a3 uge a4) +; mv a3,a1 +; andi a1,a2,127 +; li a4,128 +; sub a4,a4,a1 +; sll a6,a3,a4 +; select_reg t3,zero,a6##condition=(a1 eq zero) +; srl t0,a0,a1 +; or t2,t3,t0 +; li a2,64 +; sra a4,a3,a1 +; li a5,-1 +; select_reg a7,a5,zero##condition=(a3 slt zero) +; select_reg a0,a4,t2##condition=(a1 uge a2) +; select_reg a1,a7,a4##condition=(a1 uge a2) ; ret function %sshr_i128_i128(i128, i128) -> i128 { @@ -891,18 +901,18 @@ block0(v0: i128, v1: i128): } ; block0: -; andi a4,a2,127 -; li a6,128 -; sub a6,a6,a4 -; sll t4,a1,a6 -; select_reg t1,zero,t4##condition=(a4 eq zero) -; srl a0,a0,a4 -; or a2,t1,a0 -; li a5,64 -; sra a6,a1,a4 -; li t3,-1 -; select_reg t0,t3,zero##condition=(a1 slt zero) -; select_reg a0,a6,a2##condition=(a4 uge a5) -; select_reg a1,t0,a6##condition=(a4 uge a5) +; andi a2,a2,127 +; li a4,128 +; sub a4,a4,a2 +; sll a7,a1,a4 +; select_reg t4,zero,a7##condition=(a2 eq zero) +; srl t1,a0,a2 +; or a0,t4,t1 +; li a3,64 +; sra a4,a1,a2 +; li a6,-1 +; select_reg t3,a6,zero##condition=(a1 slt zero) +; select_reg a0,a4,a0##condition=(a2 uge a3) +; select_reg a1,t3,a4##condition=(a2 uge a3) ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/call.clif b/cranelift/filetests/filetests/isa/riscv64/call.clif index ccc7ad299b..1f1a4dac75 100644 --- a/cranelift/filetests/filetests/isa/riscv64/call.clif +++ b/cranelift/filetests/filetests/isa/riscv64/call.clif @@ -36,8 +36,8 @@ block0(v0: i32): ; mv fp,sp ; block0: ; uext.w a0,a0 -; load_sym a3,%g+0 -; callind a3 +; load_sym a2,%g+0 +; callind a2 ; ld ra,8(sp) ; ld fp,0(sp) ; add sp,+16 @@ -66,8 +66,8 @@ block0(v0: i32): ; mv fp,sp ; block0: ; sext.w a0,a0 -; load_sym a3,%g+0 -; callind a3 +; load_sym a2,%g+0 +; callind a2 ; ld ra,8(sp) ; ld fp,0(sp) ; add sp,+16 @@ -109,8 +109,8 @@ block0(v0: i8): ; li a7,42 ; sext.b t3,t3 ; sd t3,0(sp) -; load_sym t4,%g+0 -; callind t4 +; load_sym t3,%g+0 +; callind t3 ; add sp,+16 ; virtual_sp_offset_adj -16 ; ld ra,8(sp) @@ -125,26 +125,26 @@ block0(v0: i8): } ; block0: -; mv a7,a0 -; mv a6,a1 -; li a0,42 -; li a1,42 ; li a2,42 -; li a5,42 -; li t3,42 -; li t1,42 -; li a3,42 +; mv t1,a2 +; li a2,42 +; mv a3,a2 ; li a4,42 -; mv t2,a7 -; mv t0,a6 -; sw a2,0(t0) -; sw a5,8(t0) -; sw t3,16(t0) -; sw t1,24(t0) -; sw a3,32(t0) -; sw a4,40(t0) -; sext.b t2,t2 -; sd t2,48(t0) +; li a6,42 +; li t3,42 +; li t0,42 +; li t2,42 +; li a2,42 +; sw a4,0(a1) +; sw a6,8(a1) +; sw t3,16(a1) +; sw t0,24(a1) +; sw t2,32(a1) +; sw a2,40(a1) +; sext.b t4,a0 +; sd a0,48(a1) +; mv a0,t1 +; mv a1,a3 ; ret function %f8() { @@ -210,7 +210,6 @@ block0(v0: i128, v1: i64): } ; block0: -; mv a2,a0 ; mv a0,a1 ; ret @@ -229,12 +228,12 @@ block0(v0: i64): ; sd fp,0(sp) ; mv fp,sp ; block0: -; mv a6,a0 +; mv a5,a0 ; li a0,42 -; mv a1,a6 +; mv a1,a5 ; li a2,42 -; load_sym a6,%f11+0 -; callind a6 +; load_sym a5,%f11+0 +; callind a5 ; ld ra,8(sp) ; ld fp,0(sp) ; add sp,+16 @@ -248,6 +247,7 @@ block0(v0: i64, v1: i128): ; block0: ; mv a0,a1 +; mv a1,a2 ; ret function %f12_call(i64) -> i64 { @@ -268,8 +268,8 @@ block0(v0: i64): ; mv a1,a0 ; li a2,42 ; li a0,42 -; load_sym a6,%f12+0 -; callind a6 +; load_sym a5,%f12+0 +; callind a5 ; ld ra,8(sp) ; ld fp,0(sp) ; add sp,+16 @@ -283,6 +283,7 @@ block0(v0: i64, v1: i128): ; block0: ; mv a0,a1 +; mv a1,a2 ; ret function %f13_call(i64) -> i64 { @@ -303,8 +304,8 @@ block0(v0: i64): ; mv a1,a0 ; li a2,42 ; li a0,42 -; load_sym a6,%f13+0 -; callind a6 +; load_sym a5,%f13+0 +; callind a5 ; ld ra,8(sp) ; ld fp,0(sp) ; add sp,+16 @@ -320,8 +321,8 @@ block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128): ; sd fp,0(sp) ; mv fp,sp ; block0: -; ld a1,16(fp) ; mv a0,a7 +; ld a1,16(fp) ; ld ra,8(sp) ; ld fp,0(sp) ; add sp,+16 @@ -370,8 +371,8 @@ block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128): ; sd fp,0(sp) ; mv fp,sp ; block0: -; ld a1,16(fp) ; mv a0,a7 +; ld a1,16(fp) ; ld ra,8(sp) ; ld fp,0(sp) ; add sp,+16 diff --git a/cranelift/filetests/filetests/isa/riscv64/condbr.clif b/cranelift/filetests/filetests/isa/riscv64/condbr.clif index cc9946faa7..587175faaa 100644 --- a/cranelift/filetests/filetests/isa/riscv64/condbr.clif +++ b/cranelift/filetests/filetests/isa/riscv64/condbr.clif @@ -128,8 +128,8 @@ block2: } ; block0: -; eq a3,a0,a1##ty=i64 -; bne a3,zero,taken(label1),not_taken(label2) +; eq a2,a0,a1##ty=i64 +; bne a2,zero,taken(label1),not_taken(label2) ; block1: ; li a0,1 ; ret @@ -149,8 +149,8 @@ block1: } ; block0: -; eq a2,a0,a1##ty=i64 -; bne a2,zero,taken(label1),not_taken(label2) +; eq a1,a0,a1##ty=i64 +; bne a1,zero,taken(label1),not_taken(label2) ; block1: ; j label3 ; block2: diff --git a/cranelift/filetests/filetests/isa/riscv64/condops.clif b/cranelift/filetests/filetests/isa/riscv64/condops.clif index d96a7a32c3..6077e2b8ac 100644 --- a/cranelift/filetests/filetests/isa/riscv64/condops.clif +++ b/cranelift/filetests/filetests/isa/riscv64/condops.clif @@ -23,11 +23,10 @@ block0(v0: i8): } ; block0: -; mv a5,a0 -; li a0,42 -; uext.b a2,a5 -; uext.b a4,a0 -; eq a0,a2,a4##ty=i8 +; li t2,42 +; uext.b a1,a0 +; uext.b a3,t2 +; eq a0,a1,a3##ty=i8 ; ret function %h(i8, i8, i8) -> i8 { @@ -37,11 +36,10 @@ block0(v0: i8, v1: i8, v2: i8): } ; block0: -; mv t3,a2 -; and a2,a0,a1 -; not a4,a0 -; and a6,a4,t3 -; or a0,a2,a6 +; and a1,a0,a1 +; not a3,a0 +; and a5,a3,a2 +; or a0,a1,a5 ; ret function %i(i8, i8, i8) -> i8 { diff --git a/cranelift/filetests/filetests/isa/riscv64/constants.clif b/cranelift/filetests/filetests/isa/riscv64/constants.clif index 84be21c1f2..e89e06694c 100644 --- a/cranelift/filetests/filetests/isa/riscv64/constants.clif +++ b/cranelift/filetests/filetests/isa/riscv64/constants.clif @@ -233,11 +233,11 @@ block0: } ; block0: -; auipc t2,0 -; ld t2,12(t2) +; auipc t1,0 +; ld t1,12(t1) ; j 12 ; .8byte 0x3ff0000000000000 -; fmv.d.x fa0,t2 +; fmv.d.x fa0,t1 ; ret function %f() -> f32 { @@ -247,8 +247,8 @@ block0: } ; block0: -; lui t2,264704 -; fmv.w.x fa0,t2 +; lui t1,264704 +; fmv.w.x fa0,t1 ; ret function %f() -> f64 { @@ -258,11 +258,11 @@ block0: } ; block0: -; auipc t2,0 -; ld t2,12(t2) +; auipc t1,0 +; ld t1,12(t1) ; j 12 ; .8byte 0x4049000000000000 -; fmv.d.x fa0,t2 +; fmv.d.x fa0,t1 ; ret function %f() -> f32 { @@ -272,8 +272,8 @@ block0: } ; block0: -; lui t2,271488 -; fmv.w.x fa0,t2 +; lui t1,271488 +; fmv.w.x fa0,t1 ; ret function %f() -> f64 { @@ -283,8 +283,8 @@ block0: } ; block0: -; li t2,0 -; fmv.d.x fa0,t2 +; li t1,0 +; fmv.d.x fa0,t1 ; ret function %f() -> f32 { @@ -294,8 +294,8 @@ block0: } ; block0: -; li t2,0 -; fmv.w.x fa0,t2 +; li t1,0 +; fmv.w.x fa0,t1 ; ret function %f() -> f64 { @@ -305,11 +305,11 @@ block0: } ; block0: -; auipc t2,0 -; ld t2,12(t2) +; auipc t1,0 +; ld t1,12(t1) ; j 12 ; .8byte 0xc030000000000000 -; fmv.d.x fa0,t2 +; fmv.d.x fa0,t1 ; ret function %f() -> f32 { @@ -319,10 +319,10 @@ block0: } ; block0: -; auipc t2,0 -; lwu t2,12(t2) +; auipc t1,0 +; lwu t1,12(t1) ; j 8 ; .4byte 0xc1800000 -; fmv.w.x fa0,t2 +; fmv.w.x fa0,t1 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/extend-op.clif b/cranelift/filetests/filetests/isa/riscv64/extend-op.clif index 0839176dcf..595ef6a8d1 100644 --- a/cranelift/filetests/filetests/isa/riscv64/extend-op.clif +++ b/cranelift/filetests/filetests/isa/riscv64/extend-op.clif @@ -11,8 +11,8 @@ block0(v0: i8): } ; block0: -; sext.b a1,a0 -; addi a0,a1,42 +; sext.b a0,a0 +; addi a0,a0,42 ; ret function %f2(i8, i64) -> i64 { @@ -44,8 +44,8 @@ block0(v0: i64): } ; block0: -; slt a1,a0,zero -; sext.b1 a1,a1 +; slt t2,a0,zero +; sext.b1 a1,t2 ; ret function %i128_uextend_i32(i32) -> i128 { @@ -66,9 +66,9 @@ block0(v0: i32): } ; block0: -; sext.w a1,a0 -; slt a3,a1,zero -; sext.b1 a1,a3 +; sext.w t2,a0 +; slt a1,t2,zero +; sext.b1 a1,a1 ; ret function %i128_uextend_i16(i16) -> i128 { @@ -89,9 +89,9 @@ block0(v0: i16): } ; block0: -; sext.h a1,a0 -; slt a3,a1,zero -; sext.b1 a1,a3 +; sext.h t2,a0 +; slt a1,t2,zero +; sext.b1 a1,a1 ; ret function %i128_uextend_i8(i8) -> i128 { @@ -112,8 +112,8 @@ block0(v0: i8): } ; block0: -; sext.b a1,a0 -; slt a3,a1,zero -; sext.b1 a1,a3 +; sext.b t2,a0 +; slt a1,t2,zero +; sext.b1 a1,a1 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif b/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif index a5b5b758fd..61df690bb7 100644 --- a/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif +++ b/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif @@ -49,7 +49,7 @@ block0(v0: f32): } ; block0: -; fcvt_to_uint.i8 a0,fa0##in_ty=f32 tmp=ft4 +; fcvt_to_uint.i8 a0,fa0##in_ty=f32 tmp=ft3 ; ret function u0:0(f64) -> i8 { @@ -59,7 +59,7 @@ block0(v0: f64): } ; block0: -; fcvt_to_uint.i8 a0,fa0##in_ty=f64 tmp=ft4 +; fcvt_to_uint.i8 a0,fa0##in_ty=f64 tmp=ft3 ; ret function u0:0(f32) -> i16 { @@ -69,7 +69,7 @@ block0(v0: f32): } ; block0: -; fcvt_to_uint.i16 a0,fa0##in_ty=f32 tmp=ft4 +; fcvt_to_uint.i16 a0,fa0##in_ty=f32 tmp=ft3 ; ret function u0:0(f64) -> i16 { @@ -79,6 +79,6 @@ block0(v0: f64): } ; block0: -; fcvt_to_uint.i16 a0,fa0##in_ty=f64 tmp=ft4 +; fcvt_to_uint.i16 a0,fa0##in_ty=f64 tmp=ft3 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/float.clif b/cranelift/filetests/filetests/isa/riscv64/float.clif index e231d4fde6..2b5f6cea89 100644 --- a/cranelift/filetests/filetests/isa/riscv64/float.clif +++ b/cranelift/filetests/filetests/isa/riscv64/float.clif @@ -89,8 +89,8 @@ block0(v0: f32, v1: f32): } ; block0: -; fmin.s ft4,fa0,fa1##tmp=a2 ty=f32 -; fmv.d fa0,ft4 +; fmv.d ft5,fa0 +; fmin.s fa0,ft5,fa1##tmp=a1 ty=f32 ; ret function %f10(f64, f64) -> f64 { @@ -100,8 +100,8 @@ block0(v0: f64, v1: f64): } ; block0: -; fmin.d ft4,fa0,fa1##tmp=a2 ty=f64 -; fmv.d fa0,ft4 +; fmv.d ft5,fa0 +; fmin.d fa0,ft5,fa1##tmp=a1 ty=f64 ; ret function %f11(f32, f32) -> f32 { @@ -111,8 +111,8 @@ block0(v0: f32, v1: f32): } ; block0: -; fmax.s ft4,fa0,fa1##tmp=a2 ty=f32 -; fmv.d fa0,ft4 +; fmv.d ft5,fa0 +; fmax.s fa0,ft5,fa1##tmp=a1 ty=f32 ; ret function %f12(f64, f64) -> f64 { @@ -122,8 +122,8 @@ block0(v0: f64, v1: f64): } ; block0: -; fmax.d ft4,fa0,fa1##tmp=a2 ty=f64 -; fmv.d fa0,ft4 +; fmv.d ft5,fa0 +; fmax.d fa0,ft5,fa1##tmp=a1 ty=f64 ; ret function %f13(f32) -> f32 { @@ -213,8 +213,8 @@ block0(v0: f32): } ; block0: -; ceil ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f32 -; fmv.d fa0,ft3 +; fmv.d ft5,fa0 +; ceil fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32 ; ret function %f22(f64) -> f64 { @@ -224,8 +224,8 @@ block0(v0: f64): } ; block0: -; ceil ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f64 -; fmv.d fa0,ft3 +; fmv.d ft5,fa0 +; ceil fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64 ; ret function %f23(f32) -> f32 { @@ -235,8 +235,8 @@ block0(v0: f32): } ; block0: -; floor ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f32 -; fmv.d fa0,ft3 +; fmv.d ft5,fa0 +; floor fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32 ; ret function %f24(f64) -> f64 { @@ -246,8 +246,8 @@ block0(v0: f64): } ; block0: -; floor ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f64 -; fmv.d fa0,ft3 +; fmv.d ft5,fa0 +; floor fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64 ; ret function %f25(f32) -> f32 { @@ -257,8 +257,8 @@ block0(v0: f32): } ; block0: -; trunc ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f32 -; fmv.d fa0,ft3 +; fmv.d ft5,fa0 +; trunc fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32 ; ret function %f26(f64) -> f64 { @@ -268,8 +268,8 @@ block0(v0: f64): } ; block0: -; trunc ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f64 -; fmv.d fa0,ft3 +; fmv.d ft5,fa0 +; trunc fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64 ; ret function %f27(f32) -> f32 { @@ -279,8 +279,8 @@ block0(v0: f32): } ; block0: -; nearest ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f32 -; fmv.d fa0,ft3 +; fmv.d ft5,fa0 +; nearest fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f32 ; ret function %f28(f64) -> f64 { @@ -290,8 +290,8 @@ block0(v0: f64): } ; block0: -; nearest ft3,fa0##int_tmp=a1 f_tmp=ft5 ty=f64 -; fmv.d fa0,ft3 +; fmv.d ft5,fa0 +; nearest fa0,ft5##int_tmp=a0 f_tmp=ft4 ty=f64 ; ret function %f29(f32, f32, f32) -> f32 { @@ -341,7 +341,7 @@ block0(v0: f32): } ; block0: -; fcvt_to_uint.i32 a0,fa0##in_ty=f32 tmp=ft4 +; fcvt_to_uint.i32 a0,fa0##in_ty=f32 tmp=ft3 ; ret function %f34(f32) -> i32 { @@ -351,7 +351,7 @@ block0(v0: f32): } ; block0: -; fcvt_to_sint.i32 a0,fa0##in_ty=f32 tmp=ft4 +; fcvt_to_sint.i32 a0,fa0##in_ty=f32 tmp=ft3 ; ret function %f35(f32) -> i64 { @@ -361,7 +361,7 @@ block0(v0: f32): } ; block0: -; fcvt_to_uint.i64 a0,fa0##in_ty=f32 tmp=ft4 +; fcvt_to_uint.i64 a0,fa0##in_ty=f32 tmp=ft3 ; ret function %f36(f32) -> i64 { @@ -371,7 +371,7 @@ block0(v0: f32): } ; block0: -; fcvt_to_sint.i64 a0,fa0##in_ty=f32 tmp=ft4 +; fcvt_to_sint.i64 a0,fa0##in_ty=f32 tmp=ft3 ; ret function %f37(f64) -> i32 { @@ -381,7 +381,7 @@ block0(v0: f64): } ; block0: -; fcvt_to_uint.i32 a0,fa0##in_ty=f64 tmp=ft4 +; fcvt_to_uint.i32 a0,fa0##in_ty=f64 tmp=ft3 ; ret function %f38(f64) -> i32 { @@ -391,7 +391,7 @@ block0(v0: f64): } ; block0: -; fcvt_to_sint.i32 a0,fa0##in_ty=f64 tmp=ft4 +; fcvt_to_sint.i32 a0,fa0##in_ty=f64 tmp=ft3 ; ret function %f39(f64) -> i64 { @@ -401,7 +401,7 @@ block0(v0: f64): } ; block0: -; fcvt_to_uint.i64 a0,fa0##in_ty=f64 tmp=ft4 +; fcvt_to_uint.i64 a0,fa0##in_ty=f64 tmp=ft3 ; ret function %f40(f64) -> i64 { @@ -411,7 +411,7 @@ block0(v0: f64): } ; block0: -; fcvt_to_sint.i64 a0,fa0##in_ty=f64 tmp=ft4 +; fcvt_to_sint.i64 a0,fa0##in_ty=f64 tmp=ft3 ; ret function %f41(i32) -> f32 { @@ -501,7 +501,7 @@ block0(v0: f32): } ; block0: -; fcvt_to_uint_sat.i32 a0,fa0##in_ty=f32 tmp=ft4 +; fcvt_to_uint_sat.i32 a0,fa0##in_ty=f32 tmp=ft3 ; ret function %f50(f32) -> i32 { @@ -511,7 +511,7 @@ block0(v0: f32): } ; block0: -; fcvt_to_sint_sat.i32 a0,fa0##in_ty=f32 tmp=ft4 +; fcvt_to_sint_sat.i32 a0,fa0##in_ty=f32 tmp=ft3 ; ret function %f51(f32) -> i64 { @@ -521,7 +521,7 @@ block0(v0: f32): } ; block0: -; fcvt_to_uint_sat.i64 a0,fa0##in_ty=f32 tmp=ft4 +; fcvt_to_uint_sat.i64 a0,fa0##in_ty=f32 tmp=ft3 ; ret function %f52(f32) -> i64 { @@ -531,7 +531,7 @@ block0(v0: f32): } ; block0: -; fcvt_to_sint_sat.i64 a0,fa0##in_ty=f32 tmp=ft4 +; fcvt_to_sint_sat.i64 a0,fa0##in_ty=f32 tmp=ft3 ; ret function %f53(f64) -> i32 { @@ -541,7 +541,7 @@ block0(v0: f64): } ; block0: -; fcvt_to_uint_sat.i32 a0,fa0##in_ty=f64 tmp=ft4 +; fcvt_to_uint_sat.i32 a0,fa0##in_ty=f64 tmp=ft3 ; ret function %f54(f64) -> i32 { @@ -551,7 +551,7 @@ block0(v0: f64): } ; block0: -; fcvt_to_sint_sat.i32 a0,fa0##in_ty=f64 tmp=ft4 +; fcvt_to_sint_sat.i32 a0,fa0##in_ty=f64 tmp=ft3 ; ret function %f55(f64) -> i64 { @@ -561,7 +561,7 @@ block0(v0: f64): } ; block0: -; fcvt_to_uint_sat.i64 a0,fa0##in_ty=f64 tmp=ft4 +; fcvt_to_uint_sat.i64 a0,fa0##in_ty=f64 tmp=ft3 ; ret function %f56(f64) -> i64 { @@ -571,6 +571,6 @@ block0(v0: f64): } ; block0: -; fcvt_to_sint_sat.i64 a0,fa0##in_ty=f64 tmp=ft4 +; fcvt_to_sint_sat.i64 a0,fa0##in_ty=f64 tmp=ft3 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/heap-addr.clif b/cranelift/filetests/filetests/isa/riscv64/heap-addr.clif index 189e68091c..140add4a6d 100644 --- a/cranelift/filetests/filetests/isa/riscv64/heap-addr.clif +++ b/cranelift/filetests/filetests/isa/riscv64/heap-addr.clif @@ -13,16 +13,16 @@ block0(v0: i64, v1: i32): } ; block0: -; uext.w t3,a1 -; ld t4,0(a0) -; addi t4,t4,0 -; ule t0,t3,t4##ty=i64 -; bne t0,zero,taken(label1),not_taken(label2) +; uext.w a7,a1 +; ld t3,0(a0) +; addi t3,t3,0 +; ule t4,a7,t3##ty=i64 +; bne t4,zero,taken(label1),not_taken(label2) ; block1: -; add t0,a0,t3 -; ugt t3,t3,t4##ty=i64 -; li t1,0 -; selectif_spectre_guard a0,t1,t0##test=t3 +; add t4,a0,a7 +; ugt a7,a7,t3##ty=i64 +; li t0,0 +; selectif_spectre_guard a0,t0,t4##test=a7 ; ret ; block2: ; udf##trap_code=heap_oob @@ -37,16 +37,16 @@ block0(v0: i64, v1: i32): } ; block0: -; uext.w t3,a1 -; lui a7,16 -; ule t4,t3,a7##ty=i64 -; bne t4,zero,taken(label1),not_taken(label2) +; uext.w a7,a1 +; lui a6,16 +; ule t3,a7,a6##ty=i64 +; bne t3,zero,taken(label1),not_taken(label2) ; block1: -; add t4,a0,t3 -; lui a7,16 -; ugt t0,t3,a7##ty=i64 -; li t1,0 -; selectif_spectre_guard a0,t1,t4##test=t0 +; add t3,a0,a7 +; lui a6,16 +; ugt t4,a7,a6##ty=i64 +; li t0,0 +; selectif_spectre_guard a0,t0,t3##test=t4 ; ret ; block2: ; udf##trap_code=heap_oob diff --git a/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif b/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif index 7bc84cc08f..9e73e89e81 100644 --- a/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif +++ b/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif @@ -9,9 +9,9 @@ block0(v0: i128): } ; block0: -; or a2,a0,a1 -; li a4,-1 -; select_reg a1,zero,a4##condition=(zero eq a2) +; or a0,a0,a1 +; li a2,-1 +; select_reg a1,zero,a2##condition=(zero eq a0) ; mv a0,a1 ; ret @@ -22,9 +22,9 @@ block0(v0: i128): } ; block0: -; or a1,a0,a1 -; li a3,-1 -; select_reg a0,zero,a3##condition=(zero eq a1) +; or a0,a0,a1 +; li a2,-1 +; select_reg a0,zero,a2##condition=(zero eq a0) ; ret function %bmask_i128_i32(i128) -> i32 { @@ -34,9 +34,9 @@ block0(v0: i128): } ; block0: -; or a1,a0,a1 -; li a3,-1 -; select_reg a0,zero,a3##condition=(zero eq a1) +; or a0,a0,a1 +; li a2,-1 +; select_reg a0,zero,a2##condition=(zero eq a0) ; ret function %bmask_i128_i16(i128) -> i16 { @@ -46,9 +46,9 @@ block0(v0: i128): } ; block0: -; or a1,a0,a1 -; li a3,-1 -; select_reg a0,zero,a3##condition=(zero eq a1) +; or a0,a0,a1 +; li a2,-1 +; select_reg a0,zero,a2##condition=(zero eq a0) ; ret function %bmask_i128_i8(i128) -> i8 { @@ -58,9 +58,9 @@ block0(v0: i128): } ; block0: -; or a1,a0,a1 -; li a3,-1 -; select_reg a0,zero,a3##condition=(zero eq a1) +; or a0,a0,a1 +; li a2,-1 +; select_reg a0,zero,a2##condition=(zero eq a0) ; ret function %bmask_i64_i128(i64) -> i128 { @@ -70,8 +70,8 @@ block0(v0: i64): } ; block0: -; li a1,-1 -; select_reg a1,zero,a1##condition=(zero eq a0) +; li t2,-1 +; select_reg a1,zero,t2##condition=(zero eq a0) ; mv a0,a1 ; ret @@ -82,9 +82,9 @@ block0(v0: i32): } ; block0: -; addiw a1,a0,0 -; li a3,-1 -; select_reg a1,zero,a3##condition=(zero eq a1) +; addiw t2,a0,0 +; li a1,-1 +; select_reg a1,zero,a1##condition=(zero eq t2) ; mv a0,a1 ; ret @@ -95,11 +95,11 @@ block0(v0: i16): } ; block0: -; lui a1,16 -; addi a1,a1,4095 -; and a4,a0,a1 -; li a6,-1 -; select_reg a1,zero,a6##condition=(zero eq a4) +; lui t2,16 +; addi t2,t2,4095 +; and a2,a0,t2 +; li a4,-1 +; select_reg a1,zero,a4##condition=(zero eq a2) ; mv a0,a1 ; ret @@ -110,9 +110,9 @@ block0(v0: i8): } ; block0: -; andi a1,a0,255 -; li a3,-1 -; select_reg a1,zero,a3##condition=(zero eq a1) +; andi t2,a0,255 +; li a1,-1 +; select_reg a1,zero,a1##condition=(zero eq t2) ; mv a0,a1 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif b/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif index 9cad68ae6f..e820ef251c 100644 --- a/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif +++ b/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif @@ -11,12 +11,12 @@ block0: } ; block0: -; lui t1,14 -; addi t1,t1,3532 -; lui a1,14 -; addi a1,a1,3532 -; uext.h a4,t1 -; uext.h a6,a1 -; ne a0,a4,a6##ty=i16 +; lui t0,14 +; addi t0,t0,3532 +; lui a0,14 +; addi a0,a0,3532 +; uext.h a3,t0 +; uext.h a5,a0 +; ne a0,a3,a5##ty=i16 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/narrow-arithmetic.clif b/cranelift/filetests/filetests/isa/riscv64/narrow-arithmetic.clif index c8d2173551..3081ff2361 100644 --- a/cranelift/filetests/filetests/isa/riscv64/narrow-arithmetic.clif +++ b/cranelift/filetests/filetests/isa/riscv64/narrow-arithmetic.clif @@ -40,8 +40,8 @@ block0(v0: i32, v1: i8): } ; block0: -; sext.b a2,a1 -; addw a0,a0,a2 +; sext.b a1,a1 +; addw a0,a0,a1 ; ret function %add64_32(i64, i32) -> i64 { @@ -52,7 +52,7 @@ block0(v0: i64, v1: i32): } ; block0: -; sext.w a2,a1 -; add a0,a0,a2 +; sext.w a1,a1 +; add a0,a0,a1 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/prologue.clif b/cranelift/filetests/filetests/isa/riscv64/prologue.clif index 439c3bc09d..c546973bb6 100644 --- a/cranelift/filetests/filetests/isa/riscv64/prologue.clif +++ b/cranelift/filetests/filetests/isa/riscv64/prologue.clif @@ -92,6 +92,7 @@ block0(v0: f64): ; fsd fs11,-88(sp) ; add sp,-96 ; block0: +; fadd.d ft3,fa0,fa0 ; fadd.d ft4,fa0,fa0 ; fadd.d ft5,fa0,fa0 ; fadd.d ft6,fa0,fa0 @@ -110,7 +111,7 @@ block0(v0: f64): ; fadd.d ft0,fa0,fa0 ; fadd.d ft1,fa0,fa0 ; fadd.d ft2,fa0,fa0 -; fadd.d ft3,fa0,fa0 +; fadd.d fs3,fa0,fa0 ; fadd.d fs4,fa0,fa0 ; fadd.d fs5,fa0,fa0 ; fadd.d fs6,fa0,fa0 @@ -122,38 +123,37 @@ block0(v0: f64): ; fadd.d fs0,fa0,fa0 ; fadd.d fs1,fa0,fa0 ; fadd.d fs2,fa0,fa0 -; fadd.d fs3,fa0,fa0 -; fadd.d ft4,fa0,ft4 -; fadd.d ft5,ft5,ft6 -; fadd.d ft6,ft7,fa1 -; fadd.d ft7,fa2,fa3 -; fadd.d fa0,fa4,fa5 -; fadd.d fa1,fa6,fa7 -; fadd.d fa2,ft8,ft9 -; fadd.d fa3,ft10,ft11 -; fadd.d fa4,ft0,ft1 -; fadd.d fa5,ft2,ft3 -; fadd.d fa6,fs4,fs5 -; fadd.d fa7,fs6,fs7 -; fadd.d ft8,fs8,fs9 -; fadd.d ft9,fs10,fs11 -; fadd.d ft10,fs0,fs1 -; fadd.d ft11,fs2,fs3 +; fadd.d ft3,fa0,ft3 ; fadd.d ft4,ft4,ft5 ; fadd.d ft5,ft6,ft7 -; fadd.d ft6,fa0,fa1 -; fadd.d ft7,fa2,fa3 -; fadd.d fa0,fa4,fa5 -; fadd.d fa1,fa6,fa7 -; fadd.d fa2,ft8,ft9 -; fadd.d fa3,ft10,ft11 -; fadd.d ft4,ft4,ft5 -; fadd.d ft5,ft6,ft7 -; fadd.d ft6,fa0,fa1 -; fadd.d ft7,fa2,fa3 -; fadd.d ft4,ft4,ft5 -; fadd.d ft5,ft6,ft7 -; fadd.d fa0,ft4,ft5 +; fadd.d ft6,fa1,fa2 +; fadd.d ft7,fa3,fa4 +; fadd.d fa0,fa5,fa6 +; fadd.d fa1,fa7,ft8 +; fadd.d fa2,ft9,ft10 +; fadd.d fa3,ft11,ft0 +; fadd.d fa4,ft1,ft2 +; fadd.d fa5,fs3,fs4 +; fadd.d fa6,fs5,fs6 +; fadd.d fa7,fs7,fs8 +; fadd.d ft8,fs9,fs10 +; fadd.d ft9,fs11,fs0 +; fadd.d ft10,fs1,fs2 +; fadd.d ft3,ft3,ft4 +; fadd.d ft4,ft5,ft6 +; fadd.d ft5,ft7,fa0 +; fadd.d ft6,fa1,fa2 +; fadd.d ft7,fa3,fa4 +; fadd.d fa0,fa5,fa6 +; fadd.d fa1,fa7,ft8 +; fadd.d fa2,ft9,ft10 +; fadd.d ft3,ft3,ft4 +; fadd.d ft4,ft5,ft6 +; fadd.d ft5,ft7,fa0 +; fadd.d ft6,fa1,fa2 +; fadd.d ft3,ft3,ft4 +; fadd.d ft4,ft5,ft6 +; fadd.d fa0,ft3,ft4 ; add sp,+96 ; fld fs0,-8(sp) ; fld fs2,-16(sp) @@ -221,15 +221,16 @@ block0(v0: i64): ; sd ra,8(sp) ; sd fp,0(sp) ; mv fp,sp -; sd s6,-8(sp) -; sd s7,-16(sp) -; sd s8,-24(sp) -; sd s9,-32(sp) -; sd s10,-40(sp) -; sd s11,-48(sp) +; sd s5,-8(sp) +; sd s6,-16(sp) +; sd s7,-24(sp) +; sd s8,-32(sp) +; sd s9,-40(sp) +; sd s10,-48(sp) ; add sp,-48 ; block0: -; add t4,a0,a0 +; add t3,a0,a0 +; add t4,a0,t3 ; add t0,a0,t4 ; add t1,a0,t0 ; add t2,a0,t1 @@ -240,38 +241,37 @@ block0(v0: i64): ; add a5,a0,a4 ; add a6,a0,a5 ; add a7,a0,a6 -; add t3,a0,a7 -; add s6,a0,t3 +; add s5,a0,a7 +; add s6,a0,s5 ; add s7,a0,s6 ; add s8,a0,s7 ; add s9,a0,s8 ; add s10,a0,s9 -; add s11,a0,s10 -; add t4,a0,t4 -; add t0,t0,t1 -; add t1,t2,a1 -; add t2,a2,a3 -; add a0,a4,a5 -; add a1,a6,a7 -; add a2,t3,s6 -; add a3,s7,s8 -; add a4,s9,s10 -; add t4,s11,t4 -; add t0,t0,t1 -; add t1,t2,a0 -; add t2,a1,a2 -; add a0,a3,a4 +; add t3,a0,t3 ; add t4,t4,t0 ; add t0,t1,t2 -; add t4,a0,t4 -; add a0,t0,t4 +; add t1,a1,a2 +; add t2,a3,a4 +; add a0,a5,a6 +; add a1,a7,s5 +; add a2,s6,s7 +; add a3,s8,s9 +; add t3,s10,t3 +; add t4,t4,t0 +; add t0,t1,t2 +; add t1,a0,a1 +; add t2,a2,a3 +; add t3,t3,t4 +; add t4,t0,t1 +; add t3,t2,t3 +; add a0,t4,t3 ; add sp,+48 -; ld s6,-8(sp) -; ld s7,-16(sp) -; ld s8,-24(sp) -; ld s9,-32(sp) -; ld s10,-40(sp) -; ld s11,-48(sp) +; ld s5,-8(sp) +; ld s6,-16(sp) +; ld s7,-24(sp) +; ld s8,-32(sp) +; ld s9,-40(sp) +; ld s10,-48(sp) ; ld ra,8(sp) ; ld fp,0(sp) ; add sp,+16 diff --git a/cranelift/filetests/filetests/isa/riscv64/reftypes.clif b/cranelift/filetests/filetests/isa/riscv64/reftypes.clif index d3f903a57b..56cf5b83d6 100644 --- a/cranelift/filetests/filetests/isa/riscv64/reftypes.clif +++ b/cranelift/filetests/filetests/isa/riscv64/reftypes.clif @@ -65,38 +65,38 @@ block3(v7: r64, v8: r64): ; sd ra,8(sp) ; sd fp,0(sp) ; mv fp,sp -; sd s10,-8(sp) +; sd s7,-8(sp) ; add sp,-48 ; block0: ; sd a0,8(nominal_sp) ; sd a1,16(nominal_sp) -; mv s10,a2 -; load_sym a4,%f+0 -; callind a4 -; load_addr a3,nsp+0 -; ld t2,8(nominal_sp) -; sd t2,0(a3) -; andi a4,a0,255 -; beq a4,zero,taken(label1),not_taken(label3) +; mv s7,a2 +; load_sym a1,%f+0 +; callind a1 +; load_addr a1,nsp+0 +; ld t4,8(nominal_sp) +; sd t4,0(a1) +; andi a1,a0,255 +; beq a1,zero,taken(label1),not_taken(label3) ; block1: ; j label2 ; block2: -; mv a1,t2 +; mv a1,t4 ; ld a0,16(nominal_sp) ; j label5 ; block3: ; j label4 ; block4: -; mv a0,t2 +; mv a0,t4 ; ld a1,16(nominal_sp) ; j label5 ; block5: -; load_addr a5,nsp+0 -; ld a5,0(a5) -; mv a2,s10 -; sd a5,0(a2) +; load_addr a2,nsp+0 +; ld a2,0(a2) +; mv a3,s7 +; sd a2,0(a3) ; add sp,+48 -; ld s10,-8(sp) +; ld s7,-8(sp) ; ld ra,8(sp) ; ld fp,0(sp) ; add sp,+16 diff --git a/cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif b/cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif index 3ba647fecb..9ae1ea4b1f 100644 --- a/cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif +++ b/cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif @@ -13,20 +13,20 @@ block0(v0: i128, v1: i128): } ; block0: -; andi a4,a2,127 -; li a6,128 -; sub a6,a6,a4 -; srl t4,a0,a4 -; sll t1,a1,a6 -; select_reg a2,zero,t1##condition=(a4 eq zero) -; or a2,t4,a2 -; srl a5,a1,a4 -; sll a6,a0,a6 -; select_reg t3,zero,a6##condition=(a4 eq zero) -; or t0,a5,t3 -; li t2,64 -; select_reg a0,t0,a2##condition=(a4 uge t2) -; select_reg a1,a2,t0##condition=(a4 uge t2) +; andi a2,a2,127 +; li a4,128 +; sub a4,a4,a2 +; srl a7,a0,a2 +; sll t4,a1,a4 +; select_reg t1,zero,t4##condition=(a2 eq zero) +; or a3,a7,t1 +; srl a5,a1,a2 +; sll a4,a0,a4 +; select_reg a6,zero,a4##condition=(a2 eq zero) +; or t3,a5,a6 +; li t0,64 +; select_reg a0,t3,a3##condition=(a2 uge t0) +; select_reg a1,a3,t3##condition=(a2 uge t0) ; ret function %f0(i64, i64) -> i64 { @@ -36,13 +36,15 @@ block0(v0: i64, v1: i64): } ; block0: -; andi a1,a1,63 -; li a3,64 -; sub a3,a3,a1 -; srl a6,a0,a1 -; sll t3,a0,a3 -; select_reg t0,zero,t3##condition=(a1 eq zero) -; or a0,a6,t0 +; mv a6,a0 +; andi a0,a1,63 +; li a2,64 +; sub a2,a2,a0 +; mv t4,a6 +; srl a5,t4,a0 +; sll a7,t4,a2 +; select_reg t4,zero,a7##condition=(a0 eq zero) +; or a0,a5,t4 ; ret function %f1(i32, i32) -> i32 { @@ -52,14 +54,14 @@ block0(v0: i32, v1: i32): } ; block0: -; uext.w a2,a0 -; andi a3,a1,31 -; li a5,32 -; sub a5,a5,a3 -; srl t3,a2,a3 -; sll t0,a2,a5 -; select_reg t2,zero,t0##condition=(a3 eq zero) -; or a0,t3,t2 +; uext.w a0,a0 +; andi a2,a1,31 +; li a4,32 +; sub a4,a4,a2 +; srl a7,a0,a2 +; sll t4,a0,a4 +; select_reg t1,zero,t4##condition=(a2 eq zero) +; or a0,a7,t1 ; ret function %f2(i16, i16) -> i16 { @@ -69,14 +71,14 @@ block0(v0: i16, v1: i16): } ; block0: -; uext.h a2,a0 -; andi a3,a1,15 -; li a5,16 -; sub a5,a5,a3 -; srl t3,a2,a3 -; sll t0,a2,a5 -; select_reg t2,zero,t0##condition=(a3 eq zero) -; or a0,t3,t2 +; uext.h a0,a0 +; andi a2,a1,15 +; li a4,16 +; sub a4,a4,a2 +; srl a7,a0,a2 +; sll t4,a0,a4 +; select_reg t1,zero,t4##condition=(a2 eq zero) +; or a0,a7,t1 ; ret function %f3(i8, i8) -> i8 { @@ -86,14 +88,14 @@ block0(v0: i8, v1: i8): } ; block0: -; uext.b a2,a0 -; andi a3,a1,7 -; li a5,8 -; sub a5,a5,a3 -; srl t3,a2,a3 -; sll t0,a2,a5 -; select_reg t2,zero,t0##condition=(a3 eq zero) -; or a0,t3,t2 +; uext.b a0,a0 +; andi a2,a1,7 +; li a4,8 +; sub a4,a4,a2 +; srl a7,a0,a2 +; sll t4,a0,a4 +; select_reg t1,zero,t4##condition=(a2 eq zero) +; or a0,a7,t1 ; ret function %i128_rotl(i128, i128) -> i128 { @@ -103,20 +105,20 @@ block0(v0: i128, v1: i128): } ; block0: -; andi a4,a2,127 -; li a6,128 -; sub a6,a6,a4 -; sll t4,a0,a4 -; srl t1,a1,a6 -; select_reg a2,zero,t1##condition=(a4 eq zero) -; or a2,t4,a2 -; sll a5,a1,a4 -; srl a6,a0,a6 -; select_reg t3,zero,a6##condition=(a4 eq zero) -; or t0,a5,t3 -; li t2,64 -; select_reg a0,t0,a2##condition=(a4 uge t2) -; select_reg a1,a2,t0##condition=(a4 uge t2) +; andi a2,a2,127 +; li a4,128 +; sub a4,a4,a2 +; sll a7,a0,a2 +; srl t4,a1,a4 +; select_reg t1,zero,t4##condition=(a2 eq zero) +; or a3,a7,t1 +; sll a5,a1,a2 +; srl a4,a0,a4 +; select_reg a6,zero,a4##condition=(a2 eq zero) +; or t3,a5,a6 +; li t0,64 +; select_reg a0,t3,a3##condition=(a2 uge t0) +; select_reg a1,a3,t3##condition=(a2 uge t0) ; ret function %f4(i64, i64) -> i64 { @@ -126,13 +128,15 @@ block0(v0: i64, v1: i64): } ; block0: -; andi a1,a1,63 -; li a3,64 -; sub a3,a3,a1 -; sll a6,a0,a1 -; srl t3,a0,a3 -; select_reg t0,zero,t3##condition=(a1 eq zero) -; or a0,a6,t0 +; mv a6,a0 +; andi a0,a1,63 +; li a2,64 +; sub a2,a2,a0 +; mv t4,a6 +; sll a5,t4,a0 +; srl a7,t4,a2 +; select_reg t4,zero,a7##condition=(a0 eq zero) +; or a0,a5,t4 ; ret function %f5(i32, i32) -> i32 { @@ -142,14 +146,14 @@ block0(v0: i32, v1: i32): } ; block0: -; uext.w a2,a0 -; andi a3,a1,31 -; li a5,32 -; sub a5,a5,a3 -; sll t3,a2,a3 -; srl t0,a2,a5 -; select_reg t2,zero,t0##condition=(a3 eq zero) -; or a0,t3,t2 +; uext.w a0,a0 +; andi a2,a1,31 +; li a4,32 +; sub a4,a4,a2 +; sll a7,a0,a2 +; srl t4,a0,a4 +; select_reg t1,zero,t4##condition=(a2 eq zero) +; or a0,a7,t1 ; ret function %f6(i16, i16) -> i16 { @@ -159,14 +163,14 @@ block0(v0: i16, v1: i16): } ; block0: -; uext.h a2,a0 -; andi a3,a1,15 -; li a5,16 -; sub a5,a5,a3 -; sll t3,a2,a3 -; srl t0,a2,a5 -; select_reg t2,zero,t0##condition=(a3 eq zero) -; or a0,t3,t2 +; uext.h a0,a0 +; andi a2,a1,15 +; li a4,16 +; sub a4,a4,a2 +; sll a7,a0,a2 +; srl t4,a0,a4 +; select_reg t1,zero,t4##condition=(a2 eq zero) +; or a0,a7,t1 ; ret function %f7(i8, i8) -> i8 { @@ -176,14 +180,14 @@ block0(v0: i8, v1: i8): } ; block0: -; uext.b a2,a0 -; andi a3,a1,7 -; li a5,8 -; sub a5,a5,a3 -; sll t3,a2,a3 -; srl t0,a2,a5 -; select_reg t2,zero,t0##condition=(a3 eq zero) -; or a0,t3,t2 +; uext.b a0,a0 +; andi a2,a1,7 +; li a4,8 +; sub a4,a4,a2 +; sll a7,a0,a2 +; srl t4,a0,a4 +; select_reg t1,zero,t4##condition=(a2 eq zero) +; or a0,a7,t1 ; ret function %f8(i64, i64) -> i64 { @@ -213,10 +217,9 @@ block0(v0: i16, v1: i16): } ; block0: -; mv a5,a1 -; uext.h a1,a0 -; andi a3,a5,15 -; srlw a0,a1,a3 +; uext.h a0,a0 +; andi a2,a1,15 +; srlw a0,a0,a2 ; ret function %f11(i8, i8) -> i8 { @@ -226,10 +229,9 @@ block0(v0: i8, v1: i8): } ; block0: -; mv a5,a1 -; uext.b a1,a0 -; andi a3,a5,7 -; srlw a0,a1,a3 +; uext.b a0,a0 +; andi a2,a1,7 +; srlw a0,a0,a2 ; ret function %f12(i64, i64) -> i64 { @@ -301,10 +303,9 @@ block0(v0: i16, v1: i16): } ; block0: -; mv a5,a1 -; sext.h a1,a0 -; andi a3,a5,15 -; sra a0,a1,a3 +; sext.h a0,a0 +; andi a2,a1,15 +; sra a0,a0,a2 ; ret function %f19(i8, i8) -> i8 { @@ -314,10 +315,9 @@ block0(v0: i8, v1: i8): } ; block0: -; mv a5,a1 -; sext.b a1,a0 -; andi a3,a5,7 -; sra a0,a1,a3 +; sext.b a0,a0 +; andi a2,a1,7 +; sra a0,a0,a2 ; ret function %f20(i64) -> i64 { @@ -328,14 +328,14 @@ block0(v0: i64): } ; block0: -; li a1,17 -; andi a2,a1,63 -; li a4,64 -; sub a4,a4,a2 -; srl a7,a0,a2 -; sll t4,a0,a4 -; select_reg t1,zero,t4##condition=(a2 eq zero) -; or a0,a7,t1 +; li t2,17 +; andi a1,t2,63 +; li a3,64 +; sub a3,a3,a1 +; srl a6,a0,a1 +; sll t3,a0,a3 +; select_reg t0,zero,t3##condition=(a1 eq zero) +; or a0,a6,t0 ; ret function %f21(i64) -> i64 { @@ -346,14 +346,14 @@ block0(v0: i64): } ; block0: -; li a1,17 -; andi a2,a1,63 -; li a4,64 -; sub a4,a4,a2 -; sll a7,a0,a2 -; srl t4,a0,a4 -; select_reg t1,zero,t4##condition=(a2 eq zero) -; or a0,a7,t1 +; li t2,17 +; andi a1,t2,63 +; li a3,64 +; sub a3,a3,a1 +; sll a6,a0,a1 +; srl t3,a0,a3 +; select_reg t0,zero,t3##condition=(a1 eq zero) +; or a0,a6,t0 ; ret function %f22(i32) -> i32 { @@ -364,16 +364,15 @@ block0(v0: i32): } ; block0: -; mv t4,a0 -; li a0,17 -; uext.w a2,t4 -; andi a4,a0,31 -; li a6,32 -; sub a6,a6,a4 -; sll t4,a2,a4 -; srl t1,a2,a6 -; select_reg a0,zero,t1##condition=(a4 eq zero) -; or a0,t4,a0 +; li t2,17 +; uext.w a1,a0 +; andi a3,t2,31 +; li a5,32 +; sub a5,a5,a3 +; sll t3,a1,a3 +; srl t0,a1,a5 +; select_reg t2,zero,t0##condition=(a3 eq zero) +; or a0,t3,t2 ; ret function %f23(i16) -> i16 { @@ -384,16 +383,15 @@ block0(v0: i16): } ; block0: -; mv t4,a0 -; li a0,10 -; uext.h a2,t4 -; andi a4,a0,15 -; li a6,16 -; sub a6,a6,a4 -; sll t4,a2,a4 -; srl t1,a2,a6 -; select_reg a0,zero,t1##condition=(a4 eq zero) -; or a0,t4,a0 +; li t2,10 +; uext.h a1,a0 +; andi a3,t2,15 +; li a5,16 +; sub a5,a5,a3 +; sll t3,a1,a3 +; srl t0,a1,a5 +; select_reg t2,zero,t0##condition=(a3 eq zero) +; or a0,t3,t2 ; ret function %f24(i8) -> i8 { @@ -404,16 +402,15 @@ block0(v0: i8): } ; block0: -; mv t4,a0 -; li a0,3 -; uext.b a2,t4 -; andi a4,a0,7 -; li a6,8 -; sub a6,a6,a4 -; sll t4,a2,a4 -; srl t1,a2,a6 -; select_reg a0,zero,t1##condition=(a4 eq zero) -; or a0,t4,a0 +; li t2,3 +; uext.b a1,a0 +; andi a3,t2,7 +; li a5,8 +; sub a5,a5,a3 +; sll t3,a1,a3 +; srl t0,a1,a5 +; select_reg t2,zero,t0##condition=(a3 eq zero) +; or a0,t3,t2 ; ret function %f25(i64) -> i64 { diff --git a/cranelift/filetests/filetests/isa/riscv64/stack.clif b/cranelift/filetests/filetests/isa/riscv64/stack.clif index 1045b4380b..c5073cf78c 100644 --- a/cranelift/filetests/filetests/isa/riscv64/stack.clif +++ b/cranelift/filetests/filetests/isa/riscv64/stack.clif @@ -62,8 +62,8 @@ block0: ; mv fp,sp ; add sp,-16 ; block0: -; load_addr t2,nsp+0 -; ld a0,0(t2) +; load_addr t1,nsp+0 +; ld a0,0(t1) ; add sp,+16 ; ld ra,8(sp) ; ld fp,0(sp) @@ -88,8 +88,8 @@ block0: ; call %Probestack ; add sp,-100016 ; block0: -; load_addr t2,nsp+0 -; ld a0,0(t2) +; load_addr t1,nsp+0 +; ld a0,0(t1) ; add sp,+100016 ; ld ra,8(sp) ; ld fp,0(sp) @@ -313,152 +313,152 @@ block0(v0: i8): ; add sp,-1280 ; block0: ; sd a0,1000(nominal_sp) -; li t0,2 -; addi a1,t0,1 -; sd a1,1176(nominal_sp) -; li t0,4 -; addi a2,t0,3 -; sd a2,1168(nominal_sp) -; li t0,6 -; addi a3,t0,5 -; sd a3,1160(nominal_sp) -; li t0,8 -; addi a4,t0,7 -; sd a4,1152(nominal_sp) -; li t0,10 -; addi a5,t0,9 -; sd a5,1144(nominal_sp) -; li t0,12 -; addi a6,t0,11 -; sd a6,1136(nominal_sp) -; li t0,14 -; addi a7,t0,13 -; sd a7,1128(nominal_sp) -; li t0,16 -; addi t3,t0,15 -; sd t3,1120(nominal_sp) -; li t0,18 -; addi t4,t0,17 -; sd t4,1112(nominal_sp) -; li t0,20 -; addi t0,t0,19 -; sd t0,1104(nominal_sp) -; li t0,22 -; addi t1,t0,21 -; sd t1,1096(nominal_sp) -; li t0,24 -; addi s8,t0,23 -; sd s8,1088(nominal_sp) -; li t0,26 -; addi s9,t0,25 -; sd s9,1080(nominal_sp) -; li t0,28 -; addi s10,t0,27 -; sd s10,1072(nominal_sp) -; li t0,30 -; addi s11,t0,29 -; sd s11,1064(nominal_sp) -; li t0,32 -; addi s1,t0,31 -; sd s1,1056(nominal_sp) -; li t0,34 -; addi s2,t0,33 -; sd s2,1048(nominal_sp) -; li t0,36 -; addi s3,t0,35 -; sd s3,1040(nominal_sp) -; li t0,38 -; addi s4,t0,37 -; sd s4,1032(nominal_sp) -; li t0,30 -; addi s5,t0,39 -; sd s5,1024(nominal_sp) -; li t0,32 -; addi s6,t0,31 -; sd s6,1016(nominal_sp) -; li t0,34 -; addi s7,t0,33 -; sd s7,1008(nominal_sp) -; li t0,36 -; addi s7,t0,35 -; li t0,38 -; addi a0,t0,37 -; li t0,30 -; addi t2,t0,39 -; li t0,32 -; addi a1,t0,31 -; li t0,34 -; addi a2,t0,33 -; li t0,36 -; addi a3,t0,35 -; li t0,38 -; addi a4,t0,37 -; li t0,30 -; addi a5,t0,39 -; li t0,32 -; addi a6,t0,31 -; li t0,34 -; addi a7,t0,33 -; li t0,36 -; addi t3,t0,35 -; li t0,38 -; addi t4,t0,37 -; ld t0,1176(nominal_sp) -; addi t0,t0,39 -; ld t1,1160(nominal_sp) -; ld s4,1168(nominal_sp) -; add t1,s4,t1 -; ld s11,1144(nominal_sp) -; ld s9,1152(nominal_sp) -; add s8,s9,s11 -; ld s5,1128(nominal_sp) -; ld s3,1136(nominal_sp) -; add s9,s3,s5 -; ld s10,1112(nominal_sp) -; ld s11,1120(nominal_sp) +; li t3,2 +; addi t1,t3,1 +; sd t1,1176(nominal_sp) +; li t3,4 +; addi t2,t3,3 +; sd t2,1168(nominal_sp) +; li t3,6 +; addi a1,t3,5 +; sd a1,1160(nominal_sp) +; li t3,8 +; addi a2,t3,7 +; sd a2,1152(nominal_sp) +; li t3,10 +; addi a3,t3,9 +; sd a3,1144(nominal_sp) +; li t3,12 +; addi a4,t3,11 +; sd a4,1136(nominal_sp) +; li t3,14 +; addi a5,t3,13 +; sd a5,1128(nominal_sp) +; li t3,16 +; addi a6,t3,15 +; sd a6,1120(nominal_sp) +; li t3,18 +; addi a7,t3,17 +; sd a7,1112(nominal_sp) +; li t3,20 +; addi t3,t3,19 +; sd t3,1104(nominal_sp) +; li t3,22 +; addi t4,t3,21 +; sd t4,1096(nominal_sp) +; li t3,24 +; addi s6,t3,23 +; sd s6,1088(nominal_sp) +; li t3,26 +; addi s7,t3,25 +; sd s7,1080(nominal_sp) +; li t3,28 +; addi s8,t3,27 +; sd s8,1072(nominal_sp) +; li t3,30 +; addi s9,t3,29 +; sd s9,1064(nominal_sp) +; li t3,32 +; addi s10,t3,31 +; sd s10,1056(nominal_sp) +; li t3,34 +; addi s11,t3,33 +; sd s11,1048(nominal_sp) +; li t3,36 +; addi s1,t3,35 +; sd s1,1040(nominal_sp) +; li t3,38 +; addi s2,t3,37 +; sd s2,1032(nominal_sp) +; li t3,30 +; addi s3,t3,39 +; sd s3,1024(nominal_sp) +; li t3,32 +; addi s4,t3,31 +; sd s4,1016(nominal_sp) +; li t3,34 +; addi s5,t3,33 +; sd s5,1008(nominal_sp) +; li t3,36 +; addi s5,t3,35 +; li t3,38 +; addi a0,t3,37 +; li t3,30 +; addi t0,t3,39 +; li t3,32 +; addi t1,t3,31 +; li t3,34 +; addi t2,t3,33 +; li t3,36 +; addi a1,t3,35 +; li t3,38 +; addi a2,t3,37 +; li t3,30 +; addi a3,t3,39 +; li t3,32 +; addi a4,t3,31 +; li t3,34 +; addi a5,t3,33 +; li t3,36 +; addi a6,t3,35 +; li t3,38 +; addi a7,t3,37 +; ld t3,1176(nominal_sp) +; addi t3,t3,39 +; ld t4,1160(nominal_sp) +; ld s2,1168(nominal_sp) +; add t4,s2,t4 +; ld s9,1144(nominal_sp) +; ld s7,1152(nominal_sp) +; add s6,s7,s9 +; ld s3,1128(nominal_sp) +; ld s1,1136(nominal_sp) +; add s7,s1,s3 +; ld s8,1112(nominal_sp) +; ld s9,1120(nominal_sp) +; add s8,s9,s8 +; ld s2,1096(nominal_sp) +; ld s11,1104(nominal_sp) +; add s9,s11,s2 +; ld s10,1080(nominal_sp) +; ld s11,1088(nominal_sp) ; add s10,s11,s10 -; ld s4,1096(nominal_sp) -; ld s2,1104(nominal_sp) -; add s11,s2,s4 -; ld s1,1080(nominal_sp) -; ld s2,1088(nominal_sp) -; add s1,s2,s1 -; ld s3,1064(nominal_sp) -; ld s2,1072(nominal_sp) -; add s2,s2,s3 -; ld s3,1048(nominal_sp) -; ld s6,1056(nominal_sp) -; add s3,s6,s3 -; ld s4,1032(nominal_sp) -; ld s5,1040(nominal_sp) -; add s4,s5,s4 -; ld s6,1016(nominal_sp) -; ld s5,1024(nominal_sp) -; add s5,s5,s6 -; ld s6,1008(nominal_sp) -; add s7,s6,s7 -; add t2,a0,t2 -; add a0,a1,a2 -; add a1,a3,a4 -; add a2,a5,a6 -; add a3,a7,t3 -; add a4,t4,t0 -; add t1,t1,s8 -; add a5,s9,s10 -; add a6,s11,s1 -; add a7,s2,s3 -; add t3,s4,s5 -; add t2,s7,t2 -; add a0,a0,a1 -; add a1,a2,a3 -; add t1,a4,t1 -; add a2,a5,a6 -; add a3,a7,t3 -; add t2,t2,a0 -; add t1,a1,t1 -; add a0,a2,a3 -; add t1,t2,t1 -; add a1,a0,t1 +; ld s1,1064(nominal_sp) +; ld s11,1072(nominal_sp) +; add s11,s11,s1 +; ld s1,1048(nominal_sp) +; ld s4,1056(nominal_sp) +; add s1,s4,s1 +; ld s2,1032(nominal_sp) +; ld s3,1040(nominal_sp) +; add s2,s3,s2 +; ld s4,1016(nominal_sp) +; ld s3,1024(nominal_sp) +; add s3,s3,s4 +; ld s4,1008(nominal_sp) +; add s5,s4,s5 +; add t0,a0,t0 +; add t1,t1,t2 +; add t2,a1,a2 +; add a0,a3,a4 +; add a1,a5,a6 +; add a2,a7,t3 +; add t4,t4,s6 +; add a3,s7,s8 +; add a4,s9,s10 +; add a5,s11,s1 +; add a6,s2,s3 +; add t0,s5,t0 +; add t1,t1,t2 +; add t2,a0,a1 +; add t4,a2,t4 +; add a0,a3,a4 +; add a1,a5,a6 +; add t0,t0,t1 +; add t4,t2,t4 +; add t1,a0,a1 +; add t4,t0,t4 +; add a1,t1,t4 ; ld a0,1000(nominal_sp) ; add sp,+1280 ; ld s1,-8(sp) @@ -568,9 +568,9 @@ block0: ; mv fp,sp ; add sp,-16 ; block0: -; load_addr a1,nsp+0 -; ld a0,0(a1) -; ld a1,8(a1) +; load_addr t2,nsp+0 +; ld a0,0(t2) +; ld a1,8(t2) ; add sp,+16 ; ld ra,8(sp) ; ld fp,0(sp) @@ -592,9 +592,9 @@ block0: ; mv fp,sp ; add sp,-32 ; block0: -; load_addr a1,nsp+32 -; ld a0,0(a1) -; ld a1,8(a1) +; load_addr t2,nsp+32 +; ld a0,0(t2) +; ld a1,8(t2) ; add sp,+32 ; ld ra,8(sp) ; ld fp,0(sp) @@ -619,9 +619,9 @@ block0: ; call %Probestack ; add sp,-100016 ; block0: -; load_addr a1,nsp+0 -; ld a0,0(a1) -; ld a1,8(a1) +; load_addr t2,nsp+0 +; ld a0,0(t2) +; ld a1,8(t2) ; add sp,+100016 ; ld ra,8(sp) ; ld fp,0(sp) diff --git a/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif b/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif index 231f066fe4..e65998f284 100644 --- a/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif +++ b/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif @@ -9,13 +9,12 @@ block0(v0: i32): } ; block0: -; mv a6,a0 -; li a0,127 -; uext.w a2,a6 -; uext.w a4,a0 -; add a0,a2,a4 -; srli t3,a0,32 -; trap_if t3,user0 +; li t2,127 +; uext.w a1,a0 +; uext.w a3,t2 +; add a0,a1,a3 +; srli a7,a0,32 +; trap_if a7,user0 ; ret function %f1(i32) -> i32 { @@ -26,12 +25,12 @@ block0(v0: i32): } ; block0: -; li a1,127 -; uext.w a2,a1 -; uext.w a4,a0 -; add a0,a2,a4 -; srli t3,a0,32 -; trap_if t3,user0 +; li t2,127 +; uext.w a1,t2 +; uext.w a3,a0 +; add a0,a1,a3 +; srli a7,a0,32 +; trap_if a7,user0 ; ret function %f2(i32, i32) -> i32 { @@ -41,12 +40,11 @@ block0(v0: i32, v1: i32): } ; block0: -; mv a6,a1 -; uext.w a1,a0 -; uext.w a3,a6 -; add a0,a1,a3 -; srli a7,a0,32 -; trap_if a7,user0 +; uext.w a0,a0 +; uext.w a2,a1 +; add a0,a0,a2 +; srli a6,a0,32 +; trap_if a6,user0 ; ret function %f3(i64) -> i64 { @@ -57,13 +55,11 @@ block0(v0: i64): } ; block0: -; li a1,127 -; add a2,a0,a1 -; mv a5,a2 -; ult a4,a5,a0##ty=i64 -; mv a2,a5 -; trap_if a4,user0 -; mv a0,a2 +; mv a4,a0 +; li t2,127 +; add a0,a4,t2 +; ult a3,a0,a4##ty=i64 +; trap_if a3,user0 ; ret function %f3(i64) -> i64 { @@ -74,10 +70,10 @@ block0(v0: i64): } ; block0: -; li a1,127 -; add a0,a1,a0 -; ult a4,a0,a1##ty=i64 -; trap_if a4,user0 +; li t2,127 +; add a0,t2,a0 +; ult a3,a0,t2##ty=i64 +; trap_if a3,user0 ; ret function %f4(i64, i64) -> i64 { @@ -88,10 +84,9 @@ block0(v0: i64, v1: i64): ; block0: ; add a1,a0,a1 -; mv a4,a1 -; ult a3,a4,a0##ty=i64 -; mv a1,a4 -; trap_if a3,user0 -; mv a0,a1 +; mv a3,a1 +; ult a2,a3,a0##ty=i64 +; mv a0,a3 +; trap_if a2,user0 ; ret diff --git a/cranelift/filetests/filetests/isa/s390x/arithmetic.clif b/cranelift/filetests/filetests/isa/s390x/arithmetic.clif index 2fef9e1cc0..17b76ce554 100644 --- a/cranelift/filetests/filetests/isa/s390x/arithmetic.clif +++ b/cranelift/filetests/filetests/isa/s390x/arithmetic.clif @@ -10,8 +10,8 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vaq %v7, %v0, %v1 -; vst %v7, 0(%r2) +; vaq %v6, %v0, %v1 +; vst %v6, 0(%r2) ; br %r14 function %iadd_i64(i64, i64) -> i64 { @@ -341,8 +341,8 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vsq %v7, %v0, %v1 -; vst %v7, 0(%r2) +; vsq %v6, %v0, %v1 +; vst %v6, 0(%r2) ; br %r14 function %isub_i64(i64, i64) -> i64 { @@ -570,12 +570,12 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vgbm %v5, 0 -; vsq %v7, %v5, %v0 -; vrepg %v17, %v0, 0 -; vchg %v19, %v5, %v17 -; vsel %v21, %v7, %v0, %v19 -; vst %v21, 0(%r2) +; vgbm %v4, 0 +; vsq %v6, %v4, %v0 +; vrepg %v16, %v0, 0 +; vchg %v18, %v4, %v16 +; vsel %v20, %v6, %v0, %v18 +; vst %v20, 0(%r2) ; br %r14 function %iabs_i64(i64) -> i64 { @@ -616,8 +616,8 @@ block0(v0: i16): } ; block0: -; lhr %r5, %r2 -; lpr %r2, %r5 +; lhr %r4, %r2 +; lpr %r2, %r4 ; br %r14 function %iabs_i8(i8) -> i8 { @@ -627,8 +627,8 @@ block0(v0: i8): } ; block0: -; lbr %r5, %r2 -; lpr %r2, %r5 +; lbr %r4, %r2 +; lpr %r2, %r4 ; br %r14 function %ineg_i128(i128) -> i128 { @@ -639,9 +639,9 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vgbm %v5, 0 -; vsq %v7, %v5, %v0 -; vst %v7, 0(%r2) +; vgbm %v4, 0 +; vsq %v6, %v4, %v0 +; vst %v6, 0(%r2) ; br %r14 function %ineg_i64(i64) -> i64 { @@ -701,26 +701,26 @@ block0(v0: i128, v1: i128): return v2 } -; stmg %r6, %r15, 48(%r15) +; stmg %r7, %r15, 56(%r15) ; block0: -; lgr %r6, %r2 +; lgr %r14, %r2 ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; lgdr %r5, %f0 -; vlgvg %r4, %v0, 1 -; lgdr %r8, %f1 -; vlgvg %r10, %v1, 1 -; lgr %r3, %r4 -; mlgr %r2, %r10 -; lgr %r9, %r2 -; msgr %r4, %r8 -; msgrkc %r2, %r5, %r10 -; agr %r4, %r9 -; agr %r2, %r4 -; vlvgp %v6, %r2, %r3 -; lgr %r2, %r6 -; vst %v6, 0(%r2) -; lmg %r6, %r15, 48(%r15) +; lgdr %r4, %f0 +; vlgvg %r5, %v0, 1 +; lgdr %r7, %f1 +; vlgvg %r9, %v1, 1 +; lgr %r3, %r5 +; mlgr %r2, %r9 +; lgr %r8, %r2 +; msgrkc %r2, %r5, %r7 +; msgrkc %r5, %r4, %r9 +; agrk %r4, %r2, %r8 +; agr %r5, %r4 +; vlvgp %v5, %r5, %r3 +; lgr %r2, %r14 +; vst %v5, 0(%r2) +; lmg %r7, %r15, 56(%r15) ; br %r14 function %imul_i64(i64, i64) -> i64 { @@ -936,10 +936,9 @@ block0(v0: i64, v1: i64): } ; block0: -; lgr %r4, %r2 -; lgr %r2, %r3 -; lgr %r3, %r4 -; mlgr %r2, %r2 +; lgr %r5, %r3 +; lgr %r3, %r2 +; mlgr %r2, %r5 ; br %r14 function %umulhi_i32(i32, i32) -> i32 { @@ -949,10 +948,10 @@ block0(v0: i32, v1: i32): } ; block0: -; llgfr %r2, %r2 -; llgfr %r4, %r3 -; msgr %r2, %r4 -; srlg %r2, %r2, 32 +; llgfr %r5, %r2 +; llgfr %r3, %r3 +; msgr %r5, %r3 +; srlg %r2, %r5, 32 ; br %r14 function %umulhi_i16(i16, i16) -> i16 { @@ -962,10 +961,10 @@ block0(v0: i16, v1: i16): } ; block0: -; llhr %r2, %r2 -; llhr %r4, %r3 -; msr %r2, %r4 -; srlk %r2, %r2, 16 +; llhr %r5, %r2 +; llhr %r3, %r3 +; msr %r5, %r3 +; srlk %r2, %r5, 16 ; br %r14 function %umulhi_i8(i8, i8) -> i8 { @@ -975,10 +974,10 @@ block0(v0: i8, v1: i8): } ; block0: -; llcr %r2, %r2 -; llcr %r4, %r3 -; msr %r2, %r4 -; srlk %r2, %r2, 8 +; llcr %r5, %r2 +; llcr %r3, %r3 +; msr %r5, %r3 +; srlk %r2, %r5, 8 ; br %r14 function %smulhi_i64(i64, i64) -> i64 { @@ -998,10 +997,10 @@ block0(v0: i32, v1: i32): } ; block0: -; lgfr %r2, %r2 -; lgfr %r4, %r3 -; msgr %r2, %r4 -; srag %r2, %r2, 32 +; lgfr %r5, %r2 +; lgfr %r3, %r3 +; msgr %r5, %r3 +; srag %r2, %r5, 32 ; br %r14 function %smulhi_i16(i16, i16) -> i16 { @@ -1011,10 +1010,10 @@ block0(v0: i16, v1: i16): } ; block0: -; lhr %r2, %r2 -; lhr %r4, %r3 -; msr %r2, %r4 -; srak %r2, %r2, 16 +; lhr %r5, %r2 +; lhr %r3, %r3 +; msr %r5, %r3 +; srak %r2, %r5, 16 ; br %r14 function %smulhi_i8(i8, i8) -> i8 { @@ -1024,10 +1023,10 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r2 -; lbr %r4, %r3 -; msr %r2, %r4 -; srak %r2, %r2, 8 +; lbr %r5, %r2 +; lbr %r3, %r3 +; msr %r5, %r3 +; srak %r2, %r5, 8 ; br %r14 function %sdiv_i64(i64, i64) -> i64 { @@ -1039,12 +1038,11 @@ block0(v0: i64, v1: i64): ; block0: ; llihf %r4, 2147483647 ; iilf %r4, 4294967295 -; xgr %r4, %r2 -; lgr %r5, %r2 -; ngr %r4, %r3 +; xgrk %r5, %r4, %r2 +; ngrk %r4, %r5, %r3 ; cgite %r4, -1 ; lgr %r4, %r3 -; lgr %r3, %r5 +; lgr %r3, %r2 ; dsgr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -1058,8 +1056,8 @@ block0(v0: i64): ; block0: ; lgr %r3, %r2 -; lghi %r5, 2 -; dsgr %r2, %r5 +; lghi %r4, 2 +; dsgr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -1069,16 +1067,18 @@ block0(v0: i32, v1: i32): return v2 } +; stmg %r7, %r15, 56(%r15) ; block0: -; lgr %r5, %r3 +; lgr %r7, %r3 ; lgfr %r3, %r2 ; iilf %r4, 2147483647 -; xrk %r2, %r4, %r3 -; lgr %r4, %r5 -; nrk %r5, %r2, %r4 +; xrk %r5, %r4, %r3 +; lgr %r4, %r7 +; nr %r5, %r4 ; cite %r5, -1 ; dsgfr %r2, %r4 ; lgr %r2, %r3 +; lmg %r7, %r15, 56(%r15) ; br %r14 function %sdiv_i32_imm(i32) -> i32 { @@ -1090,8 +1090,8 @@ block0(v0: i32): ; block0: ; lgfr %r3, %r2 -; lhi %r4, 2 -; dsgfr %r2, %r4 +; lhi %r2, 2 +; dsgfr %r2, %r2 ; lgr %r2, %r3 ; br %r14 @@ -1102,14 +1102,14 @@ block0(v0: i16, v1: i16): } ; block0: -; lghr %r2, %r2 -; lgr %r5, %r2 +; lghr %r5, %r2 +; lgr %r2, %r5 ; lhr %r4, %r3 -; lhi %r2, 32767 -; lgr %r3, %r5 -; xrk %r5, %r2, %r3 -; nrk %r2, %r5, %r4 -; cite %r2, -1 +; lhi %r5, 32767 +; lgr %r3, %r2 +; xr %r5, %r3 +; nr %r5, %r4 +; cite %r5, -1 ; dsgfr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -1123,8 +1123,8 @@ block0(v0: i16): ; block0: ; lghr %r3, %r2 -; lhi %r4, 2 -; dsgfr %r2, %r4 +; lhi %r2, 2 +; dsgfr %r2, %r2 ; lgr %r2, %r3 ; br %r14 @@ -1135,14 +1135,14 @@ block0(v0: i8, v1: i8): } ; block0: -; lgbr %r2, %r2 -; lgr %r5, %r2 +; lgbr %r5, %r2 +; lgr %r2, %r5 ; lbr %r4, %r3 -; lhi %r2, 127 -; lgr %r3, %r5 -; xrk %r5, %r2, %r3 -; nrk %r2, %r5, %r4 -; cite %r2, -1 +; lhi %r5, 127 +; lgr %r3, %r2 +; xr %r5, %r3 +; nr %r5, %r4 +; cite %r5, -1 ; dsgfr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -1156,8 +1156,8 @@ block0(v0: i8): ; block0: ; lgbr %r3, %r2 -; lhi %r4, 2 -; dsgfr %r2, %r4 +; lhi %r2, 2 +; dsgfr %r2, %r2 ; lgr %r2, %r3 ; br %r14 @@ -1168,10 +1168,10 @@ block0(v0: i64, v1: i64): } ; block0: -; lgr %r5, %r3 +; lgr %r4, %r3 ; lgr %r3, %r2 ; lghi %r2, 0 -; dlgr %r2, %r5 +; dlgr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -1197,10 +1197,10 @@ block0(v0: i32, v1: i32): } ; block0: -; lgr %r5, %r3 +; lgr %r4, %r3 ; lgr %r3, %r2 ; lhi %r2, 0 -; dlr %r2, %r5 +; dlr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -1225,16 +1225,18 @@ block0(v0: i16, v1: i16): return v2 } +; stmg %r8, %r15, 64(%r15) ; block0: ; lgr %r4, %r3 -; lhi %r3, 0 -; lgr %r5, %r3 +; lhi %r5, 0 +; lgr %r8, %r5 ; llhr %r3, %r2 -; lgr %r2, %r4 -; llhr %r4, %r2 -; lgr %r2, %r5 -; dlr %r2, %r4 +; lgr %r5, %r4 +; llhr %r5, %r5 +; lgr %r2, %r8 +; dlr %r2, %r5 ; lgr %r2, %r3 +; lmg %r8, %r15, 64(%r15) ; br %r14 function %udiv_i16_imm(i16) -> i16 { @@ -1245,12 +1247,12 @@ block0(v0: i16): } ; block0: -; lhi %r5, 0 -; lgr %r4, %r5 +; lhi %r4, 0 +; lgr %r5, %r4 ; llhr %r3, %r2 -; lhi %r5, 2 -; lgr %r2, %r4 -; dlr %r2, %r5 +; lhi %r4, 2 +; lgr %r2, %r5 +; dlr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -1260,16 +1262,18 @@ block0(v0: i8, v1: i8): return v2 } +; stmg %r8, %r15, 64(%r15) ; block0: ; lgr %r4, %r3 -; lhi %r3, 0 -; lgr %r5, %r3 +; lhi %r5, 0 +; lgr %r8, %r5 ; llcr %r3, %r2 -; lgr %r2, %r4 -; llcr %r4, %r2 -; lgr %r2, %r5 -; dlr %r2, %r4 +; lgr %r5, %r4 +; llcr %r5, %r5 +; lgr %r2, %r8 +; dlr %r2, %r5 ; lgr %r2, %r3 +; lmg %r8, %r15, 64(%r15) ; br %r14 function %udiv_i8_imm(i8) -> i8 { @@ -1280,12 +1284,12 @@ block0(v0: i8): } ; block0: -; lhi %r5, 0 -; lgr %r4, %r5 +; lhi %r4, 0 +; lgr %r5, %r4 ; llcr %r3, %r2 -; lhi %r5, 2 -; lgr %r2, %r4 -; dlr %r2, %r5 +; lhi %r4, 2 +; lgr %r2, %r5 +; dlr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -1310,9 +1314,10 @@ block0(v0: i32, v1: i32): } ; block0: -; lgr %r4, %r3 +; lgr %r5, %r3 ; lgfr %r3, %r2 -; dsgfr %r2, %r4 +; lgr %r2, %r5 +; dsgfr %r2, %r2 ; br %r14 function %srem_i16(i16, i16) -> i16 { @@ -1348,10 +1353,10 @@ block0(v0: i64, v1: i64): } ; block0: -; lgr %r5, %r3 +; lgr %r4, %r3 ; lgr %r3, %r2 ; lghi %r2, 0 -; dlgr %r2, %r5 +; dlgr %r2, %r4 ; br %r14 function %urem_i32(i32, i32) -> i32 { @@ -1361,10 +1366,10 @@ block0(v0: i32, v1: i32): } ; block0: -; lgr %r5, %r3 +; lgr %r4, %r3 ; lgr %r3, %r2 ; lhi %r2, 0 -; dlr %r2, %r5 +; dlr %r2, %r4 ; br %r14 function %urem_i16(i16, i16) -> i16 { @@ -1373,15 +1378,17 @@ block0(v0: i16, v1: i16): return v2 } +; stmg %r8, %r15, 64(%r15) ; block0: ; lgr %r4, %r3 -; lhi %r3, 0 -; lgr %r5, %r3 +; lhi %r5, 0 +; lgr %r8, %r5 ; llhr %r3, %r2 -; lgr %r2, %r4 -; llhr %r4, %r2 -; lgr %r2, %r5 -; dlr %r2, %r4 +; lgr %r5, %r4 +; llhr %r5, %r5 +; lgr %r2, %r8 +; dlr %r2, %r5 +; lmg %r8, %r15, 64(%r15) ; br %r14 function %urem_i8(i8, i8) -> i8 { @@ -1390,14 +1397,16 @@ block0(v0: i8, v1: i8): return v2 } +; stmg %r8, %r15, 64(%r15) ; block0: ; lgr %r4, %r3 -; lhi %r3, 0 -; lgr %r5, %r3 +; lhi %r5, 0 +; lgr %r8, %r5 ; llcr %r3, %r2 -; lgr %r2, %r4 -; llcr %r4, %r2 -; lgr %r2, %r5 -; dlr %r2, %r4 +; lgr %r5, %r4 +; llcr %r5, %r5 +; lgr %r2, %r8 +; dlr %r2, %r5 +; lmg %r8, %r15, 64(%r15) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif b/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif index 6f1341f7a8..88d609fe52 100644 --- a/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif +++ b/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif @@ -37,20 +37,17 @@ block0(v0: i64, v1: i16, v2: i16, v3: i64): return v4 } -; stmg %r9, %r15, 72(%r15) +; stmg %r11, %r15, 88(%r15) ; block0: -; lgr %r9, %r4 -; sllk %r4, %r5, 3 -; lgr %r2, %r5 -; nill %r2, 65532 -; lrvr %r5, %r3 -; lgr %r3, %r9 -; lrvr %r3, %r3 -; l %r0, 0(%r2) -; 0: rll %r1, %r0, 16(%r4) ; rxsbg %r1, %r5, 176, 64, 48 ; jglh 1f ; risbgn %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r2) ; jglh 0b ; 1: -; rll %r2, %r0, 0(%r4) -; lrvr %r2, %r2 -; lmg %r9, %r15, 72(%r15) +; sllk %r11, %r5, 3 +; nill %r5, 65532 +; lrvr %r2, %r3 +; lrvr %r3, %r4 +; l %r0, 0(%r5) +; 0: rll %r1, %r0, 16(%r11) ; rxsbg %r1, %r2, 176, 64, 48 ; jglh 1f ; risbgn %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r11) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r5, %r0, 0(%r11) +; lrvr %r2, %r5 +; lmg %r11, %r15, 88(%r15) ; br %r14 function %atomic_cas_i8(i64, i8, i8, i64) -> i8 { @@ -59,16 +56,15 @@ block0(v0: i64, v1: i8, v2: i8, v3: i64): return v4 } -; stmg %r11, %r15, 88(%r15) +; stmg %r10, %r15, 80(%r15) ; block0: -; lgr %r11, %r4 -; sllk %r4, %r5, 3 -; lgr %r2, %r5 -; nill %r2, 65532 -; lcr %r5, %r4 -; l %r0, 0(%r2) -; 0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r3, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r11, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r2) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) -; lmg %r11, %r15, 88(%r15) +; lgr %r10, %r3 +; sllk %r3, %r5, 3 +; nill %r5, 65532 +; lcr %r2, %r3 +; l %r0, 0(%r5) +; 0: rll %r1, %r0, 0(%r3) ; rxsbg %r1, %r10, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r3) +; lmg %r10, %r15, 80(%r15) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif b/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif index db516f8bb4..32f2e4b765 100644 --- a/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif +++ b/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif @@ -31,17 +31,13 @@ block0(v0: i64, v1: i16, v2: i16, v3: i64): return v4 } -; stmg %r6, %r15, 48(%r15) ; block0: -; lgr %r6, %r4 -; sllk %r4, %r5, 3 -; lgr %r2, %r5 -; nill %r2, 65532 -; l %r0, 0(%r2) -; lgr %r5, %r6 -; 0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r3, 160, 48, 16 ; jglh 1f ; risbgn %r1, %r5, 32, 48, 16 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r2) ; jglh 0b ; 1: -; rll %r2, %r0, 16(%r4) -; lmg %r6, %r15, 48(%r15) +; lgr %r2, %r3 +; sllk %r3, %r5, 3 +; nill %r5, 65532 +; l %r0, 0(%r5) +; 0: rll %r1, %r0, 0(%r3) ; rxsbg %r1, %r2, 160, 48, 16 ; jglh 1f ; risbgn %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 16(%r3) ; br %r14 function %atomic_cas_i8(i64, i8, i8, i64) -> i8 { @@ -50,16 +46,15 @@ block0(v0: i64, v1: i8, v2: i8, v3: i64): return v4 } -; stmg %r11, %r15, 88(%r15) +; stmg %r10, %r15, 80(%r15) ; block0: -; lgr %r11, %r4 -; sllk %r4, %r5, 3 -; lgr %r2, %r5 -; nill %r2, 65532 -; lcr %r5, %r4 -; l %r0, 0(%r2) -; 0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r3, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r11, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r2) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) -; lmg %r11, %r15, 88(%r15) +; lgr %r10, %r3 +; sllk %r3, %r5, 3 +; nill %r5, 65532 +; lcr %r2, %r3 +; l %r0, 0(%r5) +; 0: rll %r1, %r0, 0(%r3) ; rxsbg %r1, %r10, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r3) +; lmg %r10, %r15, 80(%r15) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif index 3e80200734..730d0c1824 100644 --- a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif +++ b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif @@ -46,16 +46,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 { @@ -65,9 +63,9 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; lrvgr %r4, %r4 +; lrvgr %r2, %r4 ; lg %r0, 0(%r3) -; 0: nngrk %r1, %r0, %r4 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; 0: nngrk %r1, %r0, %r2 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1: ; lrvgr %r2, %r0 ; br %r14 @@ -78,9 +76,9 @@ block0(v0: i64, v1: i64, v2: i32): } ; block0: -; lrvr %r4, %r4 +; lrvr %r2, %r4 ; l %r0, 0(%r3) -; 0: nnrk %r1, %r0, %r4 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; 0: nnrk %r1, %r0, %r2 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: ; lrvr %r2, %r0 ; br %r14 @@ -91,14 +89,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; lrvr %r4, %r4 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r4, 48, 64, 48 ; xilf %r1, 65535 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; lrvr %r3, %r5 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r3, 48, 64, 48 ; xilf %r1, 65535 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 { @@ -107,15 +106,13 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif index 64eb171ba5..14135aeb0c 100644 --- a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif +++ b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif @@ -12,9 +12,9 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; lrvgr %r4, %r4 +; lrvgr %r2, %r4 ; lg %r0, 0(%r3) -; 0: csg %r0, %r4, 0(%r3) ; jglh 0b ; 1: +; 0: csg %r0, %r2, 0(%r3) ; jglh 0b ; 1: ; lrvgr %r2, %r0 ; br %r14 @@ -25,9 +25,9 @@ block0(v0: i64, v1: i64, v2: i32): } ; block0: -; lrvr %r4, %r4 +; lrvr %r2, %r4 ; l %r0, 0(%r3) -; 0: cs %r0, %r4, 0(%r3) ; jglh 0b ; 1: +; 0: cs %r0, %r2, 0(%r3) ; jglh 0b ; 1: ; lrvr %r2, %r0 ; br %r14 @@ -38,14 +38,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; lrvr %r4, %r4 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; risbgn %r1, %r4, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; lrvr %r3, %r5 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; risbgn %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_xchg_i8(i64, i64, i8) -> i8 { @@ -54,16 +55,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_add_i64(i64, i64, i64) -> i64 { @@ -97,14 +96,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; ar %r1, %r4 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; ar %r1, %r3 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_add_i8(i64, i64, i8) -> i8 { @@ -113,17 +113,15 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; ar %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; ar %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_sub_i64(i64, i64, i64) -> i64 { @@ -157,14 +155,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; sr %r1, %r4 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; sr %r1, %r3 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_sub_i8(i64, i64, i8) -> i8 { @@ -173,17 +172,15 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; sr %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; sr %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_and_i64(i64, i64, i64) -> i64 { @@ -193,9 +190,9 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; lrvgr %r4, %r4 -; lang %r5, %r4, 0(%r3) -; lrvgr %r2, %r5 +; lrvgr %r2, %r4 +; lang %r4, %r2, 0(%r3) +; lrvgr %r2, %r4 ; br %r14 function %atomic_rmw_and_i32(i64, i64, i32) -> i32 { @@ -205,9 +202,9 @@ block0(v0: i64, v1: i64, v2: i32): } ; block0: -; lrvr %r4, %r4 -; lan %r5, %r4, 0(%r3) -; lrvr %r2, %r5 +; lrvr %r2, %r4 +; lan %r4, %r2, 0(%r3) +; lrvr %r2, %r4 ; br %r14 function %atomic_rmw_and_i16(i64, i64, i16) -> i16 { @@ -217,14 +214,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; lrvr %r4, %r4 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r4, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; lrvr %r3, %r5 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_and_i8(i64, i64, i8) -> i8 { @@ -233,16 +231,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_or_i64(i64, i64, i64) -> i64 { @@ -252,9 +248,9 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; lrvgr %r4, %r4 -; laog %r5, %r4, 0(%r3) -; lrvgr %r2, %r5 +; lrvgr %r2, %r4 +; laog %r4, %r2, 0(%r3) +; lrvgr %r2, %r4 ; br %r14 function %atomic_rmw_or_i32(i64, i64, i32) -> i32 { @@ -264,9 +260,9 @@ block0(v0: i64, v1: i64, v2: i32): } ; block0: -; lrvr %r4, %r4 -; lao %r5, %r4, 0(%r3) -; lrvr %r2, %r5 +; lrvr %r2, %r4 +; lao %r4, %r2, 0(%r3) +; lrvr %r2, %r4 ; br %r14 function %atomic_rmw_or_i16(i64, i64, i16) -> i16 { @@ -276,14 +272,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; lrvr %r4, %r4 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; rosbg %r1, %r4, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; lrvr %r3, %r5 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; rosbg %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_or_i8(i64, i64, i8) -> i8 { @@ -292,16 +289,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_xor_i64(i64, i64, i64) -> i64 { @@ -311,9 +306,9 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; lrvgr %r4, %r4 -; laxg %r5, %r4, 0(%r3) -; lrvgr %r2, %r5 +; lrvgr %r2, %r4 +; laxg %r4, %r2, 0(%r3) +; lrvgr %r2, %r4 ; br %r14 function %atomic_rmw_xor_i32(i64, i64, i32) -> i32 { @@ -323,9 +318,9 @@ block0(v0: i64, v1: i64, v2: i32): } ; block0: -; lrvr %r4, %r4 -; lax %r5, %r4, 0(%r3) -; lrvr %r2, %r5 +; lrvr %r2, %r4 +; lax %r4, %r2, 0(%r3) +; lrvr %r2, %r4 ; br %r14 function %atomic_rmw_xor_i16(i64, i64, i16) -> i16 { @@ -335,14 +330,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; lrvr %r4, %r4 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; rxsbg %r1, %r4, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; lrvr %r3, %r5 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; rxsbg %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_xor_i8(i64, i64, i8) -> i8 { @@ -351,16 +347,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 { @@ -370,9 +364,9 @@ block0(v0: i64, v1: i64, v2: i64): } ; block0: -; lrvgr %r4, %r4 +; lrvgr %r2, %r4 ; lg %r0, 0(%r3) -; 0: ngrk %r1, %r0, %r4 ; xilf %r1, 4294967295 ; xihf %r1, 4294967295 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; 0: ngrk %r1, %r0, %r2 ; xilf %r1, 4294967295 ; xihf %r1, 4294967295 ; csg %r0, %r1, 0(%r3) ; jglh 0b ; 1: ; lrvgr %r2, %r0 ; br %r14 @@ -383,9 +377,9 @@ block0(v0: i64, v1: i64, v2: i32): } ; block0: -; lrvr %r4, %r4 +; lrvr %r2, %r4 ; l %r0, 0(%r3) -; 0: nrk %r1, %r0, %r4 ; xilf %r1, 4294967295 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; 0: nrk %r1, %r0, %r2 ; xilf %r1, 4294967295 ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: ; lrvr %r2, %r0 ; br %r14 @@ -396,14 +390,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; lrvr %r4, %r4 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r4, 48, 64, 48 ; xilf %r1, 65535 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; lrvr %r3, %r5 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; rnsbg %r1, %r3, 48, 64, 48 ; xilf %r1, 65535 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 { @@ -412,16 +407,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_smin_i64(i64, i64, i64) -> i64 { @@ -455,14 +448,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; cr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_smin_i8(i64, i64, i8) -> i8 { @@ -471,17 +465,15 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; cr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_smax_i64(i64, i64, i64) -> i64 { @@ -515,14 +507,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; cr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_smax_i8(i64, i64, i8) -> i8 { @@ -531,17 +524,15 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; cr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_umin_i64(i64, i64, i64) -> i64 { @@ -575,14 +566,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; clr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_umin_i8(i64, i64, i8) -> i8 { @@ -591,17 +583,15 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; clr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_umax_i64(i64, i64, i64) -> i64 { @@ -635,14 +625,15 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; clr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r2) -; lrvr %r2, %r3 +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 16(%r2) ; lrvr %r1, %r1 ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: +; rll %r2, %r0, 0(%r2) +; lrvr %r2, %r2 ; br %r14 function %atomic_rmw_umax_i8(i64, i64, i8) -> i8 { @@ -651,16 +642,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; clr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif b/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif index f95940aae7..4837175f09 100644 --- a/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif +++ b/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif @@ -50,16 +50,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_add_i64(i64, i64) -> i64 { @@ -89,12 +87,13 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r2) ; ar %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 0(%r2) ; ar %r1, %r3 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r2) ; br %r14 @@ -104,17 +103,15 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; ar %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; ar %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_sub_i64(i64, i64) -> i64 { @@ -124,8 +121,8 @@ block0(v0: i64, v1: i64): } ; block0: -; lcgr %r3, %r3 -; laag %r2, %r3, 0(%r2) +; lcgr %r5, %r3 +; laag %r2, %r5, 0(%r2) ; br %r14 function %atomic_rmw_sub_i32(i64, i32) -> i32 { @@ -135,8 +132,8 @@ block0(v0: i64, v1: i32): } ; block0: -; lcr %r3, %r3 -; laa %r2, %r3, 0(%r2) +; lcr %r5, %r3 +; laa %r2, %r5, 0(%r2) ; br %r14 function %atomic_rmw_sub_i16(i64, i64, i16) -> i16 { @@ -146,12 +143,13 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r2) ; sr %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 0(%r2) ; sr %r1, %r3 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r2) ; br %r14 @@ -161,17 +159,15 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; sr %r1, %r4 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; sr %r1, %r3 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_and_i64(i64, i64) -> i64 { @@ -215,16 +211,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_or_i64(i64, i64) -> i64 { @@ -268,16 +262,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_xor_i64(i64, i64) -> i64 { @@ -321,16 +313,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 { @@ -378,16 +368,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; lcr %r2, %r11 +; lcr %r3, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r3) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_smin_i64(i64, i64, i64) -> i64 { @@ -421,12 +409,13 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r2) ; cr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r2) ; br %r14 @@ -436,17 +425,15 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; cr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_smax_i64(i64, i64, i64) -> i64 { @@ -480,12 +467,13 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r2) ; cr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r2) ; br %r14 @@ -495,17 +483,15 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; cr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; cr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_umin_i64(i64, i64, i64) -> i64 { @@ -539,12 +525,13 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r2) ; clr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r2) ; br %r14 @@ -554,17 +541,15 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; clr %r4, %r1 ; jgnl 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnl 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_umax_i64(i64, i64, i64) -> i64 { @@ -598,12 +583,13 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: +; lgr %r5, %r4 ; sllk %r2, %r3, 3 -; lgr %r5, %r3 -; nill %r5, 65532 -; sllk %r4, %r4, 16 -; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r2) ; clr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; lgr %r4, %r3 +; nill %r4, 65532 +; sllk %r3, %r5, 16 +; l %r0, 0(%r4) +; 0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 48, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r4) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r2) ; br %r14 @@ -613,16 +599,14 @@ block0(v0: i64, v1: i64, v2: i8): return v3 } -; stmg %r11, %r15, 88(%r15) ; block0: -; sllk %r11, %r3, 3 +; sllk %r2, %r3, 3 ; lgr %r5, %r3 ; nill %r5, 65532 -; sllk %r4, %r4, 24 -; lcr %r2, %r11 +; sllk %r3, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r11) ; clr %r4, %r1 ; jgnh 1f ; risbgn %r1, %r4, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r11) -; lmg %r11, %r15, 88(%r15) +; 0: rll %r1, %r0, 0(%r2) ; clr %r3, %r1 ; jgnh 1f ; risbgn %r1, %r3, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/bitops-arch13.clif b/cranelift/filetests/filetests/isa/s390x/bitops-arch13.clif index e06b019347..9090f30e4e 100644 --- a/cranelift/filetests/filetests/isa/s390x/bitops-arch13.clif +++ b/cranelift/filetests/filetests/isa/s390x/bitops-arch13.clif @@ -22,8 +22,8 @@ block0(v0: i32): } ; block0: -; llgfr %r5, %r2 -; popcnt %r2, %r5, 8 +; llgfr %r4, %r2 +; popcnt %r2, %r4, 8 ; br %r14 function %popcnt_i16(i16) -> i16 { @@ -33,8 +33,8 @@ block0(v0: i16): } ; block0: -; llghr %r5, %r2 -; popcnt %r2, %r5, 8 +; llghr %r4, %r2 +; popcnt %r2, %r4, 8 ; br %r14 function %popcnt_i8(i8) -> i8 { diff --git a/cranelift/filetests/filetests/isa/s390x/bitops.clif b/cranelift/filetests/filetests/isa/s390x/bitops.clif index 94a28a93b6..15b8ec56d5 100644 --- a/cranelift/filetests/filetests/isa/s390x/bitops.clif +++ b/cranelift/filetests/filetests/isa/s390x/bitops.clif @@ -9,24 +9,24 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vrepib %v5, 170 -; vrepib %v7, 1 -; vsl %v17, %v0, %v7 -; vsrl %v19, %v0, %v7 -; vsel %v21, %v17, %v19, %v5 -; vrepib %v23, 204 -; vrepib %v25, 2 -; vsl %v27, %v21, %v25 -; vsrl %v29, %v21, %v25 -; vsel %v31, %v27, %v29, %v23 -; vrepib %v1, 240 -; vrepib %v3, 4 -; vsl %v5, %v31, %v3 -; vsrl %v7, %v31, %v3 -; vsel %v17, %v5, %v7, %v1 -; bras %r1, 20 ; data.u128 0x0f0e0d0c0b0a09080706050403020100 ; vl %v19, 0(%r1) -; vperm %v21, %v17, %v17, %v19 -; vst %v21, 0(%r2) +; vrepib %v4, 170 +; vrepib %v6, 1 +; vsl %v16, %v0, %v6 +; vsrl %v18, %v0, %v6 +; vsel %v20, %v16, %v18, %v4 +; vrepib %v22, 204 +; vrepib %v24, 2 +; vsl %v26, %v20, %v24 +; vsrl %v28, %v20, %v24 +; vsel %v30, %v26, %v28, %v22 +; vrepib %v0, 240 +; vrepib %v2, 4 +; vsl %v4, %v30, %v2 +; vsrl %v6, %v30, %v2 +; vsel %v16, %v4, %v6, %v0 +; bras %r1, 20 ; data.u128 0x0f0e0d0c0b0a09080706050403020100 ; vl %v18, 0(%r1) +; vperm %v20, %v16, %v16, %v18 +; vst %v20, 0(%r2) ; br %r14 function %bitrev_i64(i64) -> i64 { @@ -36,34 +36,36 @@ block0(v0: i64): } ; block0: -; llihf %r3, 2863311530 -; iilf %r3, 2863311530 -; sllg %r5, %r2, 1 -; srlg %r4, %r2, 1 -; ngr %r5, %r3 -; xilf %r3, 4294967295 -; xihf %r3, 4294967295 -; ngrk %r3, %r4, %r3 -; ogrk %r2, %r5, %r3 -; llihf %r5, 3435973836 -; iilf %r5, 3435973836 -; sllg %r3, %r2, 2 -; srlg %r2, %r2, 2 -; ngr %r3, %r5 -; xilf %r5, 4294967295 -; xihf %r5, 4294967295 -; ngrk %r5, %r2, %r5 -; ogrk %r4, %r3, %r5 -; llihf %r3, 4042322160 -; iilf %r3, 4042322160 -; sllg %r5, %r4, 4 -; srlg %r4, %r4, 4 -; ngr %r5, %r3 -; xilf %r3, 4294967295 -; xihf %r3, 4294967295 -; ngrk %r3, %r4, %r3 -; ogr %r5, %r3 -; lrvgr %r2, %r5 +; lgr %r4, %r2 +; llihf %r2, 2863311530 +; iilf %r2, 2863311530 +; lgr %r3, %r4 +; sllg %r4, %r3, 1 +; srlg %r3, %r3, 1 +; ngr %r4, %r2 +; xilf %r2, 4294967295 +; xihf %r2, 4294967295 +; ngrk %r2, %r3, %r2 +; ogrk %r5, %r4, %r2 +; llihf %r4, 3435973836 +; iilf %r4, 3435973836 +; sllg %r2, %r5, 2 +; srlg %r5, %r5, 2 +; ngr %r2, %r4 +; xilf %r4, 4294967295 +; xihf %r4, 4294967295 +; ngrk %r4, %r5, %r4 +; ogrk %r3, %r2, %r4 +; llihf %r2, 4042322160 +; iilf %r2, 4042322160 +; sllg %r4, %r3, 4 +; srlg %r3, %r3, 4 +; ngr %r4, %r2 +; xilf %r2, 4294967295 +; xihf %r2, 4294967295 +; ngrk %r2, %r3, %r2 +; ogr %r4, %r2 +; lrvgr %r2, %r4 ; br %r14 function %bitrev_i32(i32) -> i32 { @@ -73,28 +75,28 @@ block0(v0: i32): } ; block0: -; iilf %r5, 2863311530 +; iilf %r4, 2863311530 ; sllk %r3, %r2, 1 -; srlk %r2, %r2, 1 -; nr %r3, %r5 -; xilf %r5, 4294967295 -; nrk %r4, %r2, %r5 -; ork %r5, %r3, %r4 -; iilf %r3, 3435973836 -; sllk %r2, %r5, 2 -; srlk %r4, %r5, 2 -; nrk %r5, %r2, %r3 -; xilf %r3, 4294967295 -; nrk %r2, %r4, %r3 -; ork %r3, %r5, %r2 -; iilf %r5, 4042322160 -; sllk %r4, %r3, 4 -; srlk %r2, %r3, 4 -; nrk %r3, %r4, %r5 -; xilf %r5, 4294967295 -; nrk %r4, %r2, %r5 -; ork %r5, %r3, %r4 -; lrvr %r2, %r5 +; srlk %r5, %r2, 1 +; nrk %r2, %r3, %r4 +; xilf %r4, 4294967295 +; nrk %r3, %r5, %r4 +; ork %r4, %r2, %r3 +; iilf %r2, 3435973836 +; sllk %r5, %r4, 2 +; srlk %r3, %r4, 2 +; nrk %r4, %r5, %r2 +; xilf %r2, 4294967295 +; nrk %r5, %r3, %r2 +; ork %r2, %r4, %r5 +; iilf %r4, 4042322160 +; sllk %r3, %r2, 4 +; srlk %r5, %r2, 4 +; nrk %r2, %r3, %r4 +; xilf %r4, 4294967295 +; nrk %r3, %r5, %r4 +; ork %r4, %r2, %r3 +; lrvr %r2, %r4 ; br %r14 function %bitrev_i16(i16) -> i16 { @@ -104,29 +106,29 @@ block0(v0: i16): } ; block0: -; lhi %r5, -21846 +; lhi %r4, -21846 ; sllk %r3, %r2, 1 -; srlk %r2, %r2, 1 -; nr %r3, %r5 -; xilf %r5, 4294967295 -; nrk %r4, %r2, %r5 -; ork %r5, %r3, %r4 -; lhi %r3, -13108 -; sllk %r2, %r5, 2 -; srlk %r4, %r5, 2 -; nrk %r5, %r2, %r3 -; xilf %r3, 4294967295 -; nrk %r2, %r4, %r3 -; ork %r3, %r5, %r2 -; lhi %r5, -3856 -; sllk %r4, %r3, 4 -; srlk %r2, %r3, 4 -; nrk %r3, %r4, %r5 -; xilf %r5, 4294967295 -; nrk %r4, %r2, %r5 -; ork %r5, %r3, %r4 -; lrvr %r3, %r5 -; srlk %r2, %r3, 16 +; srlk %r5, %r2, 1 +; nrk %r2, %r3, %r4 +; xilf %r4, 4294967295 +; nrk %r3, %r5, %r4 +; ork %r4, %r2, %r3 +; lhi %r2, -13108 +; sllk %r5, %r4, 2 +; srlk %r3, %r4, 2 +; nrk %r4, %r5, %r2 +; xilf %r2, 4294967295 +; nrk %r5, %r3, %r2 +; ork %r2, %r4, %r5 +; lhi %r4, -3856 +; sllk %r3, %r2, 4 +; srlk %r5, %r2, 4 +; nrk %r2, %r3, %r4 +; xilf %r4, 4294967295 +; nrk %r3, %r5, %r4 +; ork %r4, %r2, %r3 +; lrvr %r2, %r4 +; srlk %r2, %r2, 16 ; br %r14 function %bitrev_i8(i8) -> i8 { @@ -136,27 +138,27 @@ block0(v0: i8): } ; block0: -; lhi %r5, -21846 +; lhi %r4, -21846 ; sllk %r3, %r2, 1 -; srlk %r2, %r2, 1 -; nr %r3, %r5 -; xilf %r5, 4294967295 -; nrk %r4, %r2, %r5 -; ork %r5, %r3, %r4 -; lhi %r3, -13108 -; sllk %r2, %r5, 2 -; srlk %r4, %r5, 2 -; nrk %r5, %r2, %r3 -; xilf %r3, 4294967295 -; nrk %r2, %r4, %r3 -; ork %r3, %r5, %r2 -; lhi %r5, -3856 -; sllk %r4, %r3, 4 -; srlk %r2, %r3, 4 -; nrk %r3, %r4, %r5 -; xilf %r5, 4294967295 -; nrk %r4, %r2, %r5 -; ork %r2, %r3, %r4 +; srlk %r5, %r2, 1 +; nrk %r2, %r3, %r4 +; xilf %r4, 4294967295 +; nrk %r3, %r5, %r4 +; ork %r4, %r2, %r3 +; lhi %r2, -13108 +; sllk %r5, %r4, 2 +; srlk %r3, %r4, 2 +; nrk %r4, %r5, %r2 +; xilf %r2, 4294967295 +; nrk %r5, %r3, %r2 +; ork %r2, %r4, %r5 +; lhi %r4, -3856 +; sllk %r3, %r2, 4 +; srlk %r5, %r2, 4 +; nrk %r2, %r3, %r4 +; xilf %r4, 4294967295 +; nrk %r3, %r5, %r4 +; or %r2, %r3 ; br %r14 function %clz_i128(i128) -> i128 { @@ -167,15 +169,15 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vclzg %v5, %v0 -; vgbm %v7, 0 -; vpdi %v17, %v7, %v5, 0 -; vpdi %v19, %v7, %v5, 1 -; vag %v21, %v17, %v19 -; vrepig %v23, 64 -; vceqg %v25, %v17, %v23 -; vsel %v27, %v21, %v17, %v25 -; vst %v27, 0(%r2) +; vclzg %v4, %v0 +; vgbm %v6, 0 +; vpdi %v16, %v6, %v4, 0 +; vpdi %v18, %v6, %v4, 1 +; vag %v20, %v16, %v18 +; vrepig %v22, 64 +; vceqg %v24, %v16, %v22 +; vsel %v26, %v20, %v16, %v24 +; vst %v26, 0(%r2) ; br %r14 function %clz_i64(i64) -> i64 { @@ -195,8 +197,8 @@ block0(v0: i32): } ; block0: -; llgfr %r5, %r2 -; flogr %r2, %r5 +; llgfr %r4, %r2 +; flogr %r2, %r4 ; ahi %r2, -32 ; br %r14 @@ -207,8 +209,8 @@ block0(v0: i16): } ; block0: -; llghr %r5, %r2 -; flogr %r2, %r5 +; llghr %r4, %r2 +; flogr %r2, %r4 ; ahi %r2, -48 ; br %r14 @@ -219,8 +221,8 @@ block0(v0: i8): } ; block0: -; llgcr %r5, %r2 -; flogr %r2, %r5 +; llgcr %r4, %r2 +; flogr %r2, %r4 ; ahi %r2, -56 ; br %r14 @@ -232,20 +234,20 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vrepib %v5, 255 -; vsrab %v7, %v0, %v5 -; vsra %v17, %v7, %v5 -; vx %v19, %v0, %v17 -; vclzg %v21, %v19 -; vgbm %v23, 0 -; vpdi %v25, %v23, %v21, 0 -; vpdi %v27, %v23, %v21, 1 -; vag %v29, %v25, %v27 -; vrepig %v31, 64 -; vceqg %v1, %v25, %v31 -; vsel %v3, %v29, %v25, %v1 -; vaq %v5, %v3, %v5 -; vst %v5, 0(%r2) +; vrepib %v4, 255 +; vsrab %v6, %v0, %v4 +; vsra %v16, %v6, %v4 +; vx %v18, %v0, %v16 +; vclzg %v20, %v18 +; vgbm %v22, 0 +; vpdi %v24, %v22, %v20, 0 +; vpdi %v26, %v22, %v20, 1 +; vag %v28, %v24, %v26 +; vrepig %v30, 64 +; vceqg %v0, %v24, %v30 +; vsel %v2, %v28, %v24, %v0 +; vaq %v4, %v2, %v4 +; vst %v4, 0(%r2) ; br %r14 function %cls_i64(i64) -> i64 { @@ -255,9 +257,9 @@ block0(v0: i64): } ; block0: -; srag %r5, %r2, 63 -; xgrk %r3, %r2, %r5 -; flogr %r2, %r3 +; srag %r4, %r2, 63 +; xgr %r2, %r4 +; flogr %r2, %r2 ; aghi %r2, -1 ; br %r14 @@ -268,10 +270,10 @@ block0(v0: i32): } ; block0: -; lgfr %r5, %r2 -; srag %r3, %r5, 63 -; xgr %r5, %r3 -; flogr %r2, %r5 +; lgfr %r4, %r2 +; srag %r2, %r4, 63 +; xgr %r4, %r2 +; flogr %r2, %r4 ; ahi %r2, -33 ; br %r14 @@ -282,10 +284,10 @@ block0(v0: i16): } ; block0: -; lghr %r5, %r2 -; srag %r3, %r5, 63 -; xgr %r5, %r3 -; flogr %r2, %r5 +; lghr %r4, %r2 +; srag %r2, %r4, 63 +; xgr %r4, %r2 +; flogr %r2, %r4 ; ahi %r2, -49 ; br %r14 @@ -296,10 +298,10 @@ block0(v0: i8): } ; block0: -; lgbr %r5, %r2 -; srag %r3, %r5, 63 -; xgr %r5, %r3 -; flogr %r2, %r5 +; lgbr %r4, %r2 +; srag %r2, %r4, 63 +; xgr %r4, %r2 +; flogr %r2, %r4 ; ahi %r2, -57 ; br %r14 @@ -311,15 +313,15 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vctzg %v5, %v0 -; vgbm %v7, 0 -; vpdi %v17, %v7, %v5, 0 -; vpdi %v19, %v7, %v5, 1 -; vag %v21, %v17, %v19 -; vrepig %v23, 64 -; vceqg %v25, %v19, %v23 -; vsel %v27, %v21, %v19, %v25 -; vst %v27, 0(%r2) +; vctzg %v4, %v0 +; vgbm %v6, 0 +; vpdi %v16, %v6, %v4, 0 +; vpdi %v18, %v6, %v4, 1 +; vag %v20, %v16, %v18 +; vrepig %v22, 64 +; vceqg %v24, %v18, %v22 +; vsel %v26, %v20, %v18, %v24 +; vst %v26, 0(%r2) ; br %r14 function %ctz_i64(i64) -> i64 { @@ -329,13 +331,13 @@ block0(v0: i64): } ; block0: -; lcgr %r5, %r2 -; ngrk %r3, %r2, %r5 -; flogr %r2, %r3 -; lgr %r4, %r2 -; locghie %r4, -1 -; lghi %r2, 63 -; sgr %r2, %r4 +; lcgr %r4, %r2 +; ngr %r2, %r4 +; flogr %r2, %r2 +; lgr %r3, %r2 +; locghie %r3, -1 +; lghi %r5, 63 +; sgrk %r2, %r5, %r3 ; br %r14 function %ctz_i32(i32) -> i32 { @@ -345,13 +347,13 @@ block0(v0: i32): } ; block0: -; lgr %r5, %r2 -; oihl %r5, 1 -; lcgr %r3, %r5 -; ngr %r5, %r3 -; flogr %r2, %r5 -; lhi %r3, 63 -; srk %r2, %r3, %r2 +; lgr %r4, %r2 +; oihl %r4, 1 +; lcgr %r2, %r4 +; ngr %r4, %r2 +; flogr %r2, %r4 +; lhi %r5, 63 +; srk %r2, %r5, %r2 ; br %r14 function %ctz_i16(i16) -> i16 { @@ -361,13 +363,13 @@ block0(v0: i16): } ; block0: -; lgr %r5, %r2 -; oilh %r5, 1 -; lcgr %r3, %r5 -; ngr %r5, %r3 -; flogr %r2, %r5 -; lhi %r3, 63 -; srk %r2, %r3, %r2 +; lgr %r4, %r2 +; oilh %r4, 1 +; lcgr %r2, %r4 +; ngr %r4, %r2 +; flogr %r2, %r4 +; lhi %r5, 63 +; srk %r2, %r5, %r2 ; br %r14 function %ctz_i8(i8) -> i8 { @@ -377,13 +379,13 @@ block0(v0: i8): } ; block0: -; lgr %r5, %r2 -; oill %r5, 256 -; lcgr %r3, %r5 -; ngr %r5, %r3 -; flogr %r2, %r5 -; lhi %r3, 63 -; srk %r2, %r3, %r2 +; lgr %r4, %r2 +; oill %r4, 256 +; lcgr %r2, %r4 +; ngr %r4, %r2 +; flogr %r2, %r4 +; lhi %r5, 63 +; srk %r2, %r5, %r2 ; br %r14 function %popcnt_i128(i128) -> i128 { @@ -394,12 +396,12 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vpopctg %v5, %v0 -; vgbm %v7, 0 -; vpdi %v17, %v7, %v5, 0 -; vpdi %v19, %v7, %v5, 1 -; vag %v21, %v17, %v19 -; vst %v21, 0(%r2) +; vpopctg %v4, %v0 +; vgbm %v6, 0 +; vpdi %v16, %v6, %v4, 0 +; vpdi %v18, %v6, %v4, 1 +; vag %v20, %v16, %v18 +; vst %v20, 0(%r2) ; br %r14 function %popcnt_i64(i64) -> i64 { @@ -409,14 +411,14 @@ block0(v0: i64): } ; block0: -; popcnt %r5, %r2 -; sllg %r3, %r5, 32 -; agr %r5, %r3 -; sllg %r3, %r5, 16 -; agr %r5, %r3 -; sllg %r3, %r5, 8 -; agr %r5, %r3 -; srlg %r2, %r5, 56 +; popcnt %r4, %r2 +; sllg %r2, %r4, 32 +; agr %r4, %r2 +; sllg %r2, %r4, 16 +; agr %r4, %r2 +; sllg %r2, %r4, 8 +; agr %r4, %r2 +; srlg %r2, %r4, 56 ; br %r14 function %popcnt_i32(i32) -> i32 { @@ -426,12 +428,12 @@ block0(v0: i32): } ; block0: -; popcnt %r5, %r2 -; sllk %r3, %r5, 16 -; ar %r5, %r3 -; sllk %r3, %r5, 8 -; ar %r5, %r3 -; srlk %r2, %r5, 24 +; popcnt %r4, %r2 +; sllk %r2, %r4, 16 +; ar %r4, %r2 +; sllk %r2, %r4, 8 +; ar %r4, %r2 +; srlk %r2, %r4, 24 ; br %r14 function %popcnt_i16(i16) -> i16 { @@ -441,9 +443,9 @@ block0(v0: i16): } ; block0: -; popcnt %r5, %r2 -; srlk %r3, %r5, 8 -; ark %r2, %r5, %r3 +; popcnt %r4, %r2 +; srlk %r2, %r4, 8 +; ark %r2, %r4, %r2 ; nill %r2, 255 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/bitwise-arch13.clif b/cranelift/filetests/filetests/isa/s390x/bitwise-arch13.clif index 1a16c3da02..1285f6788d 100644 --- a/cranelift/filetests/filetests/isa/s390x/bitwise-arch13.clif +++ b/cranelift/filetests/filetests/isa/s390x/bitwise-arch13.clif @@ -174,8 +174,8 @@ block0(v0: i64, v1: i64, v2: i64): ; block0: ; ngr %r3, %r2 -; ncgrk %r5, %r4, %r2 -; ogrk %r2, %r5, %r3 +; ncgrk %r4, %r4, %r2 +; ogrk %r2, %r4, %r3 ; br %r14 function %bitselect_i32(i32, i32, i32) -> i32 { @@ -186,8 +186,8 @@ block0(v0: i32, v1: i32, v2: i32): ; block0: ; nr %r3, %r2 -; ncrk %r5, %r4, %r2 -; ork %r2, %r5, %r3 +; ncrk %r4, %r4, %r2 +; ork %r2, %r4, %r3 ; br %r14 function %bitselect_i16(i16, i16, i16) -> i16 { @@ -198,8 +198,8 @@ block0(v0: i16, v1: i16, v2: i16): ; block0: ; nr %r3, %r2 -; ncrk %r5, %r4, %r2 -; ork %r2, %r5, %r3 +; ncrk %r4, %r4, %r2 +; ork %r2, %r4, %r3 ; br %r14 function %bitselect_i8(i8, i8, i8) -> i8 { @@ -210,7 +210,7 @@ block0(v0: i8, v1: i8, v2: i8): ; block0: ; nr %r3, %r2 -; ncrk %r5, %r4, %r2 -; ork %r2, %r5, %r3 +; ncrk %r4, %r4, %r2 +; ork %r2, %r4, %r3 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/bitwise.clif b/cranelift/filetests/filetests/isa/s390x/bitwise.clif index 8ea3b5bbb0..038c0aaef7 100644 --- a/cranelift/filetests/filetests/isa/s390x/bitwise.clif +++ b/cranelift/filetests/filetests/isa/s390x/bitwise.clif @@ -13,8 +13,8 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vn %v7, %v0, %v1 -; vst %v7, 0(%r2) +; vn %v6, %v0, %v1 +; vst %v6, 0(%r2) ; br %r14 function %band_i64(i64, i64) -> i64 { @@ -123,8 +123,8 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vo %v7, %v0, %v1 -; vst %v7, 0(%r2) +; vo %v6, %v0, %v1 +; vst %v6, 0(%r2) ; br %r14 function %bor_i64(i64, i64) -> i64 { @@ -233,8 +233,8 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vx %v7, %v0, %v1 -; vst %v7, 0(%r2) +; vx %v6, %v0, %v1 +; vst %v6, 0(%r2) ; br %r14 function %bxor_i64(i64, i64) -> i64 { @@ -343,8 +343,8 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vnc %v7, %v0, %v1 -; vst %v7, 0(%r2) +; vnc %v6, %v0, %v1 +; vst %v6, 0(%r2) ; br %r14 function %band_not_i64(i64, i64) -> i64 { @@ -366,8 +366,9 @@ block0(v0: i32, v1: i32): } ; block0: -; xilf %r3, 4294967295 -; nr %r2, %r3 +; lgr %r5, %r3 +; xilf %r5, 4294967295 +; nr %r2, %r5 ; br %r14 function %band_not_i16(i16, i16) -> i16 { @@ -377,8 +378,9 @@ block0(v0: i16, v1: i16): } ; block0: -; xilf %r3, 4294967295 -; nr %r2, %r3 +; lgr %r5, %r3 +; xilf %r5, 4294967295 +; nr %r2, %r5 ; br %r14 function %band_not_i8(i8, i8) -> i8 { @@ -388,8 +390,9 @@ block0(v0: i8, v1: i8): } ; block0: -; xilf %r3, 4294967295 -; nr %r2, %r3 +; lgr %r5, %r3 +; xilf %r5, 4294967295 +; nr %r2, %r5 ; br %r14 function %bor_not_i128(i128, i128) -> i128 { @@ -401,8 +404,8 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; voc %v7, %v0, %v1 -; vst %v7, 0(%r2) +; voc %v6, %v0, %v1 +; vst %v6, 0(%r2) ; br %r14 function %bor_not_i64(i64, i64) -> i64 { @@ -424,8 +427,9 @@ block0(v0: i32, v1: i32): } ; block0: -; xilf %r3, 4294967295 -; or %r2, %r3 +; lgr %r5, %r3 +; xilf %r5, 4294967295 +; or %r2, %r5 ; br %r14 function %bor_not_i16(i16, i16) -> i16 { @@ -435,8 +439,9 @@ block0(v0: i16, v1: i16): } ; block0: -; xilf %r3, 4294967295 -; or %r2, %r3 +; lgr %r5, %r3 +; xilf %r5, 4294967295 +; or %r2, %r5 ; br %r14 function %bor_not_i8(i8, i8) -> i8 { @@ -446,8 +451,9 @@ block0(v0: i8, v1: i8): } ; block0: -; xilf %r3, 4294967295 -; or %r2, %r3 +; lgr %r5, %r3 +; xilf %r5, 4294967295 +; or %r2, %r5 ; br %r14 function %bxor_not_i128(i128, i128) -> i128 { @@ -459,8 +465,8 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vnx %v7, %v0, %v1 -; vst %v7, 0(%r2) +; vnx %v6, %v0, %v1 +; vst %v6, 0(%r2) ; br %r14 function %bxor_not_i64(i64, i64) -> i64 { @@ -516,8 +522,8 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vno %v5, %v0, %v0 -; vst %v5, 0(%r2) +; vno %v4, %v0, %v0 +; vst %v4, 0(%r2) ; br %r14 function %bnot_i64(i64) -> i64 { @@ -571,8 +577,8 @@ block0(v0: i128, v1: i128, v2: i128): ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) ; vl %v2, 0(%r5) -; vsel %v17, %v1, %v2, %v0 -; vst %v17, 0(%r2) +; vsel %v16, %v1, %v2, %v0 +; vst %v16, 0(%r2) ; br %r14 function %bitselect_i64(i64, i64, i64) -> i64 { @@ -583,10 +589,11 @@ block0(v0: i64, v1: i64, v2: i64): ; block0: ; ngr %r3, %r2 -; xilf %r2, 4294967295 -; xihf %r2, 4294967295 -; ngrk %r5, %r4, %r2 -; ogrk %r2, %r5, %r3 +; lgr %r5, %r2 +; xilf %r5, 4294967295 +; xihf %r5, 4294967295 +; ngr %r4, %r5 +; ogrk %r2, %r4, %r3 ; br %r14 function %bitselect_i32(i32, i32, i32) -> i32 { @@ -599,8 +606,8 @@ block0(v0: i32, v1: i32, v2: i32): ; nr %r3, %r2 ; lgr %r5, %r2 ; xilf %r5, 4294967295 -; nr %r4, %r5 -; ork %r2, %r4, %r3 +; nrk %r2, %r4, %r5 +; or %r2, %r3 ; br %r14 function %bitselect_i16(i16, i16, i16) -> i16 { @@ -613,8 +620,8 @@ block0(v0: i16, v1: i16, v2: i16): ; nr %r3, %r2 ; lgr %r5, %r2 ; xilf %r5, 4294967295 -; nr %r4, %r5 -; ork %r2, %r4, %r3 +; nrk %r2, %r4, %r5 +; or %r2, %r3 ; br %r14 function %bitselect_i8(i8, i8, i8) -> i8 { @@ -627,7 +634,7 @@ block0(v0: i8, v1: i8, v2: i8): ; nr %r3, %r2 ; lgr %r5, %r2 ; xilf %r5, 4294967295 -; nr %r4, %r5 -; ork %r2, %r4, %r3 +; nrk %r2, %r4, %r5 +; or %r2, %r3 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/bswap.clif b/cranelift/filetests/filetests/isa/s390x/bswap.clif index 1a4033452d..6d6d87d96e 100644 --- a/cranelift/filetests/filetests/isa/s390x/bswap.clif +++ b/cranelift/filetests/filetests/isa/s390x/bswap.clif @@ -28,7 +28,7 @@ block0(v0: i16): } ; block0: -; lrvr %r5, %r2 -; srlk %r2, %r5, 16 +; lrvr %r4, %r2 +; srlk %r2, %r4, 16 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/call.clif b/cranelift/filetests/filetests/isa/s390x/call.clif index f07479ee83..cbcc2dfe5f 100644 --- a/cranelift/filetests/filetests/isa/s390x/call.clif +++ b/cranelift/filetests/filetests/isa/s390x/call.clif @@ -17,8 +17,8 @@ block0(v0: i64): ; aghi %r15, -160 ; virtual_sp_offset_adjust 160 ; block0: -; bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1) -; basr %r14, %r3 +; bras %r1, 12 ; data %g + 0 ; lg %r5, 0(%r1) +; basr %r14, %r5 ; lmg %r14, %r15, 272(%r15) ; br %r14 @@ -35,8 +35,8 @@ block0(v0: i32): ; virtual_sp_offset_adjust 160 ; block0: ; llgfr %r2, %r2 -; bras %r1, 12 ; data %g + 0 ; lg %r4, 0(%r1) -; basr %r14, %r4 +; bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1) +; basr %r14, %r3 ; lmg %r14, %r15, 272(%r15) ; br %r14 @@ -46,8 +46,7 @@ block0(v0: i32): } ; block0: -; lgr %r5, %r2 -; llgfr %r2, %r5 +; llgfr %r2, %r2 ; br %r14 function %call_uext(i32) -> i64 { @@ -63,8 +62,8 @@ block0(v0: i32): ; virtual_sp_offset_adjust 160 ; block0: ; lgfr %r2, %r2 -; bras %r1, 12 ; data %g + 0 ; lg %r4, 0(%r1) -; basr %r14, %r4 +; bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1) +; basr %r14, %r3 ; lmg %r14, %r15, 272(%r15) ; br %r14 @@ -74,8 +73,7 @@ block0(v0: i32): } ; block0: -; lgr %r5, %r2 -; lgfr %r2, %r5 +; lgfr %r2, %r2 ; br %r14 function %call_colocated(i64) -> i64 { @@ -107,8 +105,8 @@ block0(v0: i32): ; virtual_sp_offset_adjust 160 ; block0: ; llgfr %r2, %r2 -; bras %r1, 12 ; data %g + 0 ; lg %r4, 0(%r1) -; basr %r14, %r4 +; bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1) +; basr %r14, %r3 ; lmg %r14, %r15, 272(%r15) ; br %r14 @@ -151,38 +149,31 @@ block0(v0: i64, v1: i32, v2: i32, v3: i32, v4: i16, v5: i16, v6: i16, v7: i8, v8 } ; stmg %r6, %r15, 48(%r15) -; aghi %r15, -16 ; block0: -; stg %r2, 0(%r15) -; lgr %r10, %r6 -; lg %r11, 176(%r15) -; lg %r12, 184(%r15) -; llgc %r13, 199(%r15) -; lg %r6, 200(%r15) -; lg %r2, 208(%r15) -; stg %r2, 8(%r15) -; llgfr %r2, %r3 -; llgfr %r9, %r4 +; lg %r11, 160(%r15) +; lg %r12, 168(%r15) +; llgc %r13, 183(%r15) +; lg %r14, 184(%r15) +; lg %r8, 192(%r15) +; llgfr %r3, %r3 +; llgfr %r4, %r4 ; llgfr %r7, %r5 -; lgr %r4, %r10 -; llghr %r8, %r4 +; llghr %r6, %r6 ; llghr %r5, %r11 -; llghr %r10, %r12 -; llgcr %r4, %r13 -; llgcr %r13, %r6 -; lg %r3, 8(%r15) -; llgcr %r3, %r3 -; lg %r11, 0(%r15) -; agrk %r2, %r11, %r2 -; agrk %r6, %r9, %r7 -; agrk %r5, %r8, %r5 -; agrk %r4, %r10, %r4 -; agrk %r3, %r13, %r3 -; agr %r2, %r6 -; agrk %r4, %r5, %r4 -; agrk %r5, %r3, %r2 -; agrk %r2, %r4, %r5 -; lmg %r6, %r15, 64(%r15) +; llghr %r12, %r12 +; llgcr %r13, %r13 +; llgcr %r14, %r14 +; llgcr %r8, %r8 +; agrk %r3, %r2, %r3 +; agr %r4, %r7 +; agrk %r5, %r6, %r5 +; agrk %r2, %r12, %r13 +; agrk %r12, %r14, %r8 +; agr %r3, %r4 +; agrk %r4, %r5, %r2 +; agrk %r3, %r12, %r3 +; agrk %r2, %r4, %r3 +; lmg %r6, %r15, 48(%r15) ; br %r14 function %incoming_args_i128(i128, i128, i128, i128, i128, i128, i128, i128) -> i128 { @@ -202,25 +193,24 @@ block0(v0: i128, v1: i128, v2: i128, v3: i128, v4: i128, v5: i128, v6: i128, v7: ; vl %v1, 0(%r4) ; vl %v2, 0(%r5) ; vl %v3, 0(%r6) -; lg %r4, 160(%r15) -; vl %v4, 0(%r4) +; lg %r3, 160(%r15) +; vl %v4, 0(%r3) ; lg %r3, 168(%r15) ; vl %v5, 0(%r3) -; lg %r3, 176(%r15) -; vl %v6, 0(%r3) -; lg %r5, 184(%r15) -; vl %v7, 0(%r5) -; vaq %v17, %v0, %v1 -; vaq %v18, %v2, %v3 -; vaq %v19, %v4, %v5 -; vaq %v20, %v6, %v7 -; vaq %v17, %v17, %v18 -; vaq %v18, %v19, %v20 -; vaq %v17, %v17, %v18 -; vst %v17, 0(%r2) +; lg %r5, 176(%r15) +; vl %v6, 0(%r5) +; lg %r4, 184(%r15) +; vl %v7, 0(%r4) +; vaq %v16, %v0, %v1 +; vaq %v17, %v2, %v3 +; vaq %v18, %v4, %v5 +; vaq %v19, %v6, %v7 +; vaq %v16, %v16, %v17 +; vaq %v17, %v18, %v19 +; vaq %v16, %v16, %v17 +; vst %v16, 0(%r2) ; br %r14 - function %call_sret() -> i64 { fn0 = colocated %g(i64 sret) diff --git a/cranelift/filetests/filetests/isa/s390x/concat-split.clif b/cranelift/filetests/filetests/isa/s390x/concat-split.clif index 54c86d63a7..84f2ef3221 100644 --- a/cranelift/filetests/filetests/isa/s390x/concat-split.clif +++ b/cranelift/filetests/filetests/isa/s390x/concat-split.clif @@ -8,8 +8,8 @@ block0(v0: i64, v1: i64): } ; block0: -; vlvgp %v5, %r4, %r3 -; vst %v5, 0(%r2) +; vlvgp %v4, %r4, %r3 +; vst %v4, 0(%r2) ; br %r14 function %isplit_i128(i128) -> i64, i64 { diff --git a/cranelift/filetests/filetests/isa/s390x/condops.clif b/cranelift/filetests/filetests/isa/s390x/condops.clif index 3a95b79a5b..65d525e2b7 100644 --- a/cranelift/filetests/filetests/isa/s390x/condops.clif +++ b/cranelift/filetests/filetests/isa/s390x/condops.clif @@ -10,8 +10,8 @@ block0(v0: i8, v1: i64, v2: i64): } ; block0: -; llcr %r5, %r2 -; clfi %r5, 42 +; llcr %r2, %r2 +; clfi %r2, 42 ; lgr %r2, %r4 ; locgre %r2, %r3 ; br %r14 @@ -23,8 +23,8 @@ block0(v0: i8, v1: i8, v2: i8): } ; block0: -; lbr %r5, %r2 -; chi %r5, 0 +; lbr %r2, %r2 +; chi %r2, 0 ; lgr %r2, %r4 ; locrlh %r2, %r3 ; br %r14 @@ -53,8 +53,8 @@ block0(v0: i32, v1: i8x16, v2: i8x16): ; block0: ; clfi %r2, 42 -; vlr %v6, %v25 -; jne 10 ; vlr %v6, %v24 -; vlr %v24, %v6 +; vlr %v6, %v24 +; vlr %v24, %v25 +; jne 10 ; vlr %v24, %v6 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/conversions.clif b/cranelift/filetests/filetests/isa/s390x/conversions.clif index c02f0e7e30..3299aa0ec5 100644 --- a/cranelift/filetests/filetests/isa/s390x/conversions.clif +++ b/cranelift/filetests/filetests/isa/s390x/conversions.clif @@ -8,9 +8,9 @@ block0(v0: i64): } ; block0: -; vgbm %v5, 0 -; vlvgg %v5, %r3, 1 -; vst %v5, 0(%r2) +; vgbm %v4, 0 +; vlvgg %v4, %r3, 1 +; vst %v4, 0(%r2) ; br %r14 function %uextend_i32_i128(i32) -> i128 { @@ -20,9 +20,9 @@ block0(v0: i32): } ; block0: -; vgbm %v5, 0 -; vlvgf %v5, %r3, 3 -; vst %v5, 0(%r2) +; vgbm %v4, 0 +; vlvgf %v4, %r3, 3 +; vst %v4, 0(%r2) ; br %r14 function %uextend_i32_i64(i32) -> i64 { @@ -42,9 +42,9 @@ block0(v0: i16): } ; block0: -; vgbm %v5, 0 -; vlvgh %v5, %r3, 7 -; vst %v5, 0(%r2) +; vgbm %v4, 0 +; vlvgh %v4, %r3, 7 +; vst %v4, 0(%r2) ; br %r14 function %uextend_i16_i64(i16) -> i64 { @@ -74,9 +74,9 @@ block0(v0: i8): } ; block0: -; vgbm %v5, 0 -; vlvgb %v5, %r3, 15 -; vst %v5, 0(%r2) +; vgbm %v4, 0 +; vlvgb %v4, %r3, 15 +; vst %v4, 0(%r2) ; br %r14 function %uextend_i8_i64(i8) -> i64 { @@ -116,9 +116,9 @@ block0(v0: i64): } ; block0: -; srag %r4, %r3, 63 -; vlvgp %v6, %r4, %r3 -; vst %v6, 0(%r2) +; srag %r5, %r3, 63 +; vlvgp %v5, %r5, %r3 +; vst %v5, 0(%r2) ; br %r14 function %sextend_i32_i128(i32) -> i128 { @@ -128,10 +128,10 @@ block0(v0: i32): } ; block0: -; lgfr %r3, %r3 -; srag %r4, %r3, 63 -; vlvgp %v16, %r4, %r3 -; vst %v16, 0(%r2) +; lgfr %r5, %r3 +; srag %r3, %r5, 63 +; vlvgp %v7, %r3, %r5 +; vst %v7, 0(%r2) ; br %r14 function %sextend_i32_i64(i32) -> i64 { @@ -151,10 +151,10 @@ block0(v0: i16): } ; block0: -; lghr %r3, %r3 -; srag %r4, %r3, 63 -; vlvgp %v16, %r4, %r3 -; vst %v16, 0(%r2) +; lghr %r5, %r3 +; srag %r3, %r5, 63 +; vlvgp %v7, %r3, %r5 +; vst %v7, 0(%r2) ; br %r14 function %sextend_i16_i64(i16) -> i64 { @@ -184,10 +184,10 @@ block0(v0: i8): } ; block0: -; lgbr %r3, %r3 -; srag %r4, %r3, 63 -; vlvgp %v16, %r4, %r3 -; vst %v16, 0(%r2) +; lgbr %r5, %r3 +; srag %r3, %r5, 63 +; vlvgp %v7, %r3, %r5 +; vst %v7, 0(%r2) ; br %r14 function %sextend_i8_i64(i8) -> i64 { @@ -332,12 +332,12 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vgbm %v5, 0 -; vceqgs %v7, %v0, %v5 -; lghi %r4, 0 -; locghine %r4, -1 -; vlvgp %v21, %r4, %r4 -; vst %v21, 0(%r2) +; vgbm %v4, 0 +; vceqgs %v6, %v0, %v4 +; lghi %r3, 0 +; locghine %r3, -1 +; vlvgp %v20, %r3, %r3 +; vst %v20, 0(%r2) ; br %r14 function %bmask_i128_i64(i128) -> i64 { @@ -348,8 +348,8 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r2) -; vgbm %v3, 0 -; vceqgs %v5, %v0, %v3 +; vgbm %v2, 0 +; vceqgs %v4, %v0, %v2 ; lghi %r2, 0 ; locghine %r2, -1 ; br %r14 @@ -362,8 +362,8 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r2) -; vgbm %v3, 0 -; vceqgs %v5, %v0, %v3 +; vgbm %v2, 0 +; vceqgs %v4, %v0, %v2 ; lhi %r2, 0 ; lochine %r2, -1 ; br %r14 @@ -376,8 +376,8 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r2) -; vgbm %v3, 0 -; vceqgs %v5, %v0, %v3 +; vgbm %v2, 0 +; vceqgs %v4, %v0, %v2 ; lhi %r2, 0 ; lochine %r2, -1 ; br %r14 @@ -390,8 +390,8 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r2) -; vgbm %v3, 0 -; vceqgs %v5, %v0, %v3 +; vgbm %v2, 0 +; vceqgs %v4, %v0, %v2 ; lhi %r2, 0 ; lochine %r2, -1 ; br %r14 @@ -404,10 +404,10 @@ block0(v0: i64, v1: i64): ; block0: ; cghi %r4, 0 -; lghi %r5, 0 -; locghilh %r5, -1 -; vlvgp %v18, %r5, %r5 -; vst %v18, 0(%r2) +; lghi %r4, 0 +; locghilh %r4, -1 +; vlvgp %v17, %r4, %r4 +; vst %v17, 0(%r2) ; br %r14 function %bmask_i64_i64(i64, i64) -> i64 { @@ -466,10 +466,10 @@ block0(v0: i32, v1: i32): ; block0: ; chi %r4, 0 -; lghi %r5, 0 -; locghilh %r5, -1 -; vlvgp %v18, %r5, %r5 -; vst %v18, 0(%r2) +; lghi %r4, 0 +; locghilh %r4, -1 +; vlvgp %v17, %r4, %r4 +; vst %v17, 0(%r2) ; br %r14 function %bmask_i32_i64(i32, i32) -> i64 { @@ -531,8 +531,8 @@ block0(v0: i16, v1: i16): ; chi %r3, 0 ; lghi %r3, 0 ; locghilh %r3, -1 -; vlvgp %v20, %r3, %r3 -; vst %v20, 0(%r2) +; vlvgp %v19, %r3, %r3 +; vst %v19, 0(%r2) ; br %r14 function %bmask_i16_i64(i16, i16) -> i64 { @@ -542,8 +542,8 @@ block0(v0: i16, v1: i16): } ; block0: -; lhr %r2, %r3 -; chi %r2, 0 +; lhr %r5, %r3 +; chi %r5, 0 ; lghi %r2, 0 ; locghilh %r2, -1 ; br %r14 @@ -555,8 +555,8 @@ block0(v0: i16, v1: i16): } ; block0: -; lhr %r2, %r3 -; chi %r2, 0 +; lhr %r5, %r3 +; chi %r5, 0 ; lhi %r2, 0 ; lochilh %r2, -1 ; br %r14 @@ -568,8 +568,8 @@ block0(v0: i16, v1: i16): } ; block0: -; lhr %r2, %r3 -; chi %r2, 0 +; lhr %r5, %r3 +; chi %r5, 0 ; lhi %r2, 0 ; lochilh %r2, -1 ; br %r14 @@ -581,8 +581,8 @@ block0(v0: i16, v1: i16): } ; block0: -; lhr %r2, %r3 -; chi %r2, 0 +; lhr %r5, %r3 +; chi %r5, 0 ; lhi %r2, 0 ; lochilh %r2, -1 ; br %r14 @@ -598,8 +598,8 @@ block0(v0: i8, v1: i8): ; chi %r3, 0 ; lghi %r3, 0 ; locghilh %r3, -1 -; vlvgp %v20, %r3, %r3 -; vst %v20, 0(%r2) +; vlvgp %v19, %r3, %r3 +; vst %v19, 0(%r2) ; br %r14 function %bmask_i8_i64(i8, i8) -> i64 { @@ -609,8 +609,8 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r3 -; chi %r2, 0 +; lbr %r5, %r3 +; chi %r5, 0 ; lghi %r2, 0 ; locghilh %r2, -1 ; br %r14 @@ -622,8 +622,8 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r3 -; chi %r2, 0 +; lbr %r5, %r3 +; chi %r5, 0 ; lhi %r2, 0 ; lochilh %r2, -1 ; br %r14 @@ -635,8 +635,8 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r3 -; chi %r2, 0 +; lbr %r5, %r3 +; chi %r5, 0 ; lhi %r2, 0 ; lochilh %r2, -1 ; br %r14 @@ -648,8 +648,8 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r3 -; chi %r2, 0 +; lbr %r5, %r3 +; chi %r5, 0 ; lhi %r2, 0 ; lochilh %r2, -1 ; br %r14 @@ -665,8 +665,8 @@ block0(v0: i8, v1: i8): ; chi %r3, 0 ; lghi %r3, 0 ; locghilh %r3, -1 -; vlvgp %v20, %r3, %r3 -; vst %v20, 0(%r2) +; vlvgp %v19, %r3, %r3 +; vst %v19, 0(%r2) ; br %r14 function %bmask_i8_i64(i8, i8) -> i64 { @@ -676,8 +676,8 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r3 -; chi %r2, 0 +; lbr %r5, %r3 +; chi %r5, 0 ; lghi %r2, 0 ; locghilh %r2, -1 ; br %r14 @@ -689,8 +689,8 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r3 -; chi %r2, 0 +; lbr %r5, %r3 +; chi %r5, 0 ; lhi %r2, 0 ; lochilh %r2, -1 ; br %r14 @@ -702,8 +702,8 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r3 -; chi %r2, 0 +; lbr %r5, %r3 +; chi %r5, 0 ; lhi %r2, 0 ; lochilh %r2, -1 ; br %r14 @@ -715,8 +715,8 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r3 -; chi %r2, 0 +; lbr %r5, %r3 +; chi %r5, 0 ; lhi %r2, 0 ; lochilh %r2, -1 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/div-traps.clif b/cranelift/filetests/filetests/isa/s390x/div-traps.clif index 922a723ef3..ca58173104 100644 --- a/cranelift/filetests/filetests/isa/s390x/div-traps.clif +++ b/cranelift/filetests/filetests/isa/s390x/div-traps.clif @@ -17,11 +17,13 @@ block0(v0: i64, v1: i64): ; llihf %r4, 2147483647 ; iilf %r4, 4294967295 ; xgr %r4, %r2 -; ngrk %r5, %r4, %r3 -; cgite %r5, -1 -; lgr %r5, %r3 -; lgr %r3, %r2 -; dsgr %r2, %r5 +; lgr %r5, %r2 +; ngr %r4, %r3 +; lgr %r2, %r3 +; cgite %r4, -1 +; lgr %r4, %r2 +; lgr %r3, %r5 +; dsgr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -34,8 +36,8 @@ block0(v0: i64): ; block0: ; lgr %r3, %r2 -; lghi %r5, 2 -; dsgr %r2, %r5 +; lghi %r4, 2 +; dsgr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -45,19 +47,21 @@ block0(v0: i32, v1: i32): return v2 } +; stmg %r7, %r15, 56(%r15) ; block0: -; lgfr %r2, %r2 +; lgfr %r5, %r2 +; lgr %r7, %r5 ; cite %r3, 0 ; iilf %r5, 2147483647 -; lgr %r4, %r2 -; xr %r5, %r4 -; nr %r5, %r3 -; lgr %r4, %r3 -; cite %r5, -1 -; lgr %r3, %r2 -; lgr %r2, %r4 -; dsgfr %r2, %r2 +; lgr %r4, %r7 +; xrk %r2, %r5, %r4 +; nrk %r4, %r2, %r3 +; lgr %r5, %r3 +; cite %r4, -1 +; lgr %r3, %r7 +; dsgfr %r2, %r5 ; lgr %r2, %r3 +; lmg %r7, %r15, 56(%r15) ; br %r14 function %sdiv_i32_imm(i32) -> i32 { @@ -69,8 +73,8 @@ block0(v0: i32): ; block0: ; lgfr %r3, %r2 -; lhi %r4, 2 -; dsgfr %r2, %r4 +; lhi %r2, 2 +; dsgfr %r2, %r2 ; lgr %r2, %r3 ; br %r14 @@ -81,14 +85,14 @@ block0(v0: i16, v1: i16): } ; block0: -; lghr %r2, %r2 +; lghr %r5, %r2 ; lhr %r4, %r3 ; cite %r4, 0 -; lhi %r5, 32767 -; lgr %r3, %r2 -; xr %r5, %r3 -; nr %r5, %r4 -; cite %r5, -1 +; lhi %r2, 32767 +; lgr %r3, %r5 +; xrk %r5, %r2, %r3 +; nrk %r2, %r5, %r4 +; cite %r2, -1 ; dsgfr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -102,8 +106,8 @@ block0(v0: i16): ; block0: ; lghr %r3, %r2 -; lhi %r4, 2 -; dsgfr %r2, %r4 +; lhi %r2, 2 +; dsgfr %r2, %r2 ; lgr %r2, %r3 ; br %r14 @@ -114,14 +118,14 @@ block0(v0: i8, v1: i8): } ; block0: -; lgbr %r2, %r2 +; lgbr %r5, %r2 ; lbr %r4, %r3 ; cite %r4, 0 -; lhi %r5, 127 -; lgr %r3, %r2 -; xr %r5, %r3 -; nr %r5, %r4 -; cite %r5, -1 +; lhi %r2, 127 +; lgr %r3, %r5 +; xrk %r5, %r2, %r3 +; nrk %r2, %r5, %r4 +; cite %r2, -1 ; dsgfr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -135,8 +139,8 @@ block0(v0: i8): ; block0: ; lgbr %r3, %r2 -; lhi %r4, 2 -; dsgfr %r2, %r4 +; lhi %r2, 2 +; dsgfr %r2, %r2 ; lgr %r2, %r3 ; br %r14 @@ -147,13 +151,13 @@ block0(v0: i64, v1: i64): } ; block0: -; lgr %r4, %r2 +; lgr %r5, %r2 ; lghi %r2, 0 ; cgite %r3, 0 -; lgr %r5, %r3 -; lgr %r3, %r4 -; lgr %r4, %r5 -; dlgr %r2, %r4 +; lgr %r4, %r3 +; lgr %r3, %r5 +; lgr %r5, %r4 +; dlgr %r2, %r5 ; lgr %r2, %r3 ; br %r14 @@ -179,13 +183,13 @@ block0(v0: i32, v1: i32): } ; block0: -; lgr %r4, %r2 +; lgr %r5, %r2 ; lhi %r2, 0 ; cite %r3, 0 -; lgr %r5, %r3 -; lgr %r3, %r4 -; lgr %r4, %r5 -; dlr %r2, %r4 +; lgr %r4, %r3 +; lgr %r3, %r5 +; lgr %r5, %r4 +; dlr %r2, %r5 ; lgr %r2, %r3 ; br %r14 @@ -210,17 +214,19 @@ block0(v0: i16, v1: i16): return v2 } +; stmg %r8, %r15, 64(%r15) ; block0: ; lgr %r4, %r3 -; lhi %r3, 0 -; lgr %r5, %r3 +; lhi %r5, 0 +; lgr %r8, %r5 ; llhr %r3, %r2 -; lgr %r2, %r4 -; llhr %r4, %r2 -; cite %r4, 0 -; lgr %r2, %r5 -; dlr %r2, %r4 +; lgr %r5, %r4 +; llhr %r5, %r5 +; cite %r5, 0 +; lgr %r2, %r8 +; dlr %r2, %r5 ; lgr %r2, %r3 +; lmg %r8, %r15, 64(%r15) ; br %r14 function %udiv_i16_imm(i16) -> i16 { @@ -231,12 +237,12 @@ block0(v0: i16): } ; block0: -; lhi %r5, 0 -; lgr %r4, %r5 +; lhi %r4, 0 +; lgr %r5, %r4 ; llhr %r3, %r2 -; lhi %r5, 2 -; lgr %r2, %r4 -; dlr %r2, %r5 +; lhi %r4, 2 +; lgr %r2, %r5 +; dlr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -246,17 +252,19 @@ block0(v0: i8, v1: i8): return v2 } +; stmg %r8, %r15, 64(%r15) ; block0: ; lgr %r4, %r3 -; lhi %r3, 0 -; lgr %r5, %r3 +; lhi %r5, 0 +; lgr %r8, %r5 ; llcr %r3, %r2 -; lgr %r2, %r4 -; llcr %r4, %r2 -; cite %r4, 0 -; lgr %r2, %r5 -; dlr %r2, %r4 +; lgr %r5, %r4 +; llcr %r5, %r5 +; cite %r5, 0 +; lgr %r2, %r8 +; dlr %r2, %r5 ; lgr %r2, %r3 +; lmg %r8, %r15, 64(%r15) ; br %r14 function %udiv_i8_imm(i8) -> i8 { @@ -267,12 +275,12 @@ block0(v0: i8): } ; block0: -; lhi %r5, 0 -; lgr %r4, %r5 +; lhi %r4, 0 +; lgr %r5, %r4 ; llcr %r3, %r2 -; lhi %r5, 2 -; lgr %r2, %r4 -; dlr %r2, %r5 +; lhi %r4, 2 +; lgr %r2, %r5 +; dlr %r2, %r4 ; lgr %r2, %r3 ; br %r14 @@ -285,10 +293,10 @@ block0(v0: i64, v1: i64): ; block0: ; cgite %r3, 0 ; cghi %r3, -1 -; lgr %r5, %r3 +; lgr %r4, %r3 ; lgr %r3, %r2 ; locghie %r3, 0 -; dsgr %r2, %r5 +; dsgr %r2, %r4 ; br %r14 function %srem_i32(i32, i32) -> i32 { @@ -298,10 +306,11 @@ block0(v0: i32, v1: i32): } ; block0: -; lgr %r4, %r3 +; lgr %r5, %r3 ; lgfr %r3, %r2 -; cite %r4, 0 -; dsgfr %r2, %r4 +; lgr %r2, %r5 +; cite %r2, 0 +; dsgfr %r2, %r2 ; br %r14 function %srem_i16(i16, i16) -> i16 { @@ -311,11 +320,11 @@ block0(v0: i16, v1: i16): } ; block0: -; lghr %r2, %r2 -; lgr %r5, %r2 +; lghr %r5, %r2 +; lgr %r2, %r5 ; lhr %r4, %r3 ; cite %r4, 0 -; lgr %r3, %r5 +; lgr %r3, %r2 ; dsgfr %r2, %r4 ; br %r14 @@ -326,11 +335,11 @@ block0(v0: i8, v1: i8): } ; block0: -; lgbr %r2, %r2 -; lgr %r5, %r2 +; lgbr %r5, %r2 +; lgr %r2, %r5 ; lbr %r4, %r3 ; cite %r4, 0 -; lgr %r3, %r5 +; lgr %r3, %r2 ; dsgfr %r2, %r4 ; br %r14 @@ -341,13 +350,13 @@ block0(v0: i64, v1: i64): } ; block0: -; lgr %r4, %r2 +; lgr %r5, %r2 ; lghi %r2, 0 ; cgite %r3, 0 -; lgr %r5, %r3 -; lgr %r3, %r4 -; lgr %r4, %r5 -; dlgr %r2, %r4 +; lgr %r4, %r3 +; lgr %r3, %r5 +; lgr %r5, %r4 +; dlgr %r2, %r5 ; br %r14 function %urem_i32(i32, i32) -> i32 { @@ -357,13 +366,13 @@ block0(v0: i32, v1: i32): } ; block0: -; lgr %r4, %r2 +; lgr %r5, %r2 ; lhi %r2, 0 ; cite %r3, 0 -; lgr %r5, %r3 -; lgr %r3, %r4 -; lgr %r4, %r5 -; dlr %r2, %r4 +; lgr %r4, %r3 +; lgr %r3, %r5 +; lgr %r5, %r4 +; dlr %r2, %r5 ; br %r14 function %urem_i16(i16, i16) -> i16 { @@ -372,16 +381,18 @@ block0(v0: i16, v1: i16): return v2 } +; stmg %r8, %r15, 64(%r15) ; block0: ; lgr %r4, %r3 -; lhi %r3, 0 -; lgr %r5, %r3 +; lhi %r5, 0 +; lgr %r8, %r5 ; llhr %r3, %r2 -; lgr %r2, %r4 -; llhr %r4, %r2 -; cite %r4, 0 -; lgr %r2, %r5 -; dlr %r2, %r4 +; lgr %r5, %r4 +; llhr %r5, %r5 +; cite %r5, 0 +; lgr %r2, %r8 +; dlr %r2, %r5 +; lmg %r8, %r15, 64(%r15) ; br %r14 function %urem_i8(i8, i8) -> i8 { @@ -390,15 +401,17 @@ block0(v0: i8, v1: i8): return v2 } +; stmg %r8, %r15, 64(%r15) ; block0: ; lgr %r4, %r3 -; lhi %r3, 0 -; lgr %r5, %r3 +; lhi %r5, 0 +; lgr %r8, %r5 ; llcr %r3, %r2 -; lgr %r2, %r4 -; llcr %r4, %r2 -; cite %r4, 0 -; lgr %r2, %r5 -; dlr %r2, %r4 +; lgr %r5, %r4 +; llcr %r5, %r5 +; cite %r5, 0 +; lgr %r2, %r8 +; dlr %r2, %r5 +; lmg %r8, %r15, 64(%r15) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/floating-point-arch13.clif b/cranelift/filetests/filetests/isa/s390x/floating-point-arch13.clif index e94238e6c9..dadca7c76f 100644 --- a/cranelift/filetests/filetests/isa/s390x/floating-point-arch13.clif +++ b/cranelift/filetests/filetests/isa/s390x/floating-point-arch13.clif @@ -10,14 +10,14 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 256 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 256 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wclfeb %v21, %f0, 0, 5 -; vlgvf %r2, %v21, 0 +; wclfeb %v20, %f0, 0, 5 +; vlgvf %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f32_i8(f32) -> i8 { @@ -29,14 +29,14 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 128 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 128 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -129 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -129 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wcfeb %v21, %f0, 0, 5 -; vlgvf %r2, %v21, 0 +; wcfeb %v20, %f0, 0, 5 +; vlgvf %r2, %v20, 0 ; br %r14 function %fcvt_to_uint_f32_i16(f32) -> i16 { @@ -48,14 +48,14 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 65536 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 65536 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wclfeb %v21, %f0, 0, 5 -; vlgvf %r2, %v21, 0 +; wclfeb %v20, %f0, 0, 5 +; vlgvf %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f32_i16(f32) -> i16 { @@ -67,14 +67,14 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 32768 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 32768 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -32769 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -32769 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wcfeb %v21, %f0, 0, 5 -; vlgvf %r2, %v21, 0 +; wcfeb %v20, %f0, 0, 5 +; vlgvf %r2, %v20, 0 ; br %r14 function %fcvt_to_uint_f32_i32(f32) -> i32 { @@ -86,14 +86,14 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 4294967300 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 4294967300 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wclfeb %v21, %f0, 0, 5 -; vlgvf %r2, %v21, 0 +; wclfeb %v20, %f0, 0, 5 +; vlgvf %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f32_i32(f32) -> i32 { @@ -105,14 +105,14 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 2147483600 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 2147483600 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -2147484000 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -2147484000 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wcfeb %v21, %f0, 0, 5 -; vlgvf %r2, %v21, 0 +; wcfeb %v20, %f0, 0, 5 +; vlgvf %r2, %v20, 0 ; br %r14 function %fcvt_to_uint_f32_i64(f32) -> i64 { @@ -124,15 +124,15 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 18446744000000000000 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 18446744000000000000 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wldeb %v21, %f0 -; wclgdb %v23, %v21, 0, 5 -; vlgvg %r2, %v23, 0 +; wldeb %v20, %f0 +; wclgdb %v22, %v20, 0, 5 +; vlgvg %r2, %v22, 0 ; br %r14 function %fcvt_to_sint_f32_i64(f32) -> i64 { @@ -144,15 +144,15 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 9223372000000000000 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 9223372000000000000 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -9223373000000000000 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -9223373000000000000 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wldeb %v21, %f0 -; wcgdb %v23, %v21, 0, 5 -; vlgvg %r2, %v23, 0 +; wldeb %v20, %f0 +; wcgdb %v22, %v20, 0, 5 +; vlgvg %r2, %v22, 0 ; br %r14 function %fcvt_to_uint_f64_i8(f64) -> i8 { @@ -164,14 +164,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 256 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 256 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wclgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wclgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f64_i8(f64) -> i8 { @@ -183,14 +183,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 128 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 128 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -129 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -129 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wcgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wcgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_uint_f64_i16(f64) -> i16 { @@ -202,14 +202,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 65536 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 65536 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wclgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wclgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f64_i16(f64) -> i16 { @@ -221,14 +221,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 32768 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 32768 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -32769 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -32769 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wcgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wcgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_uint_f64_i32(f64) -> i32 { @@ -240,14 +240,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 4294967296 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 4294967296 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wclgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wclgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f64_i32(f64) -> i32 { @@ -259,14 +259,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 2147483648 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 2147483648 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -2147483649 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -2147483649 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wcgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wcgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_uint_f64_i64(f64) -> i64 { @@ -278,14 +278,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 18446744073709552000 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 18446744073709552000 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wclgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wclgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f64_i64(f64) -> i64 { @@ -297,14 +297,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 9223372036854776000 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 9223372036854776000 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -9223372036854778000 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -9223372036854778000 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wcgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wcgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_from_uint_i8_f32(i8) -> f32 { @@ -314,9 +314,9 @@ block0(v0: i8): } ; block0: -; llcr %r5, %r2 -; vlvgf %v5, %r5, 0 -; wcelfb %f0, %f5, 0, 4 +; llcr %r4, %r2 +; vlvgf %v4, %r4, 0 +; wcelfb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_sint_i8_f32(i8) -> f32 { @@ -326,9 +326,9 @@ block0(v0: i8): } ; block0: -; lbr %r5, %r2 -; vlvgf %v5, %r5, 0 -; wcefb %f0, %f5, 0, 4 +; lbr %r4, %r2 +; vlvgf %v4, %r4, 0 +; wcefb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_uint_i16_f32(i16) -> f32 { @@ -338,9 +338,9 @@ block0(v0: i16): } ; block0: -; llhr %r5, %r2 -; vlvgf %v5, %r5, 0 -; wcelfb %f0, %f5, 0, 4 +; llhr %r4, %r2 +; vlvgf %v4, %r4, 0 +; wcelfb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_sint_i16_f32(i16) -> f32 { @@ -350,9 +350,9 @@ block0(v0: i16): } ; block0: -; lhr %r5, %r2 -; vlvgf %v5, %r5, 0 -; wcefb %f0, %f5, 0, 4 +; lhr %r4, %r2 +; vlvgf %v4, %r4, 0 +; wcefb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_uint_i32_f32(i32) -> f32 { @@ -362,8 +362,8 @@ block0(v0: i32): } ; block0: -; vlvgf %v3, %r2, 0 -; wcelfb %f0, %f3, 0, 4 +; vlvgf %v2, %r2, 0 +; wcelfb %f0, %f2, 0, 4 ; br %r14 function %fcvt_from_sint_i32_f32(i32) -> f32 { @@ -373,8 +373,8 @@ block0(v0: i32): } ; block0: -; vlvgf %v3, %r2, 0 -; wcefb %f0, %f3, 0, 4 +; vlvgf %v2, %r2, 0 +; wcefb %f0, %f2, 0, 4 ; br %r14 function %fcvt_from_uint_i64_f32(i64) -> f32 { @@ -384,9 +384,9 @@ block0(v0: i64): } ; block0: -; ldgr %f3, %r2 -; wcdlgb %f5, %f3, 0, 3 -; ledbra %f0, %f5, 4 +; ldgr %f2, %r2 +; wcdlgb %f4, %f2, 0, 3 +; ledbra %f0, %f4, 4 ; br %r14 function %fcvt_from_sint_i64_f32(i64) -> f32 { @@ -396,9 +396,9 @@ block0(v0: i64): } ; block0: -; ldgr %f3, %r2 -; wcdgb %f5, %f3, 0, 3 -; ledbra %f0, %f5, 4 +; ldgr %f2, %r2 +; wcdgb %f4, %f2, 0, 3 +; ledbra %f0, %f4, 4 ; br %r14 function %fcvt_from_uint_i8_f64(i8) -> f64 { @@ -408,9 +408,9 @@ block0(v0: i8): } ; block0: -; llgcr %r5, %r2 -; ldgr %f5, %r5 -; wcdlgb %f0, %f5, 0, 4 +; llgcr %r4, %r2 +; ldgr %f4, %r4 +; wcdlgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_sint_i8_f64(i8) -> f64 { @@ -420,9 +420,9 @@ block0(v0: i8): } ; block0: -; lgbr %r5, %r2 -; ldgr %f5, %r5 -; wcdgb %f0, %f5, 0, 4 +; lgbr %r4, %r2 +; ldgr %f4, %r4 +; wcdgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_uint_i16_f64(i16) -> f64 { @@ -432,9 +432,9 @@ block0(v0: i16): } ; block0: -; llghr %r5, %r2 -; ldgr %f5, %r5 -; wcdlgb %f0, %f5, 0, 4 +; llghr %r4, %r2 +; ldgr %f4, %r4 +; wcdlgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_sint_i16_f64(i16) -> f64 { @@ -444,9 +444,9 @@ block0(v0: i16): } ; block0: -; lghr %r5, %r2 -; ldgr %f5, %r5 -; wcdgb %f0, %f5, 0, 4 +; lghr %r4, %r2 +; ldgr %f4, %r4 +; wcdgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_uint_i32_f64(i32) -> f64 { @@ -456,9 +456,9 @@ block0(v0: i32): } ; block0: -; llgfr %r5, %r2 -; ldgr %f5, %r5 -; wcdlgb %f0, %f5, 0, 4 +; llgfr %r4, %r2 +; ldgr %f4, %r4 +; wcdlgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_sint_i32_f64(i32) -> f64 { @@ -468,9 +468,9 @@ block0(v0: i32): } ; block0: -; lgfr %r5, %r2 -; ldgr %f5, %r5 -; wcdgb %f0, %f5, 0, 4 +; lgfr %r4, %r2 +; ldgr %f4, %r4 +; wcdgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_uint_i64_f64(i64) -> f64 { @@ -480,8 +480,8 @@ block0(v0: i64): } ; block0: -; ldgr %f3, %r2 -; wcdlgb %f0, %f3, 0, 4 +; ldgr %f2, %r2 +; wcdlgb %f0, %f2, 0, 4 ; br %r14 function %fcvt_from_sint_i64_f64(i64) -> f64 { @@ -491,8 +491,8 @@ block0(v0: i64): } ; block0: -; ldgr %f3, %r2 -; wcdgb %f0, %f3, 0, 4 +; ldgr %f2, %r2 +; wcdgb %f0, %f2, 0, 4 ; br %r14 function %fcvt_to_uint_sat_f32_i8(f32) -> i8 { @@ -502,8 +502,8 @@ block0(v0: f32): } ; block0: -; wclfeb %f3, %f0, 0, 5 -; vlgvf %r2, %v3, 0 +; wclfeb %f2, %f0, 0, 5 +; vlgvf %r2, %v2, 0 ; clfi %r2, 256 ; lochih %r2, 255 ; br %r14 @@ -515,8 +515,8 @@ block0(v0: f32): } ; block0: -; wcfeb %f3, %f0, 0, 5 -; vlgvf %r2, %v3, 0 +; wcfeb %f2, %f0, 0, 5 +; vlgvf %r2, %v2, 0 ; cebr %f0, %f0 ; lochio %r2, 0 ; chi %r2, 127 @@ -532,8 +532,8 @@ block0(v0: f32): } ; block0: -; wclfeb %f3, %f0, 0, 5 -; vlgvf %r2, %v3, 0 +; wclfeb %f2, %f0, 0, 5 +; vlgvf %r2, %v2, 0 ; clfi %r2, 65535 ; lochih %r2, -1 ; br %r14 @@ -545,8 +545,8 @@ block0(v0: f32): } ; block0: -; wcfeb %f3, %f0, 0, 5 -; vlgvf %r2, %v3, 0 +; wcfeb %f2, %f0, 0, 5 +; vlgvf %r2, %v2, 0 ; cebr %f0, %f0 ; lochio %r2, 0 ; chi %r2, 32767 @@ -562,8 +562,8 @@ block0(v0: f32): } ; block0: -; wclfeb %f3, %f0, 0, 5 -; vlgvf %r2, %v3, 0 +; wclfeb %f2, %f0, 0, 5 +; vlgvf %r2, %v2, 0 ; br %r14 function %fcvt_to_sint_sat_f32_i32(f32) -> i32 { @@ -573,8 +573,8 @@ block0(v0: f32): } ; block0: -; wcfeb %f3, %f0, 0, 5 -; vlgvf %r2, %v3, 0 +; wcfeb %f2, %f0, 0, 5 +; vlgvf %r2, %v2, 0 ; cebr %f0, %f0 ; lochio %r2, 0 ; br %r14 @@ -586,9 +586,9 @@ block0(v0: f32): } ; block0: -; ldebr %f3, %f0 -; wclgdb %f5, %f3, 0, 5 -; lgdr %r2, %f5 +; ldebr %f2, %f0 +; wclgdb %f4, %f2, 0, 5 +; lgdr %r2, %f4 ; br %r14 function %fcvt_to_sint_sat_f32_i64(f32) -> i64 { @@ -598,9 +598,9 @@ block0(v0: f32): } ; block0: -; ldebr %f3, %f0 -; wcgdb %f5, %f3, 0, 5 -; lgdr %r2, %f5 +; ldebr %f2, %f0 +; wcgdb %f4, %f2, 0, 5 +; lgdr %r2, %f4 ; cebr %f0, %f0 ; locghio %r2, 0 ; br %r14 @@ -612,8 +612,8 @@ block0(v0: f64): } ; block0: -; wclgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wclgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; clgfi %r2, 256 ; locghih %r2, 255 ; br %r14 @@ -625,8 +625,8 @@ block0(v0: f64): } ; block0: -; wcgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wcgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; cdbr %f0, %f0 ; locghio %r2, 0 ; cghi %r2, 127 @@ -642,8 +642,8 @@ block0(v0: f64): } ; block0: -; wclgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wclgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; clgfi %r2, 65535 ; locghih %r2, -1 ; br %r14 @@ -655,8 +655,8 @@ block0(v0: f64): } ; block0: -; wcgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wcgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; cdbr %f0, %f0 ; locghio %r2, 0 ; cghi %r2, 32767 @@ -672,11 +672,11 @@ block0(v0: f64): } ; block0: -; wclgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 -; llilf %r5, 4294967295 -; clgr %r2, %r5 -; locgrh %r2, %r5 +; wclgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 +; llilf %r4, 4294967295 +; clgr %r2, %r4 +; locgrh %r2, %r4 ; br %r14 function %fcvt_to_sint_sat_f64_i32(f64) -> i32 { @@ -686,16 +686,16 @@ block0(v0: f64): } ; block0: -; wcgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wcgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; cdbr %f0, %f0 ; locghio %r2, 0 -; lgfi %r4, 2147483647 +; lgfi %r3, 2147483647 +; cgr %r2, %r3 +; locgrh %r2, %r3 +; lgfi %r4, -2147483648 ; cgr %r2, %r4 -; locgrh %r2, %r4 -; lgfi %r5, -2147483648 -; cgr %r2, %r5 -; locgrl %r2, %r5 +; locgrl %r2, %r4 ; br %r14 function %fcvt_to_uint_sat_f64_i64(f64) -> i64 { @@ -705,8 +705,8 @@ block0(v0: f64): } ; block0: -; wclgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wclgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; br %r14 function %fcvt_to_sint_sat_f64_i64(f64) -> i64 { @@ -716,8 +716,8 @@ block0(v0: f64): } ; block0: -; wcgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wcgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; cdbr %f0, %f0 ; locghio %r2, 0 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/floating-point.clif b/cranelift/filetests/filetests/isa/s390x/floating-point.clif index fe4a6cf41f..4a03009a58 100644 --- a/cranelift/filetests/filetests/isa/s390x/floating-point.clif +++ b/cranelift/filetests/filetests/isa/s390x/floating-point.clif @@ -395,8 +395,8 @@ block0(v0: f32, v1: f32): } ; block0: -; bras %r1, 8 ; data.f32 NaN ; le %f4, 0(%r1) -; vsel %v0, %v0, %v2, %v4 +; bras %r1, 8 ; data.f32 NaN ; le %f3, 0(%r1) +; vsel %v0, %v0, %v2, %v3 ; br %r14 function %fcopysign_f64(f64, f64) -> f64 { @@ -406,8 +406,8 @@ block0(v0: f64, v1: f64): } ; block0: -; bras %r1, 12 ; data.f64 NaN ; ld %f4, 0(%r1) -; vsel %v0, %v0, %v2, %v4 +; bras %r1, 12 ; data.f64 NaN ; ld %f3, 0(%r1) +; vsel %v0, %v0, %v2, %v3 ; br %r14 function %fcvt_to_uint_f32_i8(f32) -> i8 { @@ -419,15 +419,15 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 256 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 256 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wldeb %v21, %f0 -; wclgdb %v23, %v21, 0, 5 -; vlgvg %r2, %v23, 0 +; wldeb %v20, %f0 +; wclgdb %v22, %v20, 0, 5 +; vlgvg %r2, %v22, 0 ; br %r14 function %fcvt_to_sint_f32_i8(f32) -> i8 { @@ -439,15 +439,15 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 128 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 128 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -129 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -129 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wldeb %v21, %f0 -; wcgdb %v23, %v21, 0, 5 -; vlgvg %r2, %v23, 0 +; wldeb %v20, %f0 +; wcgdb %v22, %v20, 0, 5 +; vlgvg %r2, %v22, 0 ; br %r14 function %fcvt_to_uint_f32_i16(f32) -> i16 { @@ -459,15 +459,15 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 65536 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 65536 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wldeb %v21, %f0 -; wclgdb %v23, %v21, 0, 5 -; vlgvg %r2, %v23, 0 +; wldeb %v20, %f0 +; wclgdb %v22, %v20, 0, 5 +; vlgvg %r2, %v22, 0 ; br %r14 function %fcvt_to_sint_f32_i16(f32) -> i16 { @@ -479,15 +479,15 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 32768 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 32768 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -32769 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -32769 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wldeb %v21, %f0 -; wcgdb %v23, %v21, 0, 5 -; vlgvg %r2, %v23, 0 +; wldeb %v20, %f0 +; wcgdb %v22, %v20, 0, 5 +; vlgvg %r2, %v22, 0 ; br %r14 function %fcvt_to_uint_f32_i32(f32) -> i32 { @@ -499,15 +499,15 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 4294967300 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 4294967300 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wldeb %v21, %f0 -; wclgdb %v23, %v21, 0, 5 -; vlgvg %r2, %v23, 0 +; wldeb %v20, %f0 +; wclgdb %v22, %v20, 0, 5 +; vlgvg %r2, %v22, 0 ; br %r14 function %fcvt_to_sint_f32_i32(f32) -> i32 { @@ -519,15 +519,15 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 2147483600 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 2147483600 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -2147484000 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -2147484000 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wldeb %v21, %f0 -; wcgdb %v23, %v21, 0, 5 -; vlgvg %r2, %v23, 0 +; wldeb %v20, %f0 +; wcgdb %v22, %v20, 0, 5 +; vlgvg %r2, %v22, 0 ; br %r14 function %fcvt_to_uint_f32_i64(f32) -> i64 { @@ -539,15 +539,15 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 18446744000000000000 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 18446744000000000000 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -1 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -1 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wldeb %v21, %f0 -; wclgdb %v23, %v21, 0, 5 -; vlgvg %r2, %v23, 0 +; wldeb %v20, %f0 +; wclgdb %v22, %v20, 0, 5 +; vlgvg %r2, %v22, 0 ; br %r14 function %fcvt_to_sint_f32_i64(f32) -> i64 { @@ -559,15 +559,15 @@ block0(v0: f32): ; block0: ; cebr %f0, %f0 ; jno 6 ; trap -; bras %r1, 8 ; data.f32 9223372000000000000 ; le %f5, 0(%r1) -; cebr %f0, %f5 +; bras %r1, 8 ; data.f32 9223372000000000000 ; le %f4, 0(%r1) +; cebr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 8 ; data.f32 -9223373000000000000 ; vlef %v17, 0(%r1), 0 -; wfcsb %f0, %v17 +; bras %r1, 8 ; data.f32 -9223373000000000000 ; vlef %v16, 0(%r1), 0 +; wfcsb %f0, %v16 ; jnle 6 ; trap -; wldeb %v21, %f0 -; wcgdb %v23, %v21, 0, 5 -; vlgvg %r2, %v23, 0 +; wldeb %v20, %f0 +; wcgdb %v22, %v20, 0, 5 +; vlgvg %r2, %v22, 0 ; br %r14 function %fcvt_to_uint_f64_i8(f64) -> i8 { @@ -579,14 +579,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 256 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 256 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wclgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wclgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f64_i8(f64) -> i8 { @@ -598,14 +598,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 128 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 128 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -129 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -129 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wcgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wcgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_uint_f64_i16(f64) -> i16 { @@ -617,14 +617,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 65536 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 65536 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wclgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wclgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f64_i16(f64) -> i16 { @@ -636,14 +636,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 32768 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 32768 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -32769 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -32769 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wcgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wcgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_uint_f64_i32(f64) -> i32 { @@ -655,14 +655,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 4294967296 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 4294967296 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wclgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wclgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f64_i32(f64) -> i32 { @@ -674,14 +674,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 2147483648 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 2147483648 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -2147483649 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -2147483649 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wcgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wcgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_uint_f64_i64(f64) -> i64 { @@ -693,14 +693,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 18446744073709552000 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 18446744073709552000 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -1 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -1 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wclgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wclgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_to_sint_f64_i64(f64) -> i64 { @@ -712,14 +712,14 @@ block0(v0: f64): ; block0: ; cdbr %f0, %f0 ; jno 6 ; trap -; bras %r1, 12 ; data.f64 9223372036854776000 ; ld %f5, 0(%r1) -; cdbr %f0, %f5 +; bras %r1, 12 ; data.f64 9223372036854776000 ; ld %f4, 0(%r1) +; cdbr %f0, %f4 ; jnhe 6 ; trap -; bras %r1, 12 ; data.f64 -9223372036854778000 ; vleg %v17, 0(%r1), 0 -; wfcdb %f0, %v17 +; bras %r1, 12 ; data.f64 -9223372036854778000 ; vleg %v16, 0(%r1), 0 +; wfcdb %f0, %v16 ; jnle 6 ; trap -; wcgdb %v21, %f0, 0, 5 -; vlgvg %r2, %v21, 0 +; wcgdb %v20, %f0, 0, 5 +; vlgvg %r2, %v20, 0 ; br %r14 function %fcvt_from_uint_i8_f32(i8) -> f32 { @@ -729,10 +729,10 @@ block0(v0: i8): } ; block0: -; llgcr %r5, %r2 -; ldgr %f5, %r5 -; wcdlgb %f7, %f5, 0, 3 -; ledbra %f0, %f7, 4 +; llgcr %r4, %r2 +; ldgr %f4, %r4 +; wcdlgb %f6, %f4, 0, 3 +; ledbra %f0, %f6, 4 ; br %r14 function %fcvt_from_sint_i8_f32(i8) -> f32 { @@ -742,10 +742,10 @@ block0(v0: i8): } ; block0: -; lgbr %r5, %r2 -; ldgr %f5, %r5 -; wcdgb %f7, %f5, 0, 3 -; ledbra %f0, %f7, 4 +; lgbr %r4, %r2 +; ldgr %f4, %r4 +; wcdgb %f6, %f4, 0, 3 +; ledbra %f0, %f6, 4 ; br %r14 function %fcvt_from_uint_i16_f32(i16) -> f32 { @@ -755,10 +755,10 @@ block0(v0: i16): } ; block0: -; llghr %r5, %r2 -; ldgr %f5, %r5 -; wcdlgb %f7, %f5, 0, 3 -; ledbra %f0, %f7, 4 +; llghr %r4, %r2 +; ldgr %f4, %r4 +; wcdlgb %f6, %f4, 0, 3 +; ledbra %f0, %f6, 4 ; br %r14 function %fcvt_from_sint_i16_f32(i16) -> f32 { @@ -768,10 +768,10 @@ block0(v0: i16): } ; block0: -; lghr %r5, %r2 -; ldgr %f5, %r5 -; wcdgb %f7, %f5, 0, 3 -; ledbra %f0, %f7, 4 +; lghr %r4, %r2 +; ldgr %f4, %r4 +; wcdgb %f6, %f4, 0, 3 +; ledbra %f0, %f6, 4 ; br %r14 function %fcvt_from_uint_i32_f32(i32) -> f32 { @@ -781,10 +781,10 @@ block0(v0: i32): } ; block0: -; llgfr %r5, %r2 -; ldgr %f5, %r5 -; wcdlgb %f7, %f5, 0, 3 -; ledbra %f0, %f7, 4 +; llgfr %r4, %r2 +; ldgr %f4, %r4 +; wcdlgb %f6, %f4, 0, 3 +; ledbra %f0, %f6, 4 ; br %r14 function %fcvt_from_sint_i32_f32(i32) -> f32 { @@ -794,10 +794,10 @@ block0(v0: i32): } ; block0: -; lgfr %r5, %r2 -; ldgr %f5, %r5 -; wcdgb %f7, %f5, 0, 3 -; ledbra %f0, %f7, 4 +; lgfr %r4, %r2 +; ldgr %f4, %r4 +; wcdgb %f6, %f4, 0, 3 +; ledbra %f0, %f6, 4 ; br %r14 function %fcvt_from_uint_i64_f32(i64) -> f32 { @@ -807,9 +807,9 @@ block0(v0: i64): } ; block0: -; ldgr %f3, %r2 -; wcdlgb %f5, %f3, 0, 3 -; ledbra %f0, %f5, 4 +; ldgr %f2, %r2 +; wcdlgb %f4, %f2, 0, 3 +; ledbra %f0, %f4, 4 ; br %r14 function %fcvt_from_sint_i64_f32(i64) -> f32 { @@ -819,9 +819,9 @@ block0(v0: i64): } ; block0: -; ldgr %f3, %r2 -; wcdgb %f5, %f3, 0, 3 -; ledbra %f0, %f5, 4 +; ldgr %f2, %r2 +; wcdgb %f4, %f2, 0, 3 +; ledbra %f0, %f4, 4 ; br %r14 function %fcvt_from_uint_i8_f64(i8) -> f64 { @@ -831,9 +831,9 @@ block0(v0: i8): } ; block0: -; llgcr %r5, %r2 -; ldgr %f5, %r5 -; wcdlgb %f0, %f5, 0, 4 +; llgcr %r4, %r2 +; ldgr %f4, %r4 +; wcdlgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_sint_i8_f64(i8) -> f64 { @@ -843,9 +843,9 @@ block0(v0: i8): } ; block0: -; lgbr %r5, %r2 -; ldgr %f5, %r5 -; wcdgb %f0, %f5, 0, 4 +; lgbr %r4, %r2 +; ldgr %f4, %r4 +; wcdgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_uint_i16_f64(i16) -> f64 { @@ -855,9 +855,9 @@ block0(v0: i16): } ; block0: -; llghr %r5, %r2 -; ldgr %f5, %r5 -; wcdlgb %f0, %f5, 0, 4 +; llghr %r4, %r2 +; ldgr %f4, %r4 +; wcdlgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_sint_i16_f64(i16) -> f64 { @@ -867,9 +867,9 @@ block0(v0: i16): } ; block0: -; lghr %r5, %r2 -; ldgr %f5, %r5 -; wcdgb %f0, %f5, 0, 4 +; lghr %r4, %r2 +; ldgr %f4, %r4 +; wcdgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_uint_i32_f64(i32) -> f64 { @@ -879,9 +879,9 @@ block0(v0: i32): } ; block0: -; llgfr %r5, %r2 -; ldgr %f5, %r5 -; wcdlgb %f0, %f5, 0, 4 +; llgfr %r4, %r2 +; ldgr %f4, %r4 +; wcdlgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_sint_i32_f64(i32) -> f64 { @@ -891,9 +891,9 @@ block0(v0: i32): } ; block0: -; lgfr %r5, %r2 -; ldgr %f5, %r5 -; wcdgb %f0, %f5, 0, 4 +; lgfr %r4, %r2 +; ldgr %f4, %r4 +; wcdgb %f0, %f4, 0, 4 ; br %r14 function %fcvt_from_uint_i64_f64(i64) -> f64 { @@ -903,8 +903,8 @@ block0(v0: i64): } ; block0: -; ldgr %f3, %r2 -; wcdlgb %f0, %f3, 0, 4 +; ldgr %f2, %r2 +; wcdlgb %f0, %f2, 0, 4 ; br %r14 function %fcvt_from_sint_i64_f64(i64) -> f64 { @@ -914,8 +914,8 @@ block0(v0: i64): } ; block0: -; ldgr %f3, %r2 -; wcdgb %f0, %f3, 0, 4 +; ldgr %f2, %r2 +; wcdgb %f0, %f2, 0, 4 ; br %r14 function %fcvt_to_uint_sat_f32_i8(f32) -> i8 { @@ -925,9 +925,9 @@ block0(v0: f32): } ; block0: -; ldebr %f3, %f0 -; wclgdb %f5, %f3, 0, 5 -; lgdr %r2, %f5 +; ldebr %f2, %f0 +; wclgdb %f4, %f2, 0, 5 +; lgdr %r2, %f4 ; clgfi %r2, 256 ; locghih %r2, 255 ; br %r14 @@ -939,9 +939,9 @@ block0(v0: f32): } ; block0: -; ldebr %f3, %f0 -; wcgdb %f5, %f3, 0, 5 -; lgdr %r2, %f5 +; ldebr %f2, %f0 +; wcgdb %f4, %f2, 0, 5 +; lgdr %r2, %f4 ; cebr %f0, %f0 ; locghio %r2, 0 ; cghi %r2, 127 @@ -957,9 +957,9 @@ block0(v0: f32): } ; block0: -; ldebr %f3, %f0 -; wclgdb %f5, %f3, 0, 5 -; lgdr %r2, %f5 +; ldebr %f2, %f0 +; wclgdb %f4, %f2, 0, 5 +; lgdr %r2, %f4 ; clgfi %r2, 65535 ; locghih %r2, -1 ; br %r14 @@ -971,9 +971,9 @@ block0(v0: f32): } ; block0: -; ldebr %f3, %f0 -; wcgdb %f5, %f3, 0, 5 -; lgdr %r2, %f5 +; ldebr %f2, %f0 +; wcgdb %f4, %f2, 0, 5 +; lgdr %r2, %f4 ; cebr %f0, %f0 ; locghio %r2, 0 ; cghi %r2, 32767 @@ -989,9 +989,9 @@ block0(v0: f32): } ; block0: -; ldebr %f3, %f0 -; wclgdb %f5, %f3, 0, 5 -; lgdr %r2, %f5 +; ldebr %f2, %f0 +; wclgdb %f4, %f2, 0, 5 +; lgdr %r2, %f4 ; llilf %r3, 4294967295 ; clgr %r2, %r3 ; locgrh %r2, %r3 @@ -1004,14 +1004,14 @@ block0(v0: f32): } ; block0: -; ldebr %f3, %f0 -; wcgdb %f5, %f3, 0, 5 -; lgdr %r2, %f5 +; ldebr %f2, %f0 +; wcgdb %f4, %f2, 0, 5 +; lgdr %r2, %f4 ; cebr %f0, %f0 ; locghio %r2, 0 -; lgfi %r3, 2147483647 -; cgr %r2, %r3 -; locgrh %r2, %r3 +; lgfi %r5, 2147483647 +; cgr %r2, %r5 +; locgrh %r2, %r5 ; lgfi %r3, -2147483648 ; cgr %r2, %r3 ; locgrl %r2, %r3 @@ -1024,9 +1024,9 @@ block0(v0: f32): } ; block0: -; ldebr %f3, %f0 -; wclgdb %f5, %f3, 0, 5 -; lgdr %r2, %f5 +; ldebr %f2, %f0 +; wclgdb %f4, %f2, 0, 5 +; lgdr %r2, %f4 ; br %r14 function %fcvt_to_sint_sat_f32_i64(f32) -> i64 { @@ -1036,9 +1036,9 @@ block0(v0: f32): } ; block0: -; ldebr %f3, %f0 -; wcgdb %f5, %f3, 0, 5 -; lgdr %r2, %f5 +; ldebr %f2, %f0 +; wcgdb %f4, %f2, 0, 5 +; lgdr %r2, %f4 ; cebr %f0, %f0 ; locghio %r2, 0 ; br %r14 @@ -1050,8 +1050,8 @@ block0(v0: f64): } ; block0: -; wclgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wclgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; clgfi %r2, 256 ; locghih %r2, 255 ; br %r14 @@ -1063,8 +1063,8 @@ block0(v0: f64): } ; block0: -; wcgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wcgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; cdbr %f0, %f0 ; locghio %r2, 0 ; cghi %r2, 127 @@ -1080,8 +1080,8 @@ block0(v0: f64): } ; block0: -; wclgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wclgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; clgfi %r2, 65535 ; locghih %r2, -1 ; br %r14 @@ -1093,8 +1093,8 @@ block0(v0: f64): } ; block0: -; wcgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wcgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; cdbr %f0, %f0 ; locghio %r2, 0 ; cghi %r2, 32767 @@ -1110,11 +1110,11 @@ block0(v0: f64): } ; block0: -; wclgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 -; llilf %r5, 4294967295 -; clgr %r2, %r5 -; locgrh %r2, %r5 +; wclgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 +; llilf %r4, 4294967295 +; clgr %r2, %r4 +; locgrh %r2, %r4 ; br %r14 function %fcvt_to_sint_sat_f64_i32(f64) -> i32 { @@ -1124,16 +1124,16 @@ block0(v0: f64): } ; block0: -; wcgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wcgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; cdbr %f0, %f0 ; locghio %r2, 0 -; lgfi %r4, 2147483647 +; lgfi %r3, 2147483647 +; cgr %r2, %r3 +; locgrh %r2, %r3 +; lgfi %r4, -2147483648 ; cgr %r2, %r4 -; locgrh %r2, %r4 -; lgfi %r5, -2147483648 -; cgr %r2, %r5 -; locgrl %r2, %r5 +; locgrl %r2, %r4 ; br %r14 function %fcvt_to_uint_sat_f64_i64(f64) -> i64 { @@ -1143,8 +1143,8 @@ block0(v0: f64): } ; block0: -; wclgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wclgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; br %r14 function %fcvt_to_sint_sat_f64_i64(f64) -> i64 { @@ -1154,8 +1154,8 @@ block0(v0: f64): } ; block0: -; wcgdb %f3, %f0, 0, 5 -; lgdr %r2, %f3 +; wcgdb %f2, %f0, 0, 5 +; lgdr %r2, %f2 ; cdbr %f0, %f0 ; locghio %r2, 0 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/fpmem.clif b/cranelift/filetests/filetests/isa/s390x/fpmem.clif index 9f7b985436..9091592e30 100644 --- a/cranelift/filetests/filetests/isa/s390x/fpmem.clif +++ b/cranelift/filetests/filetests/isa/s390x/fpmem.clif @@ -28,8 +28,8 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f0, %r5 +; lrvg %r4, 0(%r2) +; ldgr %f0, %r4 ; br %r14 function %load_f32_little(i64) -> f32 { @@ -39,8 +39,8 @@ block0(v0: i64): } ; block0: -; lrv %r5, 0(%r2) -; vlvgf %v0, %r5, 0 +; lrv %r4, 0(%r2) +; vlvgf %v0, %r4, 0 ; br %r14 function %store_f64(f64, i64) { diff --git a/cranelift/filetests/filetests/isa/s390x/heap_addr.clif b/cranelift/filetests/filetests/isa/s390x/heap_addr.clif index 1968833322..acde913250 100644 --- a/cranelift/filetests/filetests/isa/s390x/heap_addr.clif +++ b/cranelift/filetests/filetests/isa/s390x/heap_addr.clif @@ -12,16 +12,17 @@ block0(v0: i64, v1: i32): } ; block0: -; llgfr %r3, %r3 -; lg %r4, 0(%r2) -; aghi %r4, 0 -; clgr %r3, %r4 +; llgfr %r5, %r3 +; lgr %r4, %r2 +; lg %r2, 0(%r4) +; aghik %r3, %r2, 0 +; clgr %r5, %r3 ; jgnh label1 ; jg label2 ; block1: -; agr %r2, %r3 -; lghi %r5, 0 -; clgr %r3, %r4 -; locgrh %r2, %r5 +; agrk %r2, %r4, %r5 +; lghi %r4, 0 +; clgr %r5, %r3 +; locgrh %r2, %r4 ; br %r14 ; block2: ; trap @@ -36,14 +37,14 @@ block0(v0: i64, v1: i32): } ; block0: -; llgfr %r5, %r3 -; clgfi %r5, 65536 +; llgfr %r4, %r3 +; clgfi %r4, 65536 ; jgnh label1 ; jg label2 ; block1: -; agr %r2, %r5 -; lghi %r3, 0 -; clgfi %r5, 65536 -; locgrh %r2, %r3 +; agr %r2, %r4 +; lghi %r5, 0 +; clgfi %r4, 65536 +; locgrh %r2, %r5 ; br %r14 ; block2: ; trap diff --git a/cranelift/filetests/filetests/isa/s390x/icmp-i128.clif b/cranelift/filetests/filetests/isa/s390x/icmp-i128.clif index 91e75492e8..abe10f1a72 100644 --- a/cranelift/filetests/filetests/isa/s390x/icmp-i128.clif +++ b/cranelift/filetests/filetests/isa/s390x/icmp-i128.clif @@ -10,7 +10,7 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r2) ; vl %v1, 0(%r3) -; vceqgs %v5, %v0, %v1 +; vceqgs %v4, %v0, %v1 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -24,7 +24,7 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r2) ; vl %v1, 0(%r3) -; vceqgs %v5, %v0, %v1 +; vceqgs %v4, %v0, %v1 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -38,7 +38,7 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r2) ; vl %v1, 0(%r3) -; vecg %v0, %v1 ; jne 10 ; vchlgs %v5, %v1, %v0 +; vecg %v0, %v1 ; jne 10 ; vchlgs %v4, %v1, %v0 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -52,7 +52,7 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r2) ; vl %v1, 0(%r3) -; vecg %v1, %v0 ; jne 10 ; vchlgs %v5, %v0, %v1 +; vecg %v1, %v0 ; jne 10 ; vchlgs %v4, %v0, %v1 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -66,7 +66,7 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r2) ; vl %v1, 0(%r3) -; vecg %v1, %v0 ; jne 10 ; vchlgs %v5, %v0, %v1 +; vecg %v1, %v0 ; jne 10 ; vchlgs %v4, %v0, %v1 ; lhi %r2, 0 ; lochinl %r2, 1 ; br %r14 @@ -80,7 +80,7 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r2) ; vl %v1, 0(%r3) -; vecg %v0, %v1 ; jne 10 ; vchlgs %v5, %v1, %v0 +; vecg %v0, %v1 ; jne 10 ; vchlgs %v4, %v1, %v0 ; lhi %r2, 0 ; lochinl %r2, 1 ; br %r14 @@ -94,7 +94,7 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r2) ; vl %v1, 0(%r3) -; veclg %v0, %v1 ; jne 10 ; vchlgs %v5, %v1, %v0 +; veclg %v0, %v1 ; jne 10 ; vchlgs %v4, %v1, %v0 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -108,7 +108,7 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r2) ; vl %v1, 0(%r3) -; veclg %v1, %v0 ; jne 10 ; vchlgs %v5, %v0, %v1 +; veclg %v1, %v0 ; jne 10 ; vchlgs %v4, %v0, %v1 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -122,7 +122,7 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r2) ; vl %v1, 0(%r3) -; veclg %v1, %v0 ; jne 10 ; vchlgs %v5, %v0, %v1 +; veclg %v1, %v0 ; jne 10 ; vchlgs %v4, %v0, %v1 ; lhi %r2, 0 ; lochinl %r2, 1 ; br %r14 @@ -136,7 +136,7 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r2) ; vl %v1, 0(%r3) -; veclg %v0, %v1 ; jne 10 ; vchlgs %v5, %v1, %v0 +; veclg %v0, %v1 ; jne 10 ; vchlgs %v4, %v1, %v0 ; lhi %r2, 0 ; lochinl %r2, 1 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/icmp.clif b/cranelift/filetests/filetests/isa/s390x/icmp.clif index 3cff7438f3..6a7fa2594d 100644 --- a/cranelift/filetests/filetests/isa/s390x/icmp.clif +++ b/cranelift/filetests/filetests/isa/s390x/icmp.clif @@ -263,9 +263,9 @@ block0(v0: i16, v1: i16): } ; block0: -; lhr %r2, %r2 -; lhr %r4, %r3 -; cr %r2, %r4 +; lhr %r5, %r2 +; lhr %r3, %r3 +; cr %r5, %r3 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -278,8 +278,8 @@ block0(v0: i16): } ; block0: -; lhr %r5, %r2 -; chi %r5, 1 +; lhr %r4, %r2 +; chi %r4, 1 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -292,8 +292,8 @@ block0(v0: i16, v1: i64): } ; block0: -; lhr %r2, %r2 -; ch %r2, 0(%r3) +; lhr %r5, %r2 +; ch %r5, 0(%r3) ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -308,8 +308,8 @@ block0(v0: i16): } ; block0: -; lhr %r5, %r2 -; chrl %r5, %sym + 0 +; lhr %r4, %r2 +; chrl %r4, %sym + 0 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -321,9 +321,9 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r2 -; lbr %r4, %r3 -; cr %r2, %r4 +; lbr %r5, %r2 +; lbr %r3, %r3 +; cr %r5, %r3 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -336,8 +336,8 @@ block0(v0: i8): } ; block0: -; lbr %r5, %r2 -; chi %r5, 1 +; lbr %r4, %r2 +; chi %r4, 1 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -350,9 +350,9 @@ block0(v0: i8, v1: i64): } ; block0: -; lbr %r2, %r2 -; lb %r4, 0(%r3) -; cr %r2, %r4 +; lbr %r5, %r2 +; lb %r3, 0(%r3) +; cr %r5, %r3 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -459,8 +459,8 @@ block0(v0: i64, v1: i64): } ; block0: -; llgh %r4, 0(%r3) -; clgr %r2, %r4 +; llgh %r3, 0(%r3) +; clgr %r2, %r3 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -554,8 +554,8 @@ block0(v0: i32, v1: i64): } ; block0: -; llh %r4, 0(%r3) -; clr %r2, %r4 +; llh %r3, 0(%r3) +; clr %r2, %r3 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -582,9 +582,9 @@ block0(v0: i16, v1: i16): } ; block0: -; llhr %r2, %r2 -; llhr %r4, %r3 -; clr %r2, %r4 +; llhr %r5, %r2 +; llhr %r3, %r3 +; clr %r5, %r3 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -597,8 +597,8 @@ block0(v0: i16): } ; block0: -; llhr %r5, %r2 -; clfi %r5, 1 +; llhr %r4, %r2 +; clfi %r4, 1 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -611,9 +611,9 @@ block0(v0: i16, v1: i64): } ; block0: -; llhr %r2, %r2 -; llh %r4, 0(%r3) -; clr %r2, %r4 +; llhr %r5, %r2 +; llh %r3, 0(%r3) +; clr %r5, %r3 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -628,8 +628,8 @@ block0(v0: i16): } ; block0: -; llhr %r5, %r2 -; clhrl %r5, %sym + 0 +; llhr %r4, %r2 +; clhrl %r4, %sym + 0 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -641,9 +641,9 @@ block0(v0: i8, v1: i8): } ; block0: -; llcr %r2, %r2 -; llcr %r4, %r3 -; clr %r2, %r4 +; llcr %r5, %r2 +; llcr %r3, %r3 +; clr %r5, %r3 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -656,8 +656,8 @@ block0(v0: i8): } ; block0: -; llcr %r5, %r2 -; clfi %r5, 1 +; llcr %r4, %r2 +; clfi %r4, 1 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 @@ -670,9 +670,9 @@ block0(v0: i8, v1: i64): } ; block0: -; llcr %r2, %r2 -; llc %r4, 0(%r3) -; clr %r2, %r4 +; llcr %r5, %r2 +; llc %r3, 0(%r3) +; clr %r5, %r3 ; lhi %r2, 0 ; lochil %r2, 1 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/load-little.clif b/cranelift/filetests/filetests/isa/s390x/load-little.clif index 329f87cd30..e3cc953376 100644 --- a/cranelift/filetests/filetests/isa/s390x/load-little.clif +++ b/cranelift/filetests/filetests/isa/s390x/load-little.clif @@ -50,8 +50,8 @@ block0(v0: i64): } ; block0: -; lrvh %r5, 0(%r2) -; llghr %r2, %r5 +; lrvh %r4, 0(%r2) +; llghr %r2, %r4 ; br %r14 function %uload16_i64_sym() -> i64 { @@ -63,8 +63,8 @@ block0: } ; block0: -; larl %r1, %sym + 0 ; lrvh %r3, 0(%r1) -; llghr %r2, %r3 +; larl %r1, %sym + 0 ; lrvh %r2, 0(%r1) +; llghr %r2, %r2 ; br %r14 function %sload16_i64(i64) -> i64 { @@ -74,8 +74,8 @@ block0(v0: i64): } ; block0: -; lrvh %r5, 0(%r2) -; lghr %r2, %r5 +; lrvh %r4, 0(%r2) +; lghr %r2, %r4 ; br %r14 function %sload16_i64_sym() -> i64 { @@ -87,8 +87,8 @@ block0: } ; block0: -; larl %r1, %sym + 0 ; lrvh %r3, 0(%r1) -; lghr %r2, %r3 +; larl %r1, %sym + 0 ; lrvh %r2, 0(%r1) +; lghr %r2, %r2 ; br %r14 function %uload32_i64(i64) -> i64 { @@ -98,8 +98,8 @@ block0(v0: i64): } ; block0: -; lrv %r5, 0(%r2) -; llgfr %r2, %r5 +; lrv %r4, 0(%r2) +; llgfr %r2, %r4 ; br %r14 function %uload32_i64_sym() -> i64 { @@ -111,8 +111,8 @@ block0: } ; block0: -; larl %r1, %sym + 0 ; lrv %r3, 0(%r1) -; llgfr %r2, %r3 +; larl %r1, %sym + 0 ; lrv %r2, 0(%r1) +; llgfr %r2, %r2 ; br %r14 function %sload32_i64(i64) -> i64 { @@ -122,8 +122,8 @@ block0(v0: i64): } ; block0: -; lrv %r5, 0(%r2) -; lgfr %r2, %r5 +; lrv %r4, 0(%r2) +; lgfr %r2, %r4 ; br %r14 function %sload32_i64_sym() -> i64 { @@ -135,8 +135,8 @@ block0: } ; block0: -; larl %r1, %sym + 0 ; lrv %r3, 0(%r1) -; lgfr %r2, %r3 +; larl %r1, %sym + 0 ; lrv %r2, 0(%r1) +; lgfr %r2, %r2 ; br %r14 function %load_i32(i64) -> i32 { @@ -188,8 +188,8 @@ block0(v0: i64): } ; block0: -; lrvh %r5, 0(%r2) -; llhr %r2, %r5 +; lrvh %r4, 0(%r2) +; llhr %r2, %r4 ; br %r14 function %uload16_i32_sym() -> i32 { @@ -201,8 +201,8 @@ block0: } ; block0: -; larl %r1, %sym + 0 ; lrvh %r3, 0(%r1) -; llhr %r2, %r3 +; larl %r1, %sym + 0 ; lrvh %r2, 0(%r1) +; llhr %r2, %r2 ; br %r14 function %sload16_i32(i64) -> i32 { @@ -212,8 +212,8 @@ block0(v0: i64): } ; block0: -; lrvh %r5, 0(%r2) -; lhr %r2, %r5 +; lrvh %r4, 0(%r2) +; lhr %r2, %r4 ; br %r14 function %sload16_i32_sym() -> i32 { @@ -225,8 +225,8 @@ block0: } ; block0: -; larl %r1, %sym + 0 ; lrvh %r3, 0(%r1) -; lhr %r2, %r3 +; larl %r1, %sym + 0 ; lrvh %r2, 0(%r1) +; lhr %r2, %r2 ; br %r14 function %load_i16(i64) -> i16 { diff --git a/cranelift/filetests/filetests/isa/s390x/multivalue-ret.clif b/cranelift/filetests/filetests/isa/s390x/multivalue-ret.clif index bbbdbba837..4a005599db 100644 --- a/cranelift/filetests/filetests/isa/s390x/multivalue-ret.clif +++ b/cranelift/filetests/filetests/isa/s390x/multivalue-ret.clif @@ -28,19 +28,19 @@ block1: return v0, v1, v2, v3, v4, v5 } -; stmg %r8, %r15, 64(%r15) +; stmg %r7, %r15, 56(%r15) ; block0: -; lgr %r12, %r2 -; lghi %r2, 1 +; lghi %r4, 1 +; lgr %r14, %r4 ; lghi %r3, 2 ; lghi %r4, 3 ; lghi %r5, 4 -; lghi %r8, 5 -; lghi %r11, 6 -; lgr %r9, %r12 -; stg %r8, 0(%r9) -; stg %r11, 8(%r9) -; lmg %r8, %r15, 64(%r15) +; lghi %r7, 5 +; lghi %r9, 6 +; stg %r7, 0(%r2) +; stg %r9, 8(%r2) +; lgr %r2, %r14 +; lmg %r7, %r15, 56(%r15) ; br %r14 function %f3() -> f64, f64, f64, f64 { @@ -75,9 +75,9 @@ block1: ; bras %r1, 12 ; data.f64 1 ; ld %f2, 0(%r1) ; bras %r1, 12 ; data.f64 2 ; ld %f4, 0(%r1) ; bras %r1, 12 ; data.f64 3 ; ld %f6, 0(%r1) -; bras %r1, 12 ; data.f64 4 ; vleg %v28, 0(%r1), 0 -; bras %r1, 12 ; data.f64 5 ; vleg %v31, 0(%r1), 0 -; vsteg %v28, 0(%r2), 0 -; vsteg %v31, 8(%r2), 0 +; bras %r1, 12 ; data.f64 4 ; vleg %v18, 0(%r1), 0 +; bras %r1, 12 ; data.f64 5 ; vleg %v20, 0(%r1), 0 +; vsteg %v18, 0(%r2), 0 +; vsteg %v20, 8(%r2), 0 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/reftypes.clif b/cranelift/filetests/filetests/isa/s390x/reftypes.clif index 793291ec7e..1fadf2f452 100644 --- a/cranelift/filetests/filetests/isa/s390x/reftypes.clif +++ b/cranelift/filetests/filetests/isa/s390x/reftypes.clif @@ -71,23 +71,24 @@ block3(v7: r64, v8: r64): ; block0: ; stg %r2, 168(%r15) ; stg %r3, 176(%r15) -; bras %r1, 12 ; data %f + 0 ; lg %r5, 0(%r1) -; basr %r14, %r5 -; la %r4, 160(%r15) -; lg %r3, 168(%r15) -; stg %r3, 0(%r4) -; lbr %r5, %r2 -; chi %r5, 0 +; bras %r1, 12 ; data %f + 0 ; lg %r3, 0(%r1) +; basr %r14, %r3 +; la %r5, 160(%r15) +; lg %r4, 168(%r15) +; stg %r4, 0(%r5) +; lbr %r2, %r2 +; chi %r2, 0 ; jgnlh label1 ; jg label3 ; block1: ; jg label2 ; block2: +; lgr %r3, %r4 ; lg %r2, 176(%r15) ; jg label5 ; block3: ; jg label4 ; block4: -; lgr %r2, %r3 +; lgr %r2, %r4 ; lg %r3, 176(%r15) ; jg label5 ; block5: diff --git a/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif b/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif index 57a118a7db..15cabd71be 100644 --- a/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif +++ b/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif @@ -10,14 +10,14 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vrepb %v7, %v1, 15 -; vlcb %v17, %v7 -; vslb %v19, %v0, %v17 -; vsl %v21, %v19, %v17 -; vsrlb %v23, %v0, %v7 -; vsrl %v25, %v23, %v7 -; vo %v27, %v21, %v25 -; vst %v27, 0(%r2) +; vrepb %v6, %v1, 15 +; vlcb %v16, %v6 +; vslb %v18, %v0, %v16 +; vsl %v20, %v18, %v16 +; vsrlb %v22, %v0, %v6 +; vsrl %v24, %v22, %v6 +; vo %v26, %v20, %v24 +; vst %v26, 0(%r2) ; br %r14 function %rotr_i128_reg(i128, i64) -> i128 { @@ -28,15 +28,15 @@ block0(v0: i128, v1: i64): ; block0: ; vl %v0, 0(%r3) -; vlvgb %v6, %r4, 0 -; vrepb %v16, %v6, 0 -; vlcb %v18, %v16 -; vslb %v20, %v0, %v18 -; vsl %v22, %v20, %v18 -; vsrlb %v24, %v0, %v16 -; vsrl %v26, %v24, %v16 -; vo %v28, %v22, %v26 -; vst %v28, 0(%r2) +; vlvgb %v5, %r4, 0 +; vrepb %v7, %v5, 0 +; vlcb %v17, %v7 +; vslb %v19, %v0, %v17 +; vsl %v21, %v19, %v17 +; vsrlb %v23, %v0, %v7 +; vsrl %v25, %v23, %v7 +; vo %v27, %v21, %v25 +; vst %v27, 0(%r2) ; br %r14 function %rotr_i128_imm(i128) -> i128 { @@ -48,14 +48,14 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vrepib %v5, 17 -; vlcb %v7, %v5 -; vslb %v17, %v0, %v7 -; vsl %v19, %v17, %v7 -; vsrlb %v21, %v0, %v5 -; vsrl %v23, %v21, %v5 -; vo %v25, %v19, %v23 -; vst %v25, 0(%r2) +; vrepib %v4, 17 +; vlcb %v6, %v4 +; vslb %v16, %v0, %v6 +; vsl %v18, %v16, %v6 +; vsrlb %v20, %v0, %v4 +; vsrl %v22, %v20, %v4 +; vo %v24, %v18, %v22 +; vst %v24, 0(%r2) ; br %r14 function %rotr_i64_vr(i64, i128) -> i64 { @@ -67,8 +67,8 @@ block0(v0: i64, v1: i128): ; block0: ; vl %v1, 0(%r3) ; vlgvg %r3, %v1, 1 -; lcr %r5, %r3 -; rllg %r2, %r2, 0(%r5) +; lcr %r4, %r3 +; rllg %r2, %r2, 0(%r4) ; br %r14 function %rotr_i64_reg(i64, i64) -> i64 { @@ -78,8 +78,8 @@ block0(v0: i64, v1: i64): } ; block0: -; lcr %r3, %r3 -; rllg %r2, %r2, 0(%r3) +; lcr %r5, %r3 +; rllg %r2, %r2, 0(%r5) ; br %r14 function %rotr_i64_imm(i64) -> i64 { @@ -102,8 +102,8 @@ block0(v0: i32, v1: i128): ; block0: ; vl %v1, 0(%r3) ; vlgvg %r3, %v1, 1 -; lcr %r5, %r3 -; rll %r2, %r2, 0(%r5) +; lcr %r4, %r3 +; rll %r2, %r2, 0(%r4) ; br %r14 function %rotr_i32_reg(i32, i32) -> i32 { @@ -113,8 +113,8 @@ block0(v0: i32, v1: i32): } ; block0: -; lcr %r3, %r3 -; rll %r2, %r2, 0(%r3) +; lcr %r5, %r3 +; rll %r2, %r2, 0(%r5) ; br %r14 function %rotr_i32_imm(i32) -> i32 { @@ -136,14 +136,14 @@ block0(v0: i16, v1: i128): ; block0: ; vl %v1, 0(%r3) -; llhr %r3, %r2 -; vlgvg %r4, %v1, 1 -; lcr %r5, %r4 +; llhr %r2, %r2 +; vlgvg %r3, %v1, 1 +; lcr %r4, %r3 +; nill %r3, 15 ; nill %r4, 15 -; nill %r5, 15 -; sllk %r5, %r3, 0(%r5) -; srlk %r3, %r3, 0(%r4) -; ork %r2, %r5, %r3 +; sllk %r4, %r2, 0(%r4) +; srlk %r2, %r2, 0(%r3) +; ork %r2, %r4, %r2 ; br %r14 function %rotr_i16_reg(i16, i16) -> i16 { @@ -153,14 +153,13 @@ block0(v0: i16, v1: i16): } ; block0: -; lgr %r4, %r3 -; llhr %r2, %r2 -; lcr %r3, %r4 -; nill %r4, 15 +; llhr %r5, %r2 +; lcr %r2, %r3 ; nill %r3, 15 -; sllk %r3, %r2, 0(%r3) -; srlk %r4, %r2, 0(%r4) -; ork %r2, %r3, %r4 +; nill %r2, 15 +; sllk %r2, %r5, 0(%r2) +; srlk %r3, %r5, 0(%r3) +; or %r2, %r3 ; br %r14 function %rotr_i16_imm(i16) -> i16 { @@ -171,10 +170,10 @@ block0(v0: i16): } ; block0: -; llhr %r5, %r2 -; sllk %r3, %r5, 6 -; srlk %r5, %r5, 10 -; ork %r2, %r3, %r5 +; llhr %r4, %r2 +; sllk %r2, %r4, 6 +; srlk %r4, %r4, 10 +; or %r2, %r4 ; br %r14 function %rotr_i8_vr(i8, i128) -> i8 { @@ -185,14 +184,14 @@ block0(v0: i8, v1: i128): ; block0: ; vl %v1, 0(%r3) -; llcr %r3, %r2 -; vlgvg %r4, %v1, 1 -; lcr %r5, %r4 +; llcr %r2, %r2 +; vlgvg %r3, %v1, 1 +; lcr %r4, %r3 +; nill %r3, 7 ; nill %r4, 7 -; nill %r5, 7 -; sllk %r5, %r3, 0(%r5) -; srlk %r3, %r3, 0(%r4) -; ork %r2, %r5, %r3 +; sllk %r4, %r2, 0(%r4) +; srlk %r2, %r2, 0(%r3) +; ork %r2, %r4, %r2 ; br %r14 function %rotr_i8_reg(i8, i8) -> i8 { @@ -202,14 +201,13 @@ block0(v0: i8, v1: i8): } ; block0: -; lgr %r4, %r3 -; llcr %r2, %r2 -; lcr %r3, %r4 -; nill %r4, 7 +; llcr %r5, %r2 +; lcr %r2, %r3 ; nill %r3, 7 -; sllk %r3, %r2, 0(%r3) -; srlk %r4, %r2, 0(%r4) -; ork %r2, %r3, %r4 +; nill %r2, 7 +; sllk %r2, %r5, 0(%r2) +; srlk %r3, %r5, 0(%r3) +; or %r2, %r3 ; br %r14 function %rotr_i8_imm(i8) -> i8 { @@ -220,10 +218,10 @@ block0(v0: i8): } ; block0: -; llcr %r5, %r2 -; sllk %r3, %r5, 5 -; srlk %r5, %r5, 3 -; ork %r2, %r3, %r5 +; llcr %r4, %r2 +; sllk %r2, %r4, 5 +; srlk %r4, %r4, 3 +; or %r2, %r4 ; br %r14 function %rotl_i128_vr(i128, i128) -> i128 { @@ -235,14 +233,14 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vrepb %v7, %v1, 15 -; vlcb %v17, %v7 -; vslb %v19, %v0, %v7 -; vsl %v21, %v19, %v7 -; vsrlb %v23, %v0, %v17 -; vsrl %v25, %v23, %v17 -; vo %v27, %v21, %v25 -; vst %v27, 0(%r2) +; vrepb %v6, %v1, 15 +; vlcb %v16, %v6 +; vslb %v18, %v0, %v6 +; vsl %v20, %v18, %v6 +; vsrlb %v22, %v0, %v16 +; vsrl %v24, %v22, %v16 +; vo %v26, %v20, %v24 +; vst %v26, 0(%r2) ; br %r14 function %rotl_i128_reg(i128, i64) -> i128 { @@ -253,15 +251,15 @@ block0(v0: i128, v1: i64): ; block0: ; vl %v0, 0(%r3) -; vlvgb %v6, %r4, 0 -; vrepb %v16, %v6, 0 -; vlcb %v18, %v16 -; vslb %v20, %v0, %v16 -; vsl %v22, %v20, %v16 -; vsrlb %v24, %v0, %v18 -; vsrl %v26, %v24, %v18 -; vo %v28, %v22, %v26 -; vst %v28, 0(%r2) +; vlvgb %v5, %r4, 0 +; vrepb %v7, %v5, 0 +; vlcb %v17, %v7 +; vslb %v19, %v0, %v7 +; vsl %v21, %v19, %v7 +; vsrlb %v23, %v0, %v17 +; vsrl %v25, %v23, %v17 +; vo %v27, %v21, %v25 +; vst %v27, 0(%r2) ; br %r14 function %rotl_i128_imm(i128) -> i128 { @@ -273,14 +271,14 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vrepib %v5, 17 -; vlcb %v7, %v5 -; vslb %v17, %v0, %v5 -; vsl %v19, %v17, %v5 -; vsrlb %v21, %v0, %v7 -; vsrl %v23, %v21, %v7 -; vo %v25, %v19, %v23 -; vst %v25, 0(%r2) +; vrepib %v4, 17 +; vlcb %v6, %v4 +; vslb %v16, %v0, %v4 +; vsl %v18, %v16, %v4 +; vsrlb %v20, %v0, %v6 +; vsrl %v22, %v20, %v6 +; vo %v24, %v18, %v22 +; vst %v24, 0(%r2) ; br %r14 function %rotl_i64_vr(i64, i128) -> i64 { @@ -357,14 +355,14 @@ block0(v0: i16, v1: i128): ; block0: ; vl %v1, 0(%r3) -; llhr %r3, %r2 -; vlgvg %r4, %v1, 1 -; lcr %r5, %r4 +; llhr %r2, %r2 +; vlgvg %r3, %v1, 1 +; lcr %r4, %r3 +; nill %r3, 15 ; nill %r4, 15 -; nill %r5, 15 -; sllk %r2, %r3, 0(%r4) -; srlk %r3, %r3, 0(%r5) -; or %r2, %r3 +; sllk %r5, %r2, 0(%r3) +; srlk %r2, %r2, 0(%r4) +; ork %r2, %r5, %r2 ; br %r14 function %rotl_i16_reg(i16, i16) -> i16 { @@ -374,12 +372,12 @@ block0(v0: i16, v1: i16): } ; block0: -; llhr %r2, %r2 -; lcr %r4, %r3 +; llhr %r5, %r2 +; lcr %r2, %r3 ; nill %r3, 15 -; nill %r4, 15 -; sllk %r3, %r2, 0(%r3) -; srlk %r4, %r2, 0(%r4) +; nill %r2, 15 +; sllk %r3, %r5, 0(%r3) +; srlk %r4, %r5, 0(%r2) ; ork %r2, %r3, %r4 ; br %r14 @@ -391,10 +389,10 @@ block0(v0: i16): } ; block0: -; llhr %r5, %r2 -; sllk %r3, %r5, 10 -; srlk %r5, %r5, 6 -; ork %r2, %r3, %r5 +; llhr %r4, %r2 +; sllk %r2, %r4, 10 +; srlk %r4, %r4, 6 +; or %r2, %r4 ; br %r14 function %rotl_i8_vr(i8, i128) -> i8 { @@ -405,14 +403,14 @@ block0(v0: i8, v1: i128): ; block0: ; vl %v1, 0(%r3) -; llcr %r3, %r2 -; vlgvg %r4, %v1, 1 -; lcr %r5, %r4 +; llcr %r2, %r2 +; vlgvg %r3, %v1, 1 +; lcr %r4, %r3 +; nill %r3, 7 ; nill %r4, 7 -; nill %r5, 7 -; sllk %r2, %r3, 0(%r4) -; srlk %r3, %r3, 0(%r5) -; or %r2, %r3 +; sllk %r5, %r2, 0(%r3) +; srlk %r2, %r2, 0(%r4) +; ork %r2, %r5, %r2 ; br %r14 function %rotl_i8_reg(i8, i8) -> i8 { @@ -422,12 +420,12 @@ block0(v0: i8, v1: i8): } ; block0: -; llcr %r2, %r2 -; lcr %r4, %r3 +; llcr %r5, %r2 +; lcr %r2, %r3 ; nill %r3, 7 -; nill %r4, 7 -; sllk %r3, %r2, 0(%r3) -; srlk %r4, %r2, 0(%r4) +; nill %r2, 7 +; sllk %r3, %r5, 0(%r3) +; srlk %r4, %r5, 0(%r2) ; ork %r2, %r3, %r4 ; br %r14 @@ -439,10 +437,10 @@ block0(v0: i8): } ; block0: -; llcr %r5, %r2 -; sllk %r3, %r5, 3 -; srlk %r5, %r5, 5 -; ork %r2, %r3, %r5 +; llcr %r4, %r2 +; sllk %r2, %r4, 3 +; srlk %r4, %r4, 5 +; or %r2, %r4 ; br %r14 function %ushr_i128_vr(i128, i128) -> i128 { @@ -454,10 +452,10 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vrepb %v7, %v1, 15 -; vsrlb %v17, %v0, %v7 -; vsrl %v19, %v17, %v7 -; vst %v19, 0(%r2) +; vrepb %v6, %v1, 15 +; vsrlb %v16, %v0, %v6 +; vsrl %v18, %v16, %v6 +; vst %v18, 0(%r2) ; br %r14 function %ushr_i128_reg(i128, i64) -> i128 { @@ -468,11 +466,11 @@ block0(v0: i128, v1: i64): ; block0: ; vl %v0, 0(%r3) -; vlvgb %v6, %r4, 0 -; vrepb %v16, %v6, 0 -; vsrlb %v18, %v0, %v16 -; vsrl %v20, %v18, %v16 -; vst %v20, 0(%r2) +; vlvgb %v5, %r4, 0 +; vrepb %v7, %v5, 0 +; vsrlb %v17, %v0, %v7 +; vsrl %v19, %v17, %v7 +; vst %v19, 0(%r2) ; br %r14 function %ushr_i128_imm(i128) -> i128 { @@ -484,10 +482,10 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vrepib %v5, 17 -; vsrlb %v7, %v0, %v5 -; vsrl %v17, %v7, %v5 -; vst %v17, 0(%r2) +; vrepib %v4, 17 +; vsrlb %v6, %v0, %v4 +; vsrl %v16, %v6, %v4 +; vst %v16, 0(%r2) ; br %r14 function %ushr_i64_vr(i64, i128) -> i64 { @@ -531,9 +529,9 @@ block0(v0: i32, v1: i128): ; block0: ; vl %v1, 0(%r3) -; vlgvg %r4, %v1, 1 -; nill %r4, 31 -; srlk %r2, %r2, 0(%r4) +; vlgvg %r3, %v1, 1 +; nill %r3, 31 +; srlk %r2, %r2, 0(%r3) ; br %r14 function %ushr_i32_reg(i32, i32) -> i32 { @@ -543,8 +541,9 @@ block0(v0: i32, v1: i32): } ; block0: -; nill %r3, 31 -; srlk %r2, %r2, 0(%r3) +; lgr %r5, %r3 +; nill %r5, 31 +; srlk %r2, %r2, 0(%r5) ; br %r14 function %ushr_i32_imm(i32) -> i32 { @@ -566,10 +565,10 @@ block0(v0: i16, v1: i128): ; block0: ; vl %v1, 0(%r3) -; llhr %r3, %r2 -; vlgvg %r2, %v1, 1 -; nill %r2, 15 -; srlk %r2, %r3, 0(%r2) +; llhr %r2, %r2 +; vlgvg %r5, %v1, 1 +; nill %r5, 15 +; srlk %r2, %r2, 0(%r5) ; br %r14 function %ushr_i16_reg(i16, i16) -> i16 { @@ -579,10 +578,9 @@ block0(v0: i16, v1: i16): } ; block0: -; llhr %r2, %r2 -; lgr %r4, %r3 -; nill %r4, 15 -; srlk %r2, %r2, 0(%r4) +; llhr %r5, %r2 +; nill %r3, 15 +; srlk %r2, %r5, 0(%r3) ; br %r14 function %ushr_i16_imm(i16) -> i16 { @@ -593,8 +591,8 @@ block0(v0: i16): } ; block0: -; llhr %r5, %r2 -; srlk %r2, %r5, 10 +; llhr %r4, %r2 +; srlk %r2, %r4, 10 ; br %r14 function %ushr_i8_vr(i8, i128) -> i8 { @@ -605,10 +603,10 @@ block0(v0: i8, v1: i128): ; block0: ; vl %v1, 0(%r3) -; llcr %r3, %r2 -; vlgvg %r2, %v1, 1 -; nill %r2, 7 -; srlk %r2, %r3, 0(%r2) +; llcr %r2, %r2 +; vlgvg %r5, %v1, 1 +; nill %r5, 7 +; srlk %r2, %r2, 0(%r5) ; br %r14 function %ushr_i8_reg(i8, i8) -> i8 { @@ -618,10 +616,9 @@ block0(v0: i8, v1: i8): } ; block0: -; llcr %r2, %r2 -; lgr %r4, %r3 -; nill %r4, 7 -; srlk %r2, %r2, 0(%r4) +; llcr %r5, %r2 +; nill %r3, 7 +; srlk %r2, %r5, 0(%r3) ; br %r14 function %ushr_i8_imm(i8) -> i8 { @@ -632,8 +629,8 @@ block0(v0: i8): } ; block0: -; llcr %r5, %r2 -; srlk %r2, %r5, 3 +; llcr %r4, %r2 +; srlk %r2, %r4, 3 ; br %r14 function %ishl_i128_vr(i128, i128) -> i128 { @@ -645,10 +642,10 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vrepb %v7, %v1, 15 -; vslb %v17, %v0, %v7 -; vsl %v19, %v17, %v7 -; vst %v19, 0(%r2) +; vrepb %v6, %v1, 15 +; vslb %v16, %v0, %v6 +; vsl %v18, %v16, %v6 +; vst %v18, 0(%r2) ; br %r14 function %ishl_i128_reg(i128, i64) -> i128 { @@ -659,11 +656,11 @@ block0(v0: i128, v1: i64): ; block0: ; vl %v0, 0(%r3) -; vlvgb %v6, %r4, 0 -; vrepb %v16, %v6, 0 -; vslb %v18, %v0, %v16 -; vsl %v20, %v18, %v16 -; vst %v20, 0(%r2) +; vlvgb %v5, %r4, 0 +; vrepb %v7, %v5, 0 +; vslb %v17, %v0, %v7 +; vsl %v19, %v17, %v7 +; vst %v19, 0(%r2) ; br %r14 function %ishl_i128_imm(i128) -> i128 { @@ -675,10 +672,10 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vrepib %v5, 17 -; vslb %v7, %v0, %v5 -; vsl %v17, %v7, %v5 -; vst %v17, 0(%r2) +; vrepib %v4, 17 +; vslb %v6, %v0, %v4 +; vsl %v16, %v6, %v4 +; vst %v16, 0(%r2) ; br %r14 function %ishl_i64_vr(i64, i128) -> i64 { @@ -722,9 +719,9 @@ block0(v0: i32, v1: i128): ; block0: ; vl %v1, 0(%r3) -; vlgvg %r4, %v1, 1 -; nill %r4, 31 -; sllk %r2, %r2, 0(%r4) +; vlgvg %r3, %v1, 1 +; nill %r3, 31 +; sllk %r2, %r2, 0(%r3) ; br %r14 function %ishl_i32_reg(i32, i32) -> i32 { @@ -734,8 +731,9 @@ block0(v0: i32, v1: i32): } ; block0: -; nill %r3, 31 -; sllk %r2, %r2, 0(%r3) +; lgr %r5, %r3 +; nill %r5, 31 +; sllk %r2, %r2, 0(%r5) ; br %r14 function %ishl_i32_imm(i32) -> i32 { @@ -757,9 +755,9 @@ block0(v0: i16, v1: i128): ; block0: ; vl %v1, 0(%r3) -; vlgvg %r4, %v1, 1 -; nill %r4, 15 -; sllk %r2, %r2, 0(%r4) +; vlgvg %r3, %v1, 1 +; nill %r3, 15 +; sllk %r2, %r2, 0(%r3) ; br %r14 function %ishl_i16_reg(i16, i16) -> i16 { @@ -769,8 +767,9 @@ block0(v0: i16, v1: i16): } ; block0: -; nill %r3, 15 -; sllk %r2, %r2, 0(%r3) +; lgr %r5, %r3 +; nill %r5, 15 +; sllk %r2, %r2, 0(%r5) ; br %r14 function %ishl_i16_imm(i16) -> i16 { @@ -792,9 +791,9 @@ block0(v0: i8, v1: i128): ; block0: ; vl %v1, 0(%r3) -; vlgvg %r4, %v1, 1 -; nill %r4, 7 -; sllk %r2, %r2, 0(%r4) +; vlgvg %r3, %v1, 1 +; nill %r3, 7 +; sllk %r2, %r2, 0(%r3) ; br %r14 function %ishl_i8_reg(i8, i8) -> i8 { @@ -804,8 +803,9 @@ block0(v0: i8, v1: i8): } ; block0: -; nill %r3, 7 -; sllk %r2, %r2, 0(%r3) +; lgr %r5, %r3 +; nill %r5, 7 +; sllk %r2, %r2, 0(%r5) ; br %r14 function %ishl_i8_imm(i8) -> i8 { @@ -828,10 +828,10 @@ block0(v0: i128, v1: i128): ; block0: ; vl %v0, 0(%r3) ; vl %v1, 0(%r4) -; vrepb %v7, %v1, 15 -; vsrab %v17, %v0, %v7 -; vsra %v19, %v17, %v7 -; vst %v19, 0(%r2) +; vrepb %v6, %v1, 15 +; vsrab %v16, %v0, %v6 +; vsra %v18, %v16, %v6 +; vst %v18, 0(%r2) ; br %r14 function %sshr_i128_reg(i128, i64) -> i128 { @@ -842,11 +842,11 @@ block0(v0: i128, v1: i64): ; block0: ; vl %v0, 0(%r3) -; vlvgb %v6, %r4, 0 -; vrepb %v16, %v6, 0 -; vsrab %v18, %v0, %v16 -; vsra %v20, %v18, %v16 -; vst %v20, 0(%r2) +; vlvgb %v5, %r4, 0 +; vrepb %v7, %v5, 0 +; vsrab %v17, %v0, %v7 +; vsra %v19, %v17, %v7 +; vst %v19, 0(%r2) ; br %r14 function %sshr_i128_imm(i128) -> i128 { @@ -858,10 +858,10 @@ block0(v0: i128): ; block0: ; vl %v0, 0(%r3) -; vrepib %v5, 17 -; vsrab %v7, %v0, %v5 -; vsra %v17, %v7, %v5 -; vst %v17, 0(%r2) +; vrepib %v4, 17 +; vsrab %v6, %v0, %v4 +; vsra %v16, %v6, %v4 +; vst %v16, 0(%r2) ; br %r14 function %sshr_i64_vr(i64, i128) -> i64 { @@ -905,9 +905,9 @@ block0(v0: i32, v1: i128): ; block0: ; vl %v1, 0(%r3) -; vlgvg %r4, %v1, 1 -; nill %r4, 31 -; srak %r2, %r2, 0(%r4) +; vlgvg %r3, %v1, 1 +; nill %r3, 31 +; srak %r2, %r2, 0(%r3) ; br %r14 function %sshr_i32_reg(i32, i32) -> i32 { @@ -917,8 +917,9 @@ block0(v0: i32, v1: i32): } ; block0: -; nill %r3, 31 -; srak %r2, %r2, 0(%r3) +; lgr %r5, %r3 +; nill %r5, 31 +; srak %r2, %r2, 0(%r5) ; br %r14 function %sshr_i32_imm(i32) -> i32 { @@ -940,10 +941,10 @@ block0(v0: i16, v1: i128): ; block0: ; vl %v1, 0(%r3) -; lhr %r3, %r2 -; vlgvg %r2, %v1, 1 -; nill %r2, 15 -; srak %r2, %r3, 0(%r2) +; lhr %r2, %r2 +; vlgvg %r5, %v1, 1 +; nill %r5, 15 +; srak %r2, %r2, 0(%r5) ; br %r14 function %sshr_i16_reg(i16, i16) -> i16 { @@ -953,10 +954,9 @@ block0(v0: i16, v1: i16): } ; block0: -; lhr %r2, %r2 -; lgr %r4, %r3 -; nill %r4, 15 -; srak %r2, %r2, 0(%r4) +; lhr %r5, %r2 +; nill %r3, 15 +; srak %r2, %r5, 0(%r3) ; br %r14 function %sshr_i16_imm(i16) -> i16 { @@ -967,8 +967,8 @@ block0(v0: i16): } ; block0: -; lhr %r5, %r2 -; srak %r2, %r5, 10 +; lhr %r4, %r2 +; srak %r2, %r4, 10 ; br %r14 function %sshr_i8_vr(i8, i128) -> i8 { @@ -979,10 +979,10 @@ block0(v0: i8, v1: i128): ; block0: ; vl %v1, 0(%r3) -; lbr %r3, %r2 -; vlgvg %r2, %v1, 1 -; nill %r2, 7 -; srak %r2, %r3, 0(%r2) +; lbr %r2, %r2 +; vlgvg %r5, %v1, 1 +; nill %r5, 7 +; srak %r2, %r2, 0(%r5) ; br %r14 function %sshr_i8_reg(i8, i8) -> i8 { @@ -992,10 +992,9 @@ block0(v0: i8, v1: i8): } ; block0: -; lbr %r2, %r2 -; lgr %r4, %r3 -; nill %r4, 7 -; srak %r2, %r2, 0(%r4) +; lbr %r5, %r2 +; nill %r3, 7 +; srak %r2, %r5, 0(%r3) ; br %r14 function %sshr_i8_imm(i8) -> i8 { @@ -1006,7 +1005,7 @@ block0(v0: i8): } ; block0: -; lbr %r5, %r2 -; srak %r2, %r5, 3 +; lbr %r4, %r2 +; srak %r2, %r4, 3 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/stack.clif b/cranelift/filetests/filetests/isa/s390x/stack.clif index d75edd6f88..f356a7fcbf 100644 --- a/cranelift/filetests/filetests/isa/s390x/stack.clif +++ b/cranelift/filetests/filetests/isa/s390x/stack.clif @@ -42,8 +42,8 @@ block0: ; aghi %r15, -8 ; block0: -; la %r4, 0(%r15) -; lg %r2, 0(%r4) +; la %r3, 0(%r15) +; lg %r2, 0(%r3) ; aghi %r15, 8 ; br %r14 @@ -58,8 +58,8 @@ block0: ; agfi %r15, -100008 ; block0: -; la %r4, 0(%r15) -; lg %r2, 0(%r4) +; la %r3, 0(%r15) +; lg %r2, 0(%r3) ; agfi %r15, 100008 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/struct-arg.clif b/cranelift/filetests/filetests/isa/s390x/struct-arg.clif index 391fd20d03..11abb7ed35 100644 --- a/cranelift/filetests/filetests/isa/s390x/struct-arg.clif +++ b/cranelift/filetests/filetests/isa/s390x/struct-arg.clif @@ -20,9 +20,9 @@ block0(v0: i64, v1: i64): } ; block0: -; llc %r4, 0(%r3) -; llc %r5, 0(%r2) -; ark %r2, %r4, %r5 +; llc %r3, 0(%r3) +; llc %r4, 0(%r2) +; ark %r2, %r3, %r4 ; br %r14 function u0:2(i64) -> i8 system_v { @@ -70,9 +70,10 @@ block0(v0: i64, v1: i64): } ; block0: -; llc %r4, 0(%r2) -; llc %r5, 0(%r3) -; ark %r2, %r4, %r5 +; lgr %r5, %r3 +; llc %r3, 0(%r2) +; llc %r4, 0(%r5) +; ark %r2, %r3, %r4 ; br %r14 function u0:5(i64, i64, i64) -> i8 system_v { @@ -103,22 +104,22 @@ block0(v0: i64, v1: i64, v2: i64): return v3 } -; stmg %r8, %r15, 64(%r15) +; stmg %r7, %r15, 56(%r15) ; aghi %r15, -1248 ; virtual_sp_offset_adjust 1248 ; block0: -; lgr %r8, %r2 -; lgr %r10, %r4 +; lgr %r7, %r2 +; lgr %r9, %r4 ; la %r2, 160(%r15) ; la %r3, 0(%r3) ; lghi %r4, 1024 ; brasl %r14, %Memcpy -; lgr %r4, %r10 +; lgr %r4, %r9 ; mvc 1184(63,%r15), 0(%r4) ; la %r3, 160(%r15) ; la %r4, 1184(%r15) -; lgr %r2, %r8 +; lgr %r2, %r7 ; brasl %r14, userextname0 -; lmg %r8, %r15, 1312(%r15) +; lmg %r7, %r15, 1304(%r15) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/tls_elf.clif b/cranelift/filetests/filetests/isa/s390x/tls_elf.clif index 20c08053ee..e23fc14d04 100644 --- a/cranelift/filetests/filetests/isa/s390x/tls_elf.clif +++ b/cranelift/filetests/filetests/isa/s390x/tls_elf.clif @@ -18,9 +18,9 @@ block0(v0: i32): ; bras %r1, 12 ; data userextname0@tlsgd ; lg %r2, 0(%r1) ; brasl %r14, %ElfTlsGetOffset:tls_gdcall:userextname0 ; ear %r3, %a0 -; sllg %r3, %r3, 32 -; ear %r3, %a1 -; agr %r2, %r3 +; sllg %r5, %r3, 32 +; ear %r5, %a1 +; agr %r2, %r5 ; lmg %r12, %r15, 256(%r15) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/vec-abi.clif b/cranelift/filetests/filetests/isa/s390x/vec-abi.clif index a18d9c8fde..2055e5836c 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-abi.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-abi.clif @@ -13,8 +13,8 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16): ; aghi %r15, -160 ; virtual_sp_offset_adjust 160 ; block0: -; bras %r1, 12 ; data %callee_be + 0 ; lg %r5, 0(%r1) -; basr %r14, %r5 +; bras %r1, 12 ; data %callee_be + 0 ; lg %r4, 0(%r1) +; basr %r14, %r4 ; lmg %r14, %r15, 272(%r15) ; br %r14 @@ -39,19 +39,19 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16): ; std %f15, 216(%r15) ; block0: ; vpdi %v24, %v24, %v24, 4 -; vpdi %v16, %v25, %v25, 4 -; verllg %v25, %v16, 32 -; vpdi %v20, %v26, %v26, 4 -; verllg %v22, %v20, 32 -; verllf %v26, %v22, 16 +; vpdi %v7, %v25, %v25, 4 +; verllg %v25, %v7, 32 +; vpdi %v19, %v26, %v26, 4 +; verllg %v21, %v19, 32 +; verllf %v26, %v21, 16 ; vpdi %v27, %v27, %v27, 4 -; verllg %v28, %v27, 32 -; verllf %v30, %v28, 16 -; verllh %v27, %v30, 8 -; bras %r1, 12 ; data %callee_le + 0 ; lg %r5, 0(%r1) -; basr %r14, %r5 -; vpdi %v6, %v24, %v24, 4 -; verllg %v24, %v6, 32 +; verllg %v27, %v27, 32 +; verllf %v29, %v27, 16 +; verllh %v27, %v29, 8 +; bras %r1, 12 ; data %callee_le + 0 ; lg %r4, 0(%r1) +; basr %r14, %r4 +; vpdi %v5, %v24, %v24, 4 +; verllg %v24, %v5, 32 ; ld %f8, 160(%r15) ; ld %f9, 168(%r15) ; ld %f10, 176(%r15) @@ -84,19 +84,19 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16): ; std %f15, 216(%r15) ; block0: ; vpdi %v24, %v24, %v24, 4 -; vpdi %v16, %v25, %v25, 4 -; verllg %v25, %v16, 32 -; vpdi %v20, %v26, %v26, 4 -; verllg %v22, %v20, 32 -; verllf %v26, %v22, 16 +; vpdi %v7, %v25, %v25, 4 +; verllg %v25, %v7, 32 +; vpdi %v19, %v26, %v26, 4 +; verllg %v21, %v19, 32 +; verllf %v26, %v21, 16 ; vpdi %v27, %v27, %v27, 4 -; verllg %v28, %v27, 32 -; verllf %v30, %v28, 16 -; verllh %v27, %v30, 8 -; bras %r1, 12 ; data %callee_be + 0 ; lg %r5, 0(%r1) -; basr %r14, %r5 -; vpdi %v6, %v24, %v24, 4 -; verllg %v24, %v6, 32 +; verllg %v27, %v27, 32 +; verllf %v29, %v27, 16 +; verllh %v27, %v29, 8 +; bras %r1, 12 ; data %callee_be + 0 ; lg %r4, 0(%r1) +; basr %r14, %r4 +; vpdi %v5, %v24, %v24, 4 +; verllg %v24, %v5, 32 ; ld %f8, 160(%r15) ; ld %f9, 168(%r15) ; ld %f10, 176(%r15) @@ -120,8 +120,8 @@ block0(v0: i64x2, v1: i32x4, v2: i16x8, v3: i8x16): ; aghi %r15, -160 ; virtual_sp_offset_adjust 160 ; block0: -; bras %r1, 12 ; data %callee_le + 0 ; lg %r5, 0(%r1) -; basr %r14, %r5 +; bras %r1, 12 ; data %callee_le + 0 ; lg %r4, 0(%r1) +; basr %r14, %r4 ; lmg %r14, %r15, 272(%r15) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/vec-arithmetic.clif b/cranelift/filetests/filetests/isa/s390x/vec-arithmetic.clif index 3f01170364..895ec748a4 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-arithmetic.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-arithmetic.clif @@ -368,9 +368,9 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vag %v4, %v24, %v25 -; vchlg %v6, %v24, %v4 -; vo %v24, %v4, %v6 +; vag %v3, %v24, %v25 +; vchlg %v5, %v24, %v3 +; vo %v24, %v3, %v5 ; br %r14 function %uadd_sat32x4(i32x4, i32x4) -> i32x4 { @@ -380,9 +380,9 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vaf %v4, %v24, %v25 -; vchlf %v6, %v24, %v4 -; vo %v24, %v4, %v6 +; vaf %v3, %v24, %v25 +; vchlf %v5, %v24, %v3 +; vo %v24, %v3, %v5 ; br %r14 function %uadd_sat16x8(i16x8, i16x8) -> i16x8 { @@ -392,9 +392,9 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vah %v4, %v24, %v25 -; vchlh %v6, %v24, %v4 -; vo %v24, %v4, %v6 +; vah %v3, %v24, %v25 +; vchlh %v5, %v24, %v3 +; vo %v24, %v3, %v5 ; br %r14 function %uadd_sat8x16(i8x16, i8x16) -> i8x16 { @@ -404,9 +404,9 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vab %v4, %v24, %v25 -; vchlb %v6, %v24, %v4 -; vo %v24, %v4, %v6 +; vab %v3, %v24, %v25 +; vchlb %v5, %v24, %v3 +; vo %v24, %v3, %v5 ; br %r14 function %sadd_sat32x4(i32x4, i32x4) -> i32x4 { @@ -416,13 +416,13 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vuphf %v4, %v24 -; vuphf %v6, %v25 -; vag %v16, %v4, %v6 -; vuplf %v18, %v24 -; vuplf %v20, %v25 -; vag %v22, %v18, %v20 -; vpksg %v24, %v16, %v22 +; vuphf %v3, %v24 +; vuphf %v5, %v25 +; vag %v7, %v3, %v5 +; vuplf %v17, %v24 +; vuplf %v19, %v25 +; vag %v21, %v17, %v19 +; vpksg %v24, %v7, %v21 ; br %r14 function %sadd_sat16x8(i16x8, i16x8) -> i16x8 { @@ -432,13 +432,13 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vuphh %v4, %v24 -; vuphh %v6, %v25 -; vaf %v16, %v4, %v6 -; vuplh %v18, %v24 -; vuplh %v20, %v25 -; vaf %v22, %v18, %v20 -; vpksf %v24, %v16, %v22 +; vuphh %v3, %v24 +; vuphh %v5, %v25 +; vaf %v7, %v3, %v5 +; vuplh %v17, %v24 +; vuplh %v19, %v25 +; vaf %v21, %v17, %v19 +; vpksf %v24, %v7, %v21 ; br %r14 function %sadd_sat8x16(i8x16, i8x16) -> i8x16 { @@ -448,13 +448,13 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vuphb %v4, %v24 -; vuphb %v6, %v25 -; vah %v16, %v4, %v6 -; vuplb %v18, %v24 -; vuplb %v20, %v25 -; vah %v22, %v18, %v20 -; vpksh %v24, %v16, %v22 +; vuphb %v3, %v24 +; vuphb %v5, %v25 +; vah %v7, %v3, %v5 +; vuplb %v17, %v24 +; vuplb %v19, %v25 +; vah %v21, %v17, %v19 +; vpksh %v24, %v7, %v21 ; br %r14 function %usub_sat64x2(i64x2, i64x2) -> i64x2 { @@ -464,9 +464,9 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vsg %v4, %v24, %v25 -; vchlg %v6, %v24, %v25 -; vn %v24, %v4, %v6 +; vsg %v3, %v24, %v25 +; vchlg %v5, %v24, %v25 +; vn %v24, %v3, %v5 ; br %r14 function %usub_sat32x4(i32x4, i32x4) -> i32x4 { @@ -476,9 +476,9 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vsf %v4, %v24, %v25 -; vchlf %v6, %v24, %v25 -; vn %v24, %v4, %v6 +; vsf %v3, %v24, %v25 +; vchlf %v5, %v24, %v25 +; vn %v24, %v3, %v5 ; br %r14 function %usub_sat16x8(i16x8, i16x8) -> i16x8 { @@ -488,9 +488,9 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vsh %v4, %v24, %v25 -; vchlh %v6, %v24, %v25 -; vn %v24, %v4, %v6 +; vsh %v3, %v24, %v25 +; vchlh %v5, %v24, %v25 +; vn %v24, %v3, %v5 ; br %r14 function %usub_sat8x16(i8x16, i8x16) -> i8x16 { @@ -500,9 +500,9 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vsb %v4, %v24, %v25 -; vchlb %v6, %v24, %v25 -; vn %v24, %v4, %v6 +; vsb %v3, %v24, %v25 +; vchlb %v5, %v24, %v25 +; vn %v24, %v3, %v5 ; br %r14 function %ssub_sat32x4(i32x4, i32x4) -> i32x4 { @@ -512,13 +512,13 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vuphf %v4, %v24 -; vuphf %v6, %v25 -; vsg %v16, %v4, %v6 -; vuplf %v18, %v24 -; vuplf %v20, %v25 -; vsg %v22, %v18, %v20 -; vpksg %v24, %v16, %v22 +; vuphf %v3, %v24 +; vuphf %v5, %v25 +; vsg %v7, %v3, %v5 +; vuplf %v17, %v24 +; vuplf %v19, %v25 +; vsg %v21, %v17, %v19 +; vpksg %v24, %v7, %v21 ; br %r14 function %ssub_sat16x8(i16x8, i16x8) -> i16x8 { @@ -528,13 +528,13 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vuphh %v4, %v24 -; vuphh %v6, %v25 -; vsf %v16, %v4, %v6 -; vuplh %v18, %v24 -; vuplh %v20, %v25 -; vsf %v22, %v18, %v20 -; vpksf %v24, %v16, %v22 +; vuphh %v3, %v24 +; vuphh %v5, %v25 +; vsf %v7, %v3, %v5 +; vuplh %v17, %v24 +; vuplh %v19, %v25 +; vsf %v21, %v17, %v19 +; vpksf %v24, %v7, %v21 ; br %r14 function %ssub_sat8x16(i8x16, i8x16) -> i8x16 { @@ -544,13 +544,13 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vuphb %v4, %v24 -; vuphb %v6, %v25 -; vsh %v16, %v4, %v6 -; vuplb %v18, %v24 -; vuplb %v20, %v25 -; vsh %v22, %v18, %v20 -; vpksh %v24, %v16, %v22 +; vuphb %v3, %v24 +; vuphb %v5, %v25 +; vsh %v7, %v3, %v5 +; vuplb %v17, %v24 +; vuplb %v19, %v25 +; vsh %v21, %v17, %v19 +; vpksh %v24, %v7, %v21 ; br %r14 function %iadd_pairwise_i32x4_be(i32x4, i32x4) -> i32x4 { @@ -560,12 +560,12 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vrepib %v4, 32 -; vsrlb %v6, %v24, %v4 -; vaf %v16, %v24, %v6 -; vsrlb %v18, %v25, %v4 -; vaf %v20, %v25, %v18 -; vpkg %v24, %v16, %v20 +; vrepib %v3, 32 +; vsrlb %v5, %v24, %v3 +; vaf %v7, %v24, %v5 +; vsrlb %v17, %v25, %v3 +; vaf %v19, %v25, %v17 +; vpkg %v24, %v7, %v19 ; br %r14 function %iadd_pairwise_i16x8_be(i16x8, i16x8) -> i16x8 { @@ -575,12 +575,12 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vrepib %v4, 16 -; vsrlb %v6, %v24, %v4 -; vah %v16, %v24, %v6 -; vsrlb %v18, %v25, %v4 -; vah %v20, %v25, %v18 -; vpkf %v24, %v16, %v20 +; vrepib %v3, 16 +; vsrlb %v5, %v24, %v3 +; vah %v7, %v24, %v5 +; vsrlb %v17, %v25, %v3 +; vah %v19, %v25, %v17 +; vpkf %v24, %v7, %v19 ; br %r14 function %iadd_pairwise_i8x16_be(i8x16, i8x16) -> i8x16 { @@ -590,12 +590,12 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vrepib %v4, 8 -; vsrlb %v6, %v24, %v4 -; vab %v16, %v24, %v6 -; vsrlb %v18, %v25, %v4 -; vab %v20, %v25, %v18 -; vpkh %v24, %v16, %v20 +; vrepib %v3, 8 +; vsrlb %v5, %v24, %v3 +; vab %v7, %v24, %v5 +; vsrlb %v17, %v25, %v3 +; vab %v19, %v25, %v17 +; vpkh %v24, %v7, %v19 ; br %r14 function %iadd_pairwise_i32x4_le(i32x4, i32x4) -> i32x4 wasmtime_system_v { @@ -605,12 +605,12 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vrepib %v4, 32 -; vsrlb %v6, %v24, %v4 -; vaf %v16, %v24, %v6 -; vsrlb %v18, %v25, %v4 -; vaf %v20, %v25, %v18 -; vpkg %v24, %v20, %v16 +; vrepib %v3, 32 +; vsrlb %v5, %v24, %v3 +; vaf %v7, %v24, %v5 +; vsrlb %v17, %v25, %v3 +; vaf %v19, %v25, %v17 +; vpkg %v24, %v19, %v7 ; br %r14 function %iadd_pairwise_i16x8_le(i16x8, i16x8) -> i16x8 wasmtime_system_v { @@ -620,12 +620,12 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vrepib %v4, 16 -; vsrlb %v6, %v24, %v4 -; vah %v16, %v24, %v6 -; vsrlb %v18, %v25, %v4 -; vah %v20, %v25, %v18 -; vpkf %v24, %v20, %v16 +; vrepib %v3, 16 +; vsrlb %v5, %v24, %v3 +; vah %v7, %v24, %v5 +; vsrlb %v17, %v25, %v3 +; vah %v19, %v25, %v17 +; vpkf %v24, %v19, %v7 ; br %r14 function %iadd_pairwise_i8x16_le(i8x16, i8x16) -> i8x16 wasmtime_system_v { @@ -635,12 +635,12 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vrepib %v4, 8 -; vsrlb %v6, %v24, %v4 -; vab %v16, %v24, %v6 -; vsrlb %v18, %v25, %v4 -; vab %v20, %v25, %v18 -; vpkh %v24, %v20, %v16 +; vrepib %v3, 8 +; vsrlb %v5, %v24, %v3 +; vab %v7, %v24, %v5 +; vsrlb %v17, %v25, %v3 +; vab %v19, %v25, %v17 +; vpkh %v24, %v19, %v7 ; br %r14 function %imul_i64x2(i64x2, i64x2) -> i64x2 { @@ -650,13 +650,13 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vlgvg %r2, %v24, 0 -; vlgvg %r4, %v25, 0 -; msgr %r2, %r4 -; vlgvg %r4, %v24, 1 -; vlgvg %r3, %v25, 1 -; msgr %r4, %r3 -; vlvgp %v24, %r2, %r4 +; vlgvg %r5, %v24, 0 +; vlgvg %r3, %v25, 0 +; msgr %r5, %r3 +; vlgvg %r3, %v24, 1 +; vlgvg %r2, %v25, 1 +; msgr %r3, %r2 +; vlvgp %v24, %r5, %r3 ; br %r14 function %imul_i32x4(i32x4, i32x4) -> i32x4 { @@ -699,12 +699,11 @@ block0(v0: i64x2, v1: i64x2): ; vlgvg %r3, %v24, 0 ; vlgvg %r4, %v25, 0 ; mlgr %r2, %r4 -; lgr %r4, %r2 +; lgr %r5, %r2 ; vlgvg %r3, %v24, 1 -; vlgvg %r5, %v25, 1 -; mlgr %r2, %r5 -; lgr %r3, %r2 -; vlvgp %v24, %r4, %r3 +; vlgvg %r4, %v25, 1 +; mlgr %r2, %r4 +; vlvgp %v24, %r5, %r2 ; br %r14 function %umulhi_i32x4(i32x4, i32x4) -> i32x4 { @@ -744,15 +743,14 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vlgvg %r2, %v24, 0 -; vlgvg %r4, %v25, 0 -; mgrk %r2, %r2, %r4 +; vlgvg %r5, %v24, 0 +; vlgvg %r3, %v25, 0 +; mgrk %r2, %r5, %r3 ; lgr %r5, %r2 -; vlgvg %r4, %v24, 1 -; vlgvg %r2, %v25, 1 -; mgrk %r2, %r4, %r2 -; lgr %r3, %r2 -; vlvgp %v24, %r5, %r3 +; vlgvg %r2, %v24, 1 +; vlgvg %r4, %v25, 1 +; mgrk %r2, %r2, %r4 +; vlvgp %v24, %r5, %r2 ; br %r14 function %smulhi_i32x4(i32x4, i32x4) -> i32x4 { @@ -792,9 +790,9 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vmeh %v4, %v24, %v25 -; vmoh %v6, %v24, %v25 -; vaf %v24, %v4, %v6 +; vmeh %v3, %v24, %v25 +; vmoh %v5, %v24, %v25 +; vaf %v24, %v3, %v5 ; br %r14 function %sqmul_round_sat(i16x8, i16x8) -> i16x8 { @@ -804,19 +802,19 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vuphh %v4, %v24 -; vuphh %v6, %v25 -; vmlf %v16, %v4, %v6 -; vgmf %v18, 17, 17 -; vaf %v20, %v16, %v18 -; vesraf %v22, %v20, 15 -; vuplh %v24, %v24 -; vuplh %v26, %v25 -; vmlf %v28, %v24, %v26 -; vgmf %v30, 17, 17 -; vaf %v0, %v28, %v30 -; vesraf %v2, %v0, 15 -; vpksf %v24, %v22, %v2 +; vuphh %v3, %v24 +; vuphh %v5, %v25 +; vmlf %v7, %v3, %v5 +; vgmf %v17, 17, 17 +; vaf %v19, %v7, %v17 +; vesraf %v21, %v19, 15 +; vuplh %v23, %v24 +; vuplh %v25, %v25 +; vmlf %v27, %v23, %v25 +; vgmf %v29, 17, 17 +; vaf %v31, %v27, %v29 +; vesraf %v1, %v31, 15 +; vpksf %v24, %v21, %v1 ; br %r14 function %sqmul_round_sat(i32x4, i32x4) -> i32x4 { @@ -826,30 +824,30 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vuphf %v4, %v24 -; vuphf %v6, %v25 -; lgdr %r2, %f4 -; lgdr %r4, %f6 -; msgr %r2, %r4 -; vlgvg %r4, %v4, 1 -; vlgvg %r3, %v6, 1 -; msgr %r4, %r3 -; vlvgp %v28, %r2, %r4 -; vgmg %v30, 33, 33 -; vag %v0, %v28, %v30 -; vesrag %v2, %v0, 31 -; vuplf %v4, %v24 -; vuplf %v6, %v25 -; lgdr %r2, %f4 -; lgdr %r4, %f6 -; msgr %r2, %r4 -; vlgvg %r4, %v4, 1 -; vlgvg %r3, %v6, 1 -; msgr %r4, %r3 -; vlvgp %v28, %r2, %r4 -; vgmg %v30, 33, 33 -; vag %v0, %v28, %v30 -; vesrag %v3, %v0, 31 -; vpksg %v24, %v2, %v3 +; vuphf %v3, %v24 +; vuphf %v5, %v25 +; lgdr %r5, %f3 +; lgdr %r3, %f5 +; msgr %r5, %r3 +; vlgvg %r3, %v3, 1 +; vlgvg %r2, %v5, 1 +; msgr %r3, %r2 +; vlvgp %v27, %r5, %r3 +; vgmg %v29, 33, 33 +; vag %v31, %v27, %v29 +; vesrag %v1, %v31, 31 +; vuplf %v3, %v24 +; vuplf %v5, %v25 +; lgdr %r5, %f3 +; lgdr %r3, %f5 +; msgr %r5, %r3 +; vlgvg %r3, %v3, 1 +; vlgvg %r2, %v5, 1 +; msgr %r3, %r2 +; vlvgp %v27, %r5, %r3 +; vgmg %v29, 33, 33 +; vag %v31, %v27, %v29 +; vesrag %v2, %v31, 31 +; vpksg %v24, %v1, %v2 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/vec-bitcast.clif b/cranelift/filetests/filetests/isa/s390x/vec-bitcast.clif index c0d8ae4563..961142e1c0 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-bitcast.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-bitcast.clif @@ -21,9 +21,9 @@ block0(v0: i64x2): } ; block0: -; vpdi %v3, %v24, %v24, 4 -; vpdi %v5, %v3, %v3, 4 -; verllg %v24, %v5, 32 +; vpdi %v2, %v24, %v24, 4 +; vpdi %v4, %v2, %v2, 4 +; verllg %v24, %v4, 32 ; br %r14 function %bitcast_i64x2_i32x4(i64x2) -> i32x4 wasmtime_system_v { @@ -33,9 +33,9 @@ block0(v0: i64x2): } ; block0: -; vpdi %v3, %v24, %v24, 4 -; vpdi %v5, %v3, %v3, 4 -; verllg %v24, %v5, 32 +; vpdi %v2, %v24, %v24, 4 +; vpdi %v4, %v2, %v2, 4 +; verllg %v24, %v4, 32 ; br %r14 function %bitcast_i64x2_i32x4(i64x2) -> i32x4 wasmtime_system_v { diff --git a/cranelift/filetests/filetests/isa/s390x/vec-conversions-le-lane.clif b/cranelift/filetests/filetests/isa/s390x/vec-conversions-le-lane.clif index c4432afad5..249d80ce92 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-conversions-le-lane.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-conversions-le-lane.clif @@ -38,10 +38,10 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vgbm %v4, 0 -; vmxg %v6, %v24, %v4 -; vmxg %v16, %v25, %v4 -; vpklsg %v24, %v16, %v6 +; vgbm %v3, 0 +; vmxg %v5, %v24, %v3 +; vmxg %v7, %v25, %v3 +; vpklsg %v24, %v7, %v5 ; br %r14 function %unarrow_i32x4_i16x8(i32x4, i32x4) -> i16x8 wasmtime_system_v { @@ -51,10 +51,10 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vgbm %v4, 0 -; vmxf %v6, %v24, %v4 -; vmxf %v16, %v25, %v4 -; vpklsf %v24, %v16, %v6 +; vgbm %v3, 0 +; vmxf %v5, %v24, %v3 +; vmxf %v7, %v25, %v3 +; vpklsf %v24, %v7, %v5 ; br %r14 function %unarrow_i16x8_i8x16(i16x8, i16x8) -> i8x16 wasmtime_system_v { @@ -64,10 +64,10 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vgbm %v4, 0 -; vmxh %v6, %v24, %v4 -; vmxh %v16, %v25, %v4 -; vpklsh %v24, %v16, %v6 +; vgbm %v3, 0 +; vmxh %v5, %v24, %v3 +; vmxh %v7, %v25, %v3 +; vpklsh %v24, %v7, %v5 ; br %r14 function %uunarrow_i64x2_i32x4(i64x2, i64x2) -> i32x4 wasmtime_system_v { diff --git a/cranelift/filetests/filetests/isa/s390x/vec-conversions.clif b/cranelift/filetests/filetests/isa/s390x/vec-conversions.clif index f675ddf478..37dccadf94 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-conversions.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-conversions.clif @@ -38,10 +38,10 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vgbm %v4, 0 -; vmxg %v6, %v24, %v4 -; vmxg %v16, %v25, %v4 -; vpklsg %v24, %v6, %v16 +; vgbm %v3, 0 +; vmxg %v5, %v24, %v3 +; vmxg %v7, %v25, %v3 +; vpklsg %v24, %v5, %v7 ; br %r14 function %unarrow_i32x4_i16x8(i32x4, i32x4) -> i16x8 { @@ -51,10 +51,10 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vgbm %v4, 0 -; vmxf %v6, %v24, %v4 -; vmxf %v16, %v25, %v4 -; vpklsf %v24, %v6, %v16 +; vgbm %v3, 0 +; vmxf %v5, %v24, %v3 +; vmxf %v7, %v25, %v3 +; vpklsf %v24, %v5, %v7 ; br %r14 function %unarrow_i16x8_i8x16(i16x8, i16x8) -> i8x16 { @@ -64,10 +64,10 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vgbm %v4, 0 -; vmxh %v6, %v24, %v4 -; vmxh %v16, %v25, %v4 -; vpklsh %v24, %v6, %v16 +; vgbm %v3, 0 +; vmxh %v5, %v24, %v3 +; vmxh %v7, %v25, %v3 +; vpklsh %v24, %v5, %v7 ; br %r14 function %uunarrow_i64x2_i32x4(i64x2, i64x2) -> i32x4 { diff --git a/cranelift/filetests/filetests/isa/s390x/vec-fcmp.clif b/cranelift/filetests/filetests/isa/s390x/vec-fcmp.clif index d85d53b0bb..16bc92e6ee 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-fcmp.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-fcmp.clif @@ -18,8 +18,8 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfcedb %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vfcedb %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %fcmp_gt_f64x2(f64x2, f64x2) -> i64x2 { @@ -69,9 +69,9 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdb %v4, %v24, %v25 -; vfchdb %v6, %v25, %v24 -; vno %v24, %v4, %v6 +; vfchdb %v3, %v24, %v25 +; vfchdb %v5, %v25, %v24 +; vno %v24, %v3, %v5 ; br %r14 function %fcmp_one_f64x2(f64x2, f64x2) -> i64x2 { @@ -81,9 +81,9 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdb %v4, %v24, %v25 -; vfchdb %v6, %v25, %v24 -; vo %v24, %v4, %v6 +; vfchdb %v3, %v24, %v25 +; vfchdb %v5, %v25, %v24 +; vo %v24, %v3, %v5 ; br %r14 function %fcmp_ugt_f64x2(f64x2, f64x2) -> i64x2 { @@ -93,8 +93,8 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedb %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vfchedb %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %fcmp_ult_f64x2(f64x2, f64x2) -> i64x2 { @@ -104,8 +104,8 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedb %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vfchedb %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %fcmp_uge_f64x2(f64x2, f64x2) -> i64x2 { @@ -115,8 +115,8 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdb %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vfchdb %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %fcmp_ule_f64x2(f64x2, f64x2) -> i64x2 { @@ -126,8 +126,8 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdb %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vfchdb %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %fcmp_ord_f64x2(f64x2, f64x2) -> i64x2 { @@ -137,9 +137,9 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedb %v4, %v24, %v25 -; vfchedb %v6, %v25, %v24 -; vo %v24, %v4, %v6 +; vfchedb %v3, %v24, %v25 +; vfchedb %v5, %v25, %v24 +; vo %v24, %v3, %v5 ; br %r14 function %fcmp_uno_f64x2(f64x2, f64x2) -> i64x2 { @@ -149,9 +149,9 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedb %v4, %v24, %v25 -; vfchedb %v6, %v25, %v24 -; vno %v24, %v4, %v6 +; vfchedb %v3, %v24, %v25 +; vfchedb %v5, %v25, %v24 +; vno %v24, %v3, %v5 ; br %r14 function %fcmp_eq_f32x4(f32x4, f32x4) -> i32x4 { @@ -171,8 +171,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vfcesb %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vfcesb %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %fcmp_gt_f32x4(f32x4, f32x4) -> i32x4 { @@ -222,9 +222,9 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vfchsb %v4, %v24, %v25 -; vfchsb %v6, %v25, %v24 -; vno %v24, %v4, %v6 +; vfchsb %v3, %v24, %v25 +; vfchsb %v5, %v25, %v24 +; vno %v24, %v3, %v5 ; br %r14 function %fcmp_one_f32x4(f32x4, f32x4) -> i32x4 { @@ -234,9 +234,9 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vfchsb %v4, %v24, %v25 -; vfchsb %v6, %v25, %v24 -; vo %v24, %v4, %v6 +; vfchsb %v3, %v24, %v25 +; vfchsb %v5, %v25, %v24 +; vo %v24, %v3, %v5 ; br %r14 function %fcmp_ugt_f32x4(f32x4, f32x4) -> i32x4 { @@ -246,8 +246,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vfchesb %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vfchesb %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %fcmp_ult_f32x4(f32x4, f32x4) -> i32x4 { @@ -257,8 +257,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vfchesb %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vfchesb %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %fcmp_uge_f32x4(f32x4, f32x4) -> i32x4 { @@ -268,8 +268,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vfchsb %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vfchsb %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %fcmp_ule_f32x4(f32x4, f32x4) -> i32x4 { @@ -279,8 +279,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vfchsb %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vfchsb %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %fcmp_ord_f32x4(f32x4, f32x4) -> i32x4 { @@ -290,9 +290,9 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vfchesb %v4, %v24, %v25 -; vfchesb %v6, %v25, %v24 -; vo %v24, %v4, %v6 +; vfchesb %v3, %v24, %v25 +; vfchesb %v5, %v25, %v24 +; vo %v24, %v3, %v5 ; br %r14 function %fcmp_uno_f32x4(f32x4, f32x4) -> i32x4 { @@ -302,8 +302,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vfchesb %v4, %v24, %v25 -; vfchesb %v6, %v25, %v24 -; vno %v24, %v4, %v6 +; vfchesb %v3, %v24, %v25 +; vfchesb %v5, %v25, %v24 +; vno %v24, %v3, %v5 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/vec-fp-arch13.clif b/cranelift/filetests/filetests/isa/s390x/vec-fp-arch13.clif index 4c00c348d4..ec89bc215a 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-fp-arch13.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-fp-arch13.clif @@ -59,10 +59,10 @@ block0(v0: f32x4): } ; block0: -; vcfeb %v3, %v24, 0, 5 -; vgbm %v5, 0 -; vfcesb %v7, %v24, %v24 -; vsel %v24, %v3, %v5, %v7 +; vcfeb %v2, %v24, 0, 5 +; vgbm %v4, 0 +; vfcesb %v6, %v24, %v24 +; vsel %v24, %v2, %v4, %v6 ; br %r14 function %fcvt_to_uint_sat_f64x2_i64x2(f64x2) -> i64x2 { @@ -82,9 +82,9 @@ block0(v0: f64x2): } ; block0: -; vcgdb %v3, %v24, 0, 5 -; vgbm %v5, 0 -; vfcedb %v7, %v24, %v24 -; vsel %v24, %v3, %v5, %v7 +; vcgdb %v2, %v24, 0, 5 +; vgbm %v4, 0 +; vfcedb %v6, %v24, %v24 +; vsel %v24, %v2, %v4, %v6 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/vec-fp.clif b/cranelift/filetests/filetests/isa/s390x/vec-fp.clif index 4d87a61ab2..e93a9fcaef 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-fp.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-fp.clif @@ -288,8 +288,8 @@ block0(v0: f32x4): } ; block0: -; vmrhf %v3, %v24, %v24 -; vldeb %v24, %v3 +; vmrhf %v2, %v24, %v24 +; vldeb %v24, %v2 ; br %r14 function %fvpromote_low_f32x4_le(f32x4) -> f64x2 wasmtime_system_v { @@ -299,8 +299,8 @@ block0(v0: f32x4): } ; block0: -; vmrlf %v3, %v24, %v24 -; vldeb %v24, %v3 +; vmrlf %v2, %v24, %v24 +; vldeb %v24, %v2 ; br %r14 function %fvdemote_f64x2_be(f64x2) -> f32x4 { @@ -310,10 +310,10 @@ block0(v0: f64x2): } ; block0: -; vledb %v3, %v24, 0, 0 -; vesrlg %v5, %v3, 32 -; vgbm %v7, 0 -; vpkg %v24, %v5, %v7 +; vledb %v2, %v24, 0, 0 +; vesrlg %v4, %v2, 32 +; vgbm %v6, 0 +; vpkg %v24, %v4, %v6 ; br %r14 function %fvdemote_f64x2_le(f64x2) -> f32x4 wasmtime_system_v { @@ -323,10 +323,10 @@ block0(v0: f64x2): } ; block0: -; vledb %v3, %v24, 0, 0 -; vesrlg %v5, %v3, 32 -; vgbm %v7, 0 -; vpkg %v24, %v7, %v5 +; vledb %v2, %v24, 0, 0 +; vesrlg %v4, %v2, 32 +; vgbm %v6, 0 +; vpkg %v24, %v6, %v4 ; br %r14 function %ceil_f32x4(f32x4) -> f32x4 { @@ -436,8 +436,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vgmf %v4, 1, 31 -; vsel %v24, %v24, %v25, %v4 +; vgmf %v3, 1, 31 +; vsel %v24, %v24, %v25, %v3 ; br %r14 function %fcopysign_f64x2(f64x2, f64x2) -> f64x2 { @@ -447,8 +447,8 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vgmg %v4, 1, 63 -; vsel %v24, %v24, %v25, %v4 +; vgmg %v3, 1, 63 +; vsel %v24, %v24, %v25, %v3 ; br %r14 function %fcvt_from_uint_i32x4_f32x4(i32x4) -> f32x4 { @@ -458,14 +458,14 @@ block0(v0: i32x4): } ; block0: -; vuplhf %v3, %v24 -; vcdlgb %v5, %v3, 0, 3 -; vledb %v7, %v5, 0, 4 -; vupllf %v17, %v24 -; vcdlgb %v19, %v17, 0, 3 -; vledb %v21, %v19, 0, 4 -; bras %r1, 20 ; data.u128 0x0001020308090a0b1011121318191a1b ; vl %v23, 0(%r1) -; vperm %v24, %v7, %v21, %v23 +; vuplhf %v2, %v24 +; vcdlgb %v4, %v2, 0, 3 +; vledb %v6, %v4, 0, 4 +; vupllf %v16, %v24 +; vcdlgb %v18, %v16, 0, 3 +; vledb %v20, %v18, 0, 4 +; bras %r1, 20 ; data.u128 0x0001020308090a0b1011121318191a1b ; vl %v22, 0(%r1) +; vperm %v24, %v6, %v20, %v22 ; br %r14 function %fcvt_from_sint_i32x4_f32x4(i32x4) -> f32x4 { @@ -475,14 +475,14 @@ block0(v0: i32x4): } ; block0: -; vuphf %v3, %v24 -; vcdgb %v5, %v3, 0, 3 -; vledb %v7, %v5, 0, 4 -; vuplf %v17, %v24 -; vcdgb %v19, %v17, 0, 3 -; vledb %v21, %v19, 0, 4 -; bras %r1, 20 ; data.u128 0x0001020308090a0b1011121318191a1b ; vl %v23, 0(%r1) -; vperm %v24, %v7, %v21, %v23 +; vuphf %v2, %v24 +; vcdgb %v4, %v2, 0, 3 +; vledb %v6, %v4, 0, 4 +; vuplf %v16, %v24 +; vcdgb %v18, %v16, 0, 3 +; vledb %v20, %v18, 0, 4 +; bras %r1, 20 ; data.u128 0x0001020308090a0b1011121318191a1b ; vl %v22, 0(%r1) +; vperm %v24, %v6, %v20, %v22 ; br %r14 function %fcvt_from_uint_i64x2_f64x2(i64x2) -> f64x2 { @@ -513,8 +513,8 @@ block0(v0: i32x4): } ; block0: -; vuphf %v3, %v24 -; vcdgb %v24, %v3, 0, 4 +; vuphf %v2, %v24 +; vcdgb %v24, %v2, 0, 4 ; br %r14 function %fcvt_low_from_sint_i32x4_f64x2_le(i32x4) -> f64x2 wasmtime_system_v { @@ -524,8 +524,8 @@ block0(v0: i32x4): } ; block0: -; vuplf %v3, %v24 -; vcdgb %v24, %v3, 0, 4 +; vuplf %v2, %v24 +; vcdgb %v24, %v2, 0, 4 ; br %r14 function %fcvt_to_uint_sat_f32x4_i32x4(f32x4) -> i32x4 { @@ -535,13 +535,13 @@ block0(v0: f32x4): } ; block0: -; vmrhf %v3, %v24, %v24 -; vldeb %v5, %v3 -; vclgdb %v7, %v5, 0, 5 -; vmrlf %v17, %v24, %v24 -; vldeb %v19, %v17 -; vclgdb %v21, %v19, 0, 5 -; vpklsg %v24, %v7, %v21 +; vmrhf %v2, %v24, %v24 +; vldeb %v4, %v2 +; vclgdb %v6, %v4, 0, 5 +; vmrlf %v16, %v24, %v24 +; vldeb %v18, %v16 +; vclgdb %v20, %v18, 0, 5 +; vpklsg %v24, %v6, %v20 ; br %r14 function %fcvt_to_sint_sat_f32x4_i32x4(f32x4) -> i32x4 { @@ -551,16 +551,16 @@ block0(v0: f32x4): } ; block0: -; vmrhf %v3, %v24, %v24 -; vldeb %v5, %v3 -; vcgdb %v7, %v5, 0, 5 -; vmrlf %v17, %v24, %v24 -; vldeb %v19, %v17 -; vcgdb %v21, %v19, 0, 5 -; vpksg %v23, %v7, %v21 +; vmrhf %v2, %v24, %v24 +; vldeb %v4, %v2 +; vcgdb %v6, %v4, 0, 5 +; vmrlf %v16, %v24, %v24 +; vldeb %v18, %v16 +; vcgdb %v20, %v18, 0, 5 +; vpksg %v22, %v6, %v20 ; vgbm %v25, 0 -; vfcesb %v27, %v24, %v24 -; vsel %v24, %v23, %v25, %v27 +; vfcesb %v26, %v24, %v24 +; vsel %v24, %v22, %v25, %v26 ; br %r14 function %fcvt_to_uint_sat_f64x2_i64x2(f64x2) -> i64x2 { @@ -580,9 +580,9 @@ block0(v0: f64x2): } ; block0: -; vcgdb %v3, %v24, 0, 5 -; vgbm %v5, 0 -; vfcedb %v7, %v24, %v24 -; vsel %v24, %v3, %v5, %v7 +; vcgdb %v2, %v24, 0, 5 +; vgbm %v4, 0 +; vfcedb %v6, %v24, %v24 +; vsel %v24, %v2, %v4, %v6 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/vec-icmp.clif b/cranelift/filetests/filetests/isa/s390x/vec-icmp.clif index 530629372d..b4f812532e 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-icmp.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-icmp.clif @@ -18,8 +18,8 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vceqg %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vceqg %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_sgt_i64x2(i64x2, i64x2) -> i64x2 { @@ -49,8 +49,8 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchg %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vchg %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_sle_i64x2(i64x2, i64x2) -> i64x2 { @@ -60,8 +60,8 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchg %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vchg %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_ugt_i64x2(i64x2, i64x2) -> i64x2 { @@ -91,8 +91,8 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchlg %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vchlg %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_ule_i64x2(i64x2, i64x2) -> i64x2 { @@ -102,8 +102,8 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchlg %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vchlg %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_eq_i32x4(i32x4, i32x4) -> i32x4 { @@ -123,8 +123,8 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vceqf %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vceqf %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_sgt_i32x4(i32x4, i32x4) -> i32x4 { @@ -154,8 +154,8 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vchf %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vchf %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_sle_i32x4(i32x4, i32x4) -> i32x4 { @@ -165,8 +165,8 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vchf %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vchf %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_ugt_i32x4(i32x4, i32x4) -> i32x4 { @@ -196,8 +196,8 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vchlf %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vchlf %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_ule_i32x4(i32x4, i32x4) -> i32x4 { @@ -207,8 +207,8 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vchlf %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vchlf %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_eq_i16x8(i16x8, i16x8) -> i16x8 { @@ -228,8 +228,8 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vceqh %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vceqh %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_sgt_i16x8(i16x8, i16x8) -> i16x8 { @@ -259,8 +259,8 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vchh %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vchh %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_sle_i16x8(i16x8, i16x8) -> i16x8 { @@ -270,8 +270,8 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vchh %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vchh %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_ugt_i16x8(i16x8, i16x8) -> i16x8 { @@ -301,8 +301,8 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vchlh %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vchlh %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_ule_i16x8(i16x8, i16x8) -> i16x8 { @@ -312,8 +312,8 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vchlh %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vchlh %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_eq_i8x16(i8x16, i8x16) -> i8x16 { @@ -333,8 +333,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vceqb %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vceqb %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_sgt_i8x16(i8x16, i8x16) -> i8x16 { @@ -364,8 +364,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vchb %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vchb %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_sle_i8x16(i8x16, i8x16) -> i8x16 { @@ -375,8 +375,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vchb %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vchb %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_ugt_i8x16(i8x16, i8x16) -> i8x16 { @@ -406,8 +406,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vchlb %v4, %v25, %v24 -; vno %v24, %v4, %v4 +; vchlb %v3, %v25, %v24 +; vno %v24, %v3, %v3 ; br %r14 function %icmp_ule_i8x16(i8x16, i8x16) -> i8x16 { @@ -417,7 +417,7 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vchlb %v4, %v24, %v25 -; vno %v24, %v4, %v4 +; vchlb %v3, %v24, %v25 +; vno %v24, %v3, %v3 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane.clif b/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane.clif index efe7fb0566..3c60ac3325 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-lane-le-lane.clif @@ -117,8 +117,8 @@ block0(v0: i64x2, v1: i64): } ; block0: -; lrvg %r2, 0(%r2) -; vlvgg %v24, %r2, 1 +; lrvg %r5, 0(%r2) +; vlvgg %v24, %r5, 1 ; br %r14 function %insertlane_i64x2_mem_little_1(i64x2, i64) -> i64x2 wasmtime_system_v { @@ -129,8 +129,8 @@ block0(v0: i64x2, v1: i64): } ; block0: -; lrvg %r2, 0(%r2) -; vlvgg %v24, %r2, 0 +; lrvg %r5, 0(%r2) +; vlvgg %v24, %r5, 0 ; br %r14 function %insertlane_i32x4_0(i32x4, i32) -> i32x4 wasmtime_system_v { @@ -183,8 +183,8 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vgbm %v4, 15 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 15 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i32x4_lane_0_3(i32x4, i32x4) -> i32x4 wasmtime_system_v { @@ -195,9 +195,9 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vrepf %v4, %v25, 3 -; vgbm %v6, 61440 -; vsel %v24, %v4, %v24, %v6 +; vrepf %v3, %v25, 3 +; vgbm %v5, 61440 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i32x4_lane_3_0(i32x4, i32x4) -> i32x4 wasmtime_system_v { @@ -208,9 +208,9 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vrepf %v4, %v25, 0 -; vgbm %v6, 15 -; vsel %v24, %v4, %v24, %v6 +; vrepf %v3, %v25, 0 +; vgbm %v5, 15 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i32x4_lane_3_3(i32x4, i32x4) -> i32x4 wasmtime_system_v { @@ -221,8 +221,8 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vgbm %v4, 61440 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 61440 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i32x4_mem_0(i32x4, i64) -> i32x4 wasmtime_system_v { @@ -255,8 +255,8 @@ block0(v0: i32x4, v1: i64): } ; block0: -; lrv %r2, 0(%r2) -; vlvgf %v24, %r2, 3 +; lrv %r5, 0(%r2) +; vlvgf %v24, %r5, 3 ; br %r14 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 wasmtime_system_v { @@ -267,8 +267,8 @@ block0(v0: i32x4, v1: i64): } ; block0: -; lrv %r2, 0(%r2) -; vlvgf %v24, %r2, 0 +; lrv %r5, 0(%r2) +; vlvgf %v24, %r5, 0 ; br %r14 function %insertlane_i16x8_0(i16x8, i16) -> i16x8 wasmtime_system_v { @@ -321,8 +321,8 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vgbm %v4, 3 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 3 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i16x8_lane_0_7(i16x8, i16x8) -> i16x8 wasmtime_system_v { @@ -333,9 +333,9 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vreph %v4, %v25, 7 -; vgbm %v6, 49152 -; vsel %v24, %v4, %v24, %v6 +; vreph %v3, %v25, 7 +; vgbm %v5, 49152 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i16x8_lane_7_0(i16x8, i16x8) -> i16x8 wasmtime_system_v { @@ -346,9 +346,9 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vreph %v4, %v25, 0 -; vgbm %v6, 3 -; vsel %v24, %v4, %v24, %v6 +; vreph %v3, %v25, 0 +; vgbm %v5, 3 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i16x8_lane_7_7(i16x8, i16x8) -> i16x8 wasmtime_system_v { @@ -359,8 +359,8 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vgbm %v4, 49152 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 49152 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i16x8_mem_0(i16x8, i64) -> i16x8 wasmtime_system_v { @@ -393,8 +393,8 @@ block0(v0: i16x8, v1: i64): } ; block0: -; lrvh %r2, 0(%r2) -; vlvgh %v24, %r2, 7 +; lrvh %r5, 0(%r2) +; vlvgh %v24, %r5, 7 ; br %r14 function %insertlane_i16x8_mem_little_7(i16x8, i64) -> i16x8 wasmtime_system_v { @@ -405,8 +405,8 @@ block0(v0: i16x8, v1: i64): } ; block0: -; lrvh %r2, 0(%r2) -; vlvgh %v24, %r2, 0 +; lrvh %r5, 0(%r2) +; vlvgh %v24, %r5, 0 ; br %r14 function %insertlane_i8x16_0(i8x16, i8) -> i8x16 wasmtime_system_v { @@ -459,8 +459,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vgbm %v4, 1 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 1 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i8x16_lane_0_15(i8x16, i8x16) -> i8x16 wasmtime_system_v { @@ -471,9 +471,9 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vrepb %v4, %v25, 15 -; vgbm %v6, 32768 -; vsel %v24, %v4, %v24, %v6 +; vrepb %v3, %v25, 15 +; vgbm %v5, 32768 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i8x16_lane_15_0(i8x16, i8x16) -> i8x16 wasmtime_system_v { @@ -484,9 +484,9 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vrepb %v4, %v25, 0 -; vgbm %v6, 1 -; vsel %v24, %v4, %v24, %v6 +; vrepb %v3, %v25, 0 +; vgbm %v5, 1 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i8x16_lane_15_15(i8x16, i8x16) -> i8x16 wasmtime_system_v { @@ -497,8 +497,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vgbm %v4, 32768 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 32768 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i8x16_mem_0(i8x16, i64) -> i8x16 wasmtime_system_v { @@ -639,8 +639,8 @@ block0(v0: f64x2, v1: i64): } ; block0: -; lrvg %r2, 0(%r2) -; vlvgg %v24, %r2, 1 +; lrvg %r5, 0(%r2) +; vlvgg %v24, %r5, 1 ; br %r14 function %insertlane_f64x2_mem_little_1(f64x2, i64) -> f64x2 wasmtime_system_v { @@ -651,8 +651,8 @@ block0(v0: f64x2, v1: i64): } ; block0: -; lrvg %r2, 0(%r2) -; vlvgg %v24, %r2, 0 +; lrvg %r5, 0(%r2) +; vlvgg %v24, %r5, 0 ; br %r14 function %insertlane_f32x4_0(f32x4, f32) -> f32x4 wasmtime_system_v { @@ -662,9 +662,9 @@ block0(v0: f32x4, v1: f32): } ; block0: -; vrepf %v4, %v0, 0 -; vgbm %v6, 15 -; vsel %v24, %v4, %v24, %v6 +; vrepf %v3, %v0, 0 +; vgbm %v5, 15 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_f32x4_3(f32x4, f32) -> f32x4 wasmtime_system_v { @@ -674,8 +674,8 @@ block0(v0: f32x4, v1: f32): } ; block0: -; vgbm %v4, 61440 -; vsel %v24, %v0, %v24, %v4 +; vgbm %v3, 61440 +; vsel %v24, %v0, %v24, %v3 ; br %r14 function %insertlane_f32x4_lane_0_0(f32x4, f32x4) -> f32x4 wasmtime_system_v { @@ -686,8 +686,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vgbm %v4, 15 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 15 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_f32x4_lane_0_3(f32x4, f32x4) -> f32x4 wasmtime_system_v { @@ -698,9 +698,9 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vrepf %v4, %v25, 3 -; vgbm %v6, 61440 -; vsel %v24, %v4, %v24, %v6 +; vrepf %v3, %v25, 3 +; vgbm %v5, 61440 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_f32x4_lane_3_0(f32x4, f32x4) -> f32x4 wasmtime_system_v { @@ -711,9 +711,9 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vrepf %v4, %v25, 0 -; vgbm %v6, 15 -; vsel %v24, %v4, %v24, %v6 +; vrepf %v3, %v25, 0 +; vgbm %v5, 15 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_f32x4_lane_3_3(f32x4, f32x4) -> f32x4 wasmtime_system_v { @@ -724,8 +724,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vgbm %v4, 61440 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 61440 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_f32x4_mem_0(f32x4, i64) -> f32x4 wasmtime_system_v { @@ -758,8 +758,8 @@ block0(v0: f32x4, v1: i64): } ; block0: -; lrv %r2, 0(%r2) -; vlvgf %v24, %r2, 3 +; lrv %r5, 0(%r2) +; vlvgf %v24, %r5, 3 ; br %r14 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 wasmtime_system_v { @@ -770,8 +770,8 @@ block0(v0: i32x4, v1: i64): } ; block0: -; lrv %r2, 0(%r2) -; vlvgf %v24, %r2, 0 +; lrv %r5, 0(%r2) +; vlvgf %v24, %r5, 0 ; br %r14 function %extractlane_i64x2_0(i64x2) -> i64 wasmtime_system_v { @@ -1175,8 +1175,8 @@ block0(v0: i64): } ; block0: -; ldgr %f3, %r2 -; vrepg %v24, %v3, 0 +; ldgr %f2, %r2 +; vrepg %v24, %v2, 0 ; br %r14 function %splat_i64x2_imm() -> i64x2 wasmtime_system_v { @@ -1231,9 +1231,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vrepg %v24, %v5, 0 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vrepg %v24, %v4, 0 ; br %r14 function %splat_i32x4(i32) -> i32x4 wasmtime_system_v { @@ -1243,8 +1243,8 @@ block0(v0: i32): } ; block0: -; vlvgf %v3, %r2, 0 -; vrepf %v24, %v3, 0 +; vlvgf %v2, %r2, 0 +; vrepf %v24, %v2, 0 ; br %r14 function %splat_i32x4_imm() -> i32x4 wasmtime_system_v { @@ -1299,9 +1299,9 @@ block0(v0: i64): } ; block0: -; lrv %r5, 0(%r2) -; vlvgf %v5, %r5, 0 -; vrepf %v24, %v5, 0 +; lrv %r4, 0(%r2) +; vlvgf %v4, %r4, 0 +; vrepf %v24, %v4, 0 ; br %r14 function %splat_i16x8(i16) -> i16x8 wasmtime_system_v { @@ -1311,8 +1311,8 @@ block0(v0: i16): } ; block0: -; vlvgh %v3, %r2, 0 -; vreph %v24, %v3, 0 +; vlvgh %v2, %r2, 0 +; vreph %v24, %v2, 0 ; br %r14 function %splat_i16x8_imm() -> i16x8 wasmtime_system_v { @@ -1367,9 +1367,9 @@ block0(v0: i64): } ; block0: -; lrvh %r5, 0(%r2) -; vlvgh %v5, %r5, 0 -; vreph %v24, %v5, 0 +; lrvh %r4, 0(%r2) +; vlvgh %v4, %r4, 0 +; vreph %v24, %v4, 0 ; br %r14 function %splat_i8x16(i8) -> i8x16 wasmtime_system_v { @@ -1379,8 +1379,8 @@ block0(v0: i8): } ; block0: -; vlvgb %v3, %r2, 0 -; vrepb %v24, %v3, 0 +; vlvgb %v2, %r2, 0 +; vrepb %v24, %v2, 0 ; br %r14 function %splat_i8x16_imm() -> i8x16 wasmtime_system_v { @@ -1489,9 +1489,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vrepg %v24, %v5, 0 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vrepg %v24, %v4, 0 ; br %r14 function %splat_f32x4(f32) -> f32x4 wasmtime_system_v { @@ -1545,9 +1545,9 @@ block0(v0: i64): } ; block0: -; lrv %r5, 0(%r2) -; vlvgf %v5, %r5, 0 -; vrepf %v24, %v5, 0 +; lrv %r4, 0(%r2) +; vlvgf %v4, %r4, 0 +; vrepf %v24, %v4, 0 ; br %r14 function %scalar_to_vector_i64x2(i64) -> i64x2 wasmtime_system_v { @@ -1581,8 +1581,8 @@ block0(v0: i64x2): } ; block0: -; vgbm %v3, 0 -; vpdi %v24, %v3, %v24, 1 +; vgbm %v2, 0 +; vpdi %v24, %v2, %v24, 1 ; br %r14 function %scalar_to_vector_i64x2_lane_1(i64x2) -> i64x2 wasmtime_system_v { @@ -1593,8 +1593,8 @@ block0(v0: i64x2): } ; block0: -; vgbm %v3, 0 -; vpdi %v24, %v3, %v24, 0 +; vgbm %v2, 0 +; vpdi %v24, %v2, %v24, 0 ; br %r14 function %scalar_to_vector_i64x2_mem(i64) -> i64x2 wasmtime_system_v { @@ -1618,8 +1618,8 @@ block0(v0: i64): ; block0: ; vgbm %v24, 0 -; lrvg %r3, 0(%r2) -; vlvgg %v24, %r3, 1 +; lrvg %r2, 0(%r2) +; vlvgg %v24, %r2, 1 ; br %r14 function %scalar_to_vector_i32x4(i32) -> i32x4 wasmtime_system_v { @@ -1653,8 +1653,8 @@ block0(v0: i32x4): } ; block0: -; vgbm %v3, 15 -; vn %v24, %v24, %v3 +; vgbm %v2, 15 +; vn %v24, %v24, %v2 ; br %r14 function %scalar_to_vector_i32x4_lane_3(i32x4) -> i32x4 wasmtime_system_v { @@ -1665,9 +1665,9 @@ block0(v0: i32x4): } ; block0: -; vrepf %v3, %v24, 0 -; vgbm %v5, 15 -; vn %v24, %v3, %v5 +; vrepf %v2, %v24, 0 +; vgbm %v4, 15 +; vn %v24, %v2, %v4 ; br %r14 function %scalar_to_vector_i32x4_mem(i64) -> i32x4 wasmtime_system_v { @@ -1691,8 +1691,8 @@ block0(v0: i64): ; block0: ; vgbm %v24, 0 -; lrv %r3, 0(%r2) -; vlvgf %v24, %r3, 3 +; lrv %r2, 0(%r2) +; vlvgf %v24, %r2, 3 ; br %r14 function %scalar_to_vector_i16x8(i16) -> i16x8 wasmtime_system_v { @@ -1726,8 +1726,8 @@ block0(v0: i16x8): } ; block0: -; vgbm %v3, 3 -; vn %v24, %v24, %v3 +; vgbm %v2, 3 +; vn %v24, %v24, %v2 ; br %r14 function %scalar_to_vector_i16x8_lane_7(i16x8) -> i16x8 wasmtime_system_v { @@ -1738,9 +1738,9 @@ block0(v0: i16x8): } ; block0: -; vreph %v3, %v24, 0 -; vgbm %v5, 3 -; vn %v24, %v3, %v5 +; vreph %v2, %v24, 0 +; vgbm %v4, 3 +; vn %v24, %v2, %v4 ; br %r14 function %scalar_to_vector_i16x8_mem(i64) -> i16x8 wasmtime_system_v { @@ -1764,8 +1764,8 @@ block0(v0: i64): ; block0: ; vgbm %v24, 0 -; lrvh %r3, 0(%r2) -; vlvgh %v24, %r3, 7 +; lrvh %r2, 0(%r2) +; vlvgh %v24, %r2, 7 ; br %r14 function %scalar_to_vector_i8x16(i8) -> i8x16 wasmtime_system_v { @@ -1799,8 +1799,8 @@ block0(v0: i8x16): } ; block0: -; vgbm %v3, 1 -; vn %v24, %v24, %v3 +; vgbm %v2, 1 +; vn %v24, %v24, %v2 ; br %r14 function %scalar_to_vector_i8x16_lane_15(i8x16) -> i8x16 wasmtime_system_v { @@ -1811,9 +1811,9 @@ block0(v0: i8x16): } ; block0: -; vrepb %v3, %v24, 0 -; vgbm %v5, 1 -; vn %v24, %v3, %v5 +; vrepb %v2, %v24, 0 +; vgbm %v4, 1 +; vn %v24, %v2, %v4 ; br %r14 function %scalar_to_vector_i8x16_mem(i64) -> i8x16 wasmtime_system_v { @@ -1847,8 +1847,8 @@ block0(v0: f64): } ; block0: -; vgbm %v3, 0 -; vpdi %v24, %v3, %v0, 0 +; vgbm %v2, 0 +; vpdi %v24, %v2, %v0, 0 ; br %r14 function %scalar_to_vector_f64x2_lane_0(f64x2) -> f64x2 wasmtime_system_v { @@ -1859,8 +1859,8 @@ block0(v0: f64x2): } ; block0: -; vgbm %v3, 0 -; vpdi %v24, %v3, %v24, 1 +; vgbm %v2, 0 +; vpdi %v24, %v2, %v24, 1 ; br %r14 function %scalar_to_vector_f64x2_lane_1(f64x2) -> f64x2 wasmtime_system_v { @@ -1871,8 +1871,8 @@ block0(v0: f64x2): } ; block0: -; vgbm %v3, 0 -; vpdi %v24, %v3, %v24, 0 +; vgbm %v2, 0 +; vpdi %v24, %v2, %v24, 0 ; br %r14 function %scalar_to_vector_f64x2_mem(i64) -> f64x2 wasmtime_system_v { @@ -1896,8 +1896,8 @@ block0(v0: i64): ; block0: ; vgbm %v24, 0 -; lrvg %r3, 0(%r2) -; vlvgg %v24, %r3, 1 +; lrvg %r2, 0(%r2) +; vlvgg %v24, %r2, 1 ; br %r14 function %scalar_to_vector_f32x4(f32) -> f32x4 wasmtime_system_v { @@ -1907,9 +1907,9 @@ block0(v0: f32): } ; block0: -; vrepf %v3, %v0, 0 -; vgbm %v5, 15 -; vn %v24, %v3, %v5 +; vrepf %v2, %v0, 0 +; vgbm %v4, 15 +; vn %v24, %v2, %v4 ; br %r14 function %scalar_to_vector_f32x4_lane_0(f32x4) -> f32x4 wasmtime_system_v { @@ -1920,8 +1920,8 @@ block0(v0: f32x4): } ; block0: -; vgbm %v3, 15 -; vn %v24, %v24, %v3 +; vgbm %v2, 15 +; vn %v24, %v24, %v2 ; br %r14 function %scalar_to_vector_f32x4_lane_3(f32x4) -> f32x4 wasmtime_system_v { @@ -1932,9 +1932,9 @@ block0(v0: f32x4): } ; block0: -; vrepf %v3, %v24, 0 -; vgbm %v5, 15 -; vn %v24, %v3, %v5 +; vrepf %v2, %v24, 0 +; vgbm %v4, 15 +; vn %v24, %v2, %v4 ; br %r14 function %scalar_to_vector_f32x4_mem(i64) -> f32x4 wasmtime_system_v { @@ -1958,7 +1958,7 @@ block0(v0: i64): ; block0: ; vgbm %v24, 0 -; lrv %r3, 0(%r2) -; vlvgf %v24, %r3, 3 +; lrv %r2, 0(%r2) +; vlvgf %v24, %r2, 3 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/vec-lane.clif b/cranelift/filetests/filetests/isa/s390x/vec-lane.clif index 5ac4b63e69..3f0a6244f1 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-lane.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-lane.clif @@ -117,8 +117,8 @@ block0(v0: i64x2, v1: i64): } ; block0: -; lrvg %r2, 0(%r2) -; vlvgg %v24, %r2, 0 +; lrvg %r5, 0(%r2) +; vlvgg %v24, %r5, 0 ; br %r14 function %insertlane_i64x2_mem_little_1(i64x2, i64) -> i64x2 { @@ -129,8 +129,8 @@ block0(v0: i64x2, v1: i64): } ; block0: -; lrvg %r2, 0(%r2) -; vlvgg %v24, %r2, 1 +; lrvg %r5, 0(%r2) +; vlvgg %v24, %r5, 1 ; br %r14 function %insertlane_i32x4_0(i32x4, i32) -> i32x4 { @@ -183,8 +183,8 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vgbm %v4, 61440 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 61440 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i32x4_lane_0_3(i32x4, i32x4) -> i32x4 { @@ -195,9 +195,9 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vrepf %v4, %v25, 0 -; vgbm %v6, 15 -; vsel %v24, %v4, %v24, %v6 +; vrepf %v3, %v25, 0 +; vgbm %v5, 15 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i32x4_lane_3_0(i32x4, i32x4) -> i32x4 { @@ -208,9 +208,9 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vrepf %v4, %v25, 3 -; vgbm %v6, 61440 -; vsel %v24, %v4, %v24, %v6 +; vrepf %v3, %v25, 3 +; vgbm %v5, 61440 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i32x4_lane_3_3(i32x4, i32x4) -> i32x4 { @@ -221,8 +221,8 @@ block0(v0: i32x4, v1: i32x4): } ; block0: -; vgbm %v4, 15 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 15 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i32x4_mem_0(i32x4, i64) -> i32x4 { @@ -255,8 +255,8 @@ block0(v0: i32x4, v1: i64): } ; block0: -; lrv %r2, 0(%r2) -; vlvgf %v24, %r2, 0 +; lrv %r5, 0(%r2) +; vlvgf %v24, %r5, 0 ; br %r14 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 { @@ -267,8 +267,8 @@ block0(v0: i32x4, v1: i64): } ; block0: -; lrv %r2, 0(%r2) -; vlvgf %v24, %r2, 3 +; lrv %r5, 0(%r2) +; vlvgf %v24, %r5, 3 ; br %r14 function %insertlane_i16x8_0(i16x8, i16) -> i16x8 { @@ -321,8 +321,8 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vgbm %v4, 49152 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 49152 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i16x8_lane_0_7(i16x8, i16x8) -> i16x8 { @@ -333,9 +333,9 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vreph %v4, %v25, 0 -; vgbm %v6, 3 -; vsel %v24, %v4, %v24, %v6 +; vreph %v3, %v25, 0 +; vgbm %v5, 3 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i16x8_lane_7_0(i16x8, i16x8) -> i16x8 { @@ -346,9 +346,9 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vreph %v4, %v25, 7 -; vgbm %v6, 49152 -; vsel %v24, %v4, %v24, %v6 +; vreph %v3, %v25, 7 +; vgbm %v5, 49152 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i16x8_lane_7_7(i16x8, i16x8) -> i16x8 { @@ -359,8 +359,8 @@ block0(v0: i16x8, v1: i16x8): } ; block0: -; vgbm %v4, 3 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 3 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i16x8_mem_0(i16x8, i64) -> i16x8 { @@ -393,8 +393,8 @@ block0(v0: i16x8, v1: i64): } ; block0: -; lrvh %r2, 0(%r2) -; vlvgh %v24, %r2, 0 +; lrvh %r5, 0(%r2) +; vlvgh %v24, %r5, 0 ; br %r14 function %insertlane_i16x8_mem_little_7(i16x8, i64) -> i16x8 { @@ -405,8 +405,8 @@ block0(v0: i16x8, v1: i64): } ; block0: -; lrvh %r2, 0(%r2) -; vlvgh %v24, %r2, 7 +; lrvh %r5, 0(%r2) +; vlvgh %v24, %r5, 7 ; br %r14 function %insertlane_i8x16_0(i8x16, i8) -> i8x16 { @@ -459,8 +459,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vgbm %v4, 32768 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 32768 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i8x16_lane_0_15(i8x16, i8x16) -> i8x16 { @@ -471,9 +471,9 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vrepb %v4, %v25, 0 -; vgbm %v6, 1 -; vsel %v24, %v4, %v24, %v6 +; vrepb %v3, %v25, 0 +; vgbm %v5, 1 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i8x16_lane_15_0(i8x16, i8x16) -> i8x16 { @@ -484,9 +484,9 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vrepb %v4, %v25, 15 -; vgbm %v6, 32768 -; vsel %v24, %v4, %v24, %v6 +; vrepb %v3, %v25, 15 +; vgbm %v5, 32768 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_i8x16_lane_15_15(i8x16, i8x16) -> i8x16 { @@ -497,8 +497,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vgbm %v4, 1 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 1 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_i8x16_mem_0(i8x16, i64) -> i8x16 { @@ -639,8 +639,8 @@ block0(v0: f64x2, v1: i64): } ; block0: -; lrvg %r2, 0(%r2) -; vlvgg %v24, %r2, 0 +; lrvg %r5, 0(%r2) +; vlvgg %v24, %r5, 0 ; br %r14 function %insertlane_f64x2_mem_little_1(f64x2, i64) -> f64x2 { @@ -651,8 +651,8 @@ block0(v0: f64x2, v1: i64): } ; block0: -; lrvg %r2, 0(%r2) -; vlvgg %v24, %r2, 1 +; lrvg %r5, 0(%r2) +; vlvgg %v24, %r5, 1 ; br %r14 function %insertlane_f32x4_0(f32x4, f32) -> f32x4 { @@ -662,8 +662,8 @@ block0(v0: f32x4, v1: f32): } ; block0: -; vgbm %v4, 61440 -; vsel %v24, %v0, %v24, %v4 +; vgbm %v3, 61440 +; vsel %v24, %v0, %v24, %v3 ; br %r14 function %insertlane_f32x4_3(f32x4, f32) -> f32x4 { @@ -673,9 +673,9 @@ block0(v0: f32x4, v1: f32): } ; block0: -; vrepf %v4, %v0, 0 -; vgbm %v6, 15 -; vsel %v24, %v4, %v24, %v6 +; vrepf %v3, %v0, 0 +; vgbm %v5, 15 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_f32x4_lane_0_0(f32x4, f32x4) -> f32x4 { @@ -686,8 +686,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vgbm %v4, 61440 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 61440 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_f32x4_lane_0_3(f32x4, f32x4) -> f32x4 { @@ -698,9 +698,9 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vrepf %v4, %v25, 0 -; vgbm %v6, 15 -; vsel %v24, %v4, %v24, %v6 +; vrepf %v3, %v25, 0 +; vgbm %v5, 15 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_f32x4_lane_3_0(f32x4, f32x4) -> f32x4 { @@ -711,9 +711,9 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vrepf %v4, %v25, 3 -; vgbm %v6, 61440 -; vsel %v24, %v4, %v24, %v6 +; vrepf %v3, %v25, 3 +; vgbm %v5, 61440 +; vsel %v24, %v3, %v24, %v5 ; br %r14 function %insertlane_f32x4_lane_3_3(f32x4, f32x4) -> f32x4 { @@ -724,8 +724,8 @@ block0(v0: f32x4, v1: f32x4): } ; block0: -; vgbm %v4, 15 -; vsel %v24, %v25, %v24, %v4 +; vgbm %v3, 15 +; vsel %v24, %v25, %v24, %v3 ; br %r14 function %insertlane_f32x4_mem_0(f32x4, i64) -> f32x4 { @@ -758,8 +758,8 @@ block0(v0: f32x4, v1: i64): } ; block0: -; lrv %r2, 0(%r2) -; vlvgf %v24, %r2, 0 +; lrv %r5, 0(%r2) +; vlvgf %v24, %r5, 0 ; br %r14 function %insertlane_i32x4_mem_little_3(i32x4, i64) -> i32x4 { @@ -770,8 +770,8 @@ block0(v0: i32x4, v1: i64): } ; block0: -; lrv %r2, 0(%r2) -; vlvgf %v24, %r2, 3 +; lrv %r5, 0(%r2) +; vlvgf %v24, %r5, 3 ; br %r14 function %extractlane_i64x2_0(i64x2) -> i64 { @@ -1175,8 +1175,8 @@ block0(v0: i64): } ; block0: -; ldgr %f3, %r2 -; vrepg %v24, %v3, 0 +; ldgr %f2, %r2 +; vrepg %v24, %v2, 0 ; br %r14 function %splat_i64x2_imm() -> i64x2 { @@ -1231,9 +1231,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vrepg %v24, %v5, 0 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vrepg %v24, %v4, 0 ; br %r14 function %splat_i32x4(i32) -> i32x4 { @@ -1243,8 +1243,8 @@ block0(v0: i32): } ; block0: -; vlvgf %v3, %r2, 0 -; vrepf %v24, %v3, 0 +; vlvgf %v2, %r2, 0 +; vrepf %v24, %v2, 0 ; br %r14 function %splat_i32x4_imm() -> i32x4 { @@ -1299,9 +1299,9 @@ block0(v0: i64): } ; block0: -; lrv %r5, 0(%r2) -; vlvgf %v5, %r5, 0 -; vrepf %v24, %v5, 0 +; lrv %r4, 0(%r2) +; vlvgf %v4, %r4, 0 +; vrepf %v24, %v4, 0 ; br %r14 function %splat_i16x8(i16) -> i16x8 { @@ -1311,8 +1311,8 @@ block0(v0: i16): } ; block0: -; vlvgh %v3, %r2, 0 -; vreph %v24, %v3, 0 +; vlvgh %v2, %r2, 0 +; vreph %v24, %v2, 0 ; br %r14 function %splat_i16x8_imm() -> i16x8 { @@ -1367,9 +1367,9 @@ block0(v0: i64): } ; block0: -; lrvh %r5, 0(%r2) -; vlvgh %v5, %r5, 0 -; vreph %v24, %v5, 0 +; lrvh %r4, 0(%r2) +; vlvgh %v4, %r4, 0 +; vreph %v24, %v4, 0 ; br %r14 function %splat_i8x16(i8) -> i8x16 { @@ -1379,8 +1379,8 @@ block0(v0: i8): } ; block0: -; vlvgb %v3, %r2, 0 -; vrepb %v24, %v3, 0 +; vlvgb %v2, %r2, 0 +; vrepb %v24, %v2, 0 ; br %r14 function %splat_i8x16_imm() -> i8x16 { @@ -1489,9 +1489,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vrepg %v24, %v5, 0 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vrepg %v24, %v4, 0 ; br %r14 function %splat_f32x4(f32) -> f32x4 { @@ -1545,9 +1545,9 @@ block0(v0: i64): } ; block0: -; lrv %r5, 0(%r2) -; vlvgf %v5, %r5, 0 -; vrepf %v24, %v5, 0 +; lrv %r4, 0(%r2) +; vlvgf %v4, %r4, 0 +; vrepf %v24, %v4, 0 ; br %r14 function %scalar_to_vector_i64x2(i64) -> i64x2 { @@ -1581,8 +1581,8 @@ block0(v0: i64x2): } ; block0: -; vgbm %v3, 0 -; vpdi %v24, %v24, %v3, 0 +; vgbm %v2, 0 +; vpdi %v24, %v24, %v2, 0 ; br %r14 function %scalar_to_vector_i64x2_lane_1(i64x2) -> i64x2 { @@ -1593,8 +1593,8 @@ block0(v0: i64x2): } ; block0: -; vgbm %v3, 0 -; vpdi %v24, %v24, %v3, 4 +; vgbm %v2, 0 +; vpdi %v24, %v24, %v2, 4 ; br %r14 function %scalar_to_vector_i64x2_mem(i64) -> i64x2 { @@ -1618,8 +1618,8 @@ block0(v0: i64): ; block0: ; vgbm %v24, 0 -; lrvg %r3, 0(%r2) -; vlvgg %v24, %r3, 0 +; lrvg %r2, 0(%r2) +; vlvgg %v24, %r2, 0 ; br %r14 function %scalar_to_vector_i32x4(i32) -> i32x4 { @@ -1653,8 +1653,8 @@ block0(v0: i32x4): } ; block0: -; vgbm %v3, 61440 -; vn %v24, %v24, %v3 +; vgbm %v2, 61440 +; vn %v24, %v24, %v2 ; br %r14 function %scalar_to_vector_i32x4_lane_3(i32x4) -> i32x4 { @@ -1665,9 +1665,9 @@ block0(v0: i32x4): } ; block0: -; vrepf %v3, %v24, 3 -; vgbm %v5, 61440 -; vn %v24, %v3, %v5 +; vrepf %v2, %v24, 3 +; vgbm %v4, 61440 +; vn %v24, %v2, %v4 ; br %r14 function %scalar_to_vector_i32x4_mem(i64) -> i32x4 { @@ -1691,8 +1691,8 @@ block0(v0: i64): ; block0: ; vgbm %v24, 0 -; lrv %r3, 0(%r2) -; vlvgf %v24, %r3, 0 +; lrv %r2, 0(%r2) +; vlvgf %v24, %r2, 0 ; br %r14 function %scalar_to_vector_i16x8(i16) -> i16x8 { @@ -1726,8 +1726,8 @@ block0(v0: i16x8): } ; block0: -; vgbm %v3, 49152 -; vn %v24, %v24, %v3 +; vgbm %v2, 49152 +; vn %v24, %v24, %v2 ; br %r14 function %scalar_to_vector_i16x8_lane_7(i16x8) -> i16x8 { @@ -1738,9 +1738,9 @@ block0(v0: i16x8): } ; block0: -; vreph %v3, %v24, 7 -; vgbm %v5, 49152 -; vn %v24, %v3, %v5 +; vreph %v2, %v24, 7 +; vgbm %v4, 49152 +; vn %v24, %v2, %v4 ; br %r14 function %scalar_to_vector_i16x8_mem(i64) -> i16x8 { @@ -1764,8 +1764,8 @@ block0(v0: i64): ; block0: ; vgbm %v24, 0 -; lrvh %r3, 0(%r2) -; vlvgh %v24, %r3, 0 +; lrvh %r2, 0(%r2) +; vlvgh %v24, %r2, 0 ; br %r14 function %scalar_to_vector_i8x16(i8) -> i8x16 { @@ -1799,8 +1799,8 @@ block0(v0: i8x16): } ; block0: -; vgbm %v3, 32768 -; vn %v24, %v24, %v3 +; vgbm %v2, 32768 +; vn %v24, %v24, %v2 ; br %r14 function %scalar_to_vector_i8x16_lane_15(i8x16) -> i8x16 { @@ -1811,9 +1811,9 @@ block0(v0: i8x16): } ; block0: -; vrepb %v3, %v24, 15 -; vgbm %v5, 32768 -; vn %v24, %v3, %v5 +; vrepb %v2, %v24, 15 +; vgbm %v4, 32768 +; vn %v24, %v2, %v4 ; br %r14 function %scalar_to_vector_i8x16_mem(i64) -> i8x16 { @@ -1847,8 +1847,8 @@ block0(v0: f64): } ; block0: -; vgbm %v3, 0 -; vpdi %v24, %v0, %v3, 0 +; vgbm %v2, 0 +; vpdi %v24, %v0, %v2, 0 ; br %r14 function %scalar_to_vector_f64x2_lane_0(f64x2) -> f64x2 { @@ -1859,8 +1859,8 @@ block0(v0: f64x2): } ; block0: -; vgbm %v3, 0 -; vpdi %v24, %v24, %v3, 0 +; vgbm %v2, 0 +; vpdi %v24, %v24, %v2, 0 ; br %r14 function %scalar_to_vector_f64x2_lane_1(f64x2) -> f64x2 { @@ -1871,8 +1871,8 @@ block0(v0: f64x2): } ; block0: -; vgbm %v3, 0 -; vpdi %v24, %v24, %v3, 4 +; vgbm %v2, 0 +; vpdi %v24, %v24, %v2, 4 ; br %r14 function %scalar_to_vector_f64x2_mem(i64) -> f64x2 { @@ -1896,8 +1896,8 @@ block0(v0: i64): ; block0: ; vgbm %v24, 0 -; lrvg %r3, 0(%r2) -; vlvgg %v24, %r3, 0 +; lrvg %r2, 0(%r2) +; vlvgg %v24, %r2, 0 ; br %r14 function %scalar_to_vector_f32x4(f32) -> f32x4 { @@ -1907,8 +1907,8 @@ block0(v0: f32): } ; block0: -; vgbm %v3, 61440 -; vn %v24, %v0, %v3 +; vgbm %v2, 61440 +; vn %v24, %v0, %v2 ; br %r14 function %scalar_to_vector_f32x4_lane_0(f32x4) -> f32x4 { @@ -1919,8 +1919,8 @@ block0(v0: f32x4): } ; block0: -; vgbm %v3, 61440 -; vn %v24, %v24, %v3 +; vgbm %v2, 61440 +; vn %v24, %v24, %v2 ; br %r14 function %scalar_to_vector_f32x4_lane_3(f32x4) -> f32x4 { @@ -1931,9 +1931,9 @@ block0(v0: f32x4): } ; block0: -; vrepf %v3, %v24, 3 -; vgbm %v5, 61440 -; vn %v24, %v3, %v5 +; vrepf %v2, %v24, 3 +; vgbm %v4, 61440 +; vn %v24, %v2, %v4 ; br %r14 function %scalar_to_vector_f32x4_mem(i64) -> f32x4 { @@ -1957,7 +1957,7 @@ block0(v0: i64): ; block0: ; vgbm %v24, 0 -; lrv %r3, 0(%r2) -; vlvgf %v24, %r3, 0 +; lrv %r2, 0(%r2) +; vlvgf %v24, %r2, 0 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/vec-logical.clif b/cranelift/filetests/filetests/isa/s390x/vec-logical.clif index 0d4b63019d..04aa8cfd85 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-logical.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-logical.clif @@ -8,8 +8,8 @@ block0(v0: i64x2): } ; block0: -; vgbm %v3, 0 -; vceqgs %v5, %v24, %v3 +; vgbm %v2, 0 +; vceqgs %v4, %v24, %v2 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -21,8 +21,8 @@ block0(v0: i32x4): } ; block0: -; vgbm %v3, 0 -; vceqfs %v5, %v24, %v3 +; vgbm %v2, 0 +; vceqfs %v4, %v24, %v2 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -34,8 +34,8 @@ block0(v0: i16x8): } ; block0: -; vgbm %v3, 0 -; vceqhs %v5, %v24, %v3 +; vgbm %v2, 0 +; vceqhs %v4, %v24, %v2 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -47,8 +47,8 @@ block0(v0: i8x16): } ; block0: -; vgbm %v3, 0 -; vceqbs %v5, %v24, %v3 +; vgbm %v2, 0 +; vceqbs %v4, %v24, %v2 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -60,8 +60,8 @@ block0(v0: i64x2): } ; block0: -; vgbm %v3, 0 -; vceqgs %v5, %v24, %v3 +; vgbm %v2, 0 +; vceqgs %v4, %v24, %v2 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -73,8 +73,8 @@ block0(v0: i32x4): } ; block0: -; vgbm %v3, 0 -; vceqfs %v5, %v24, %v3 +; vgbm %v2, 0 +; vceqfs %v4, %v24, %v2 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -86,8 +86,8 @@ block0(v0: i16x8): } ; block0: -; vgbm %v3, 0 -; vceqhs %v5, %v24, %v3 +; vgbm %v2, 0 +; vceqhs %v4, %v24, %v2 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -99,8 +99,8 @@ block0(v0: i8x16): } ; block0: -; vgbm %v3, 0 -; vceqbs %v5, %v24, %v3 +; vgbm %v2, 0 +; vceqbs %v4, %v24, %v2 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -113,7 +113,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vceqgs %v4, %v24, %v25 +; vceqgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochino %r2, 1 ; br %r14 @@ -126,7 +126,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vceqgs %v4, %v24, %v25 +; vceqgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -139,7 +139,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchgs %v4, %v24, %v25 +; vchgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochino %r2, 1 ; br %r14 @@ -152,7 +152,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchgs %v4, %v24, %v25 +; vchgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -165,7 +165,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchgs %v4, %v25, %v24 +; vchgs %v3, %v25, %v24 ; lhi %r2, 0 ; lochino %r2, 1 ; br %r14 @@ -178,7 +178,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchgs %v4, %v25, %v24 +; vchgs %v3, %v25, %v24 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -191,7 +191,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchlgs %v4, %v24, %v25 +; vchlgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochino %r2, 1 ; br %r14 @@ -204,7 +204,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchlgs %v4, %v24, %v25 +; vchlgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -217,7 +217,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchlgs %v4, %v25, %v24 +; vchlgs %v3, %v25, %v24 ; lhi %r2, 0 ; lochino %r2, 1 ; br %r14 @@ -230,7 +230,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchlgs %v4, %v25, %v24 +; vchlgs %v3, %v25, %v24 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -243,7 +243,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfcedbs %v4, %v24, %v25 +; vfcedbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochino %r2, 1 ; br %r14 @@ -256,7 +256,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfcedbs %v4, %v24, %v25 +; vfcedbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -269,7 +269,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdbs %v4, %v24, %v25 +; vfchdbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochino %r2, 1 ; br %r14 @@ -282,7 +282,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdbs %v4, %v24, %v25 +; vfchdbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -295,7 +295,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedbs %v4, %v24, %v25 +; vfchedbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochino %r2, 1 ; br %r14 @@ -308,7 +308,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedbs %v4, %v24, %v25 +; vfchedbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -321,7 +321,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdbs %v4, %v25, %v24 +; vfchdbs %v3, %v25, %v24 ; lhi %r2, 0 ; lochino %r2, 1 ; br %r14 @@ -334,7 +334,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdbs %v4, %v25, %v24 +; vfchdbs %v3, %v25, %v24 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -347,7 +347,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedbs %v4, %v25, %v24 +; vfchedbs %v3, %v25, %v24 ; lhi %r2, 0 ; lochino %r2, 1 ; br %r14 @@ -360,7 +360,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedbs %v4, %v25, %v24 +; vfchedbs %v3, %v25, %v24 ; lhi %r2, 0 ; lochine %r2, 1 ; br %r14 @@ -373,7 +373,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vceqgs %v4, %v24, %v25 +; vceqgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -386,7 +386,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vceqgs %v4, %v24, %v25 +; vceqgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -399,7 +399,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchgs %v4, %v24, %v25 +; vchgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -412,7 +412,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchgs %v4, %v24, %v25 +; vchgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -425,7 +425,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchgs %v4, %v25, %v24 +; vchgs %v3, %v25, %v24 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -438,7 +438,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchgs %v4, %v25, %v24 +; vchgs %v3, %v25, %v24 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -451,7 +451,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchlgs %v4, %v24, %v25 +; vchlgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -464,7 +464,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchlgs %v4, %v24, %v25 +; vchlgs %v3, %v24, %v25 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -477,7 +477,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchlgs %v4, %v25, %v24 +; vchlgs %v3, %v25, %v24 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -490,7 +490,7 @@ block0(v0: i64x2, v1: i64x2): } ; block0: -; vchlgs %v4, %v25, %v24 +; vchlgs %v3, %v25, %v24 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -503,7 +503,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfcedbs %v4, %v24, %v25 +; vfcedbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -516,7 +516,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfcedbs %v4, %v24, %v25 +; vfcedbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -529,7 +529,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdbs %v4, %v24, %v25 +; vfchdbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -542,7 +542,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdbs %v4, %v24, %v25 +; vfchdbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -555,7 +555,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedbs %v4, %v24, %v25 +; vfchedbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -568,7 +568,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedbs %v4, %v24, %v25 +; vfchedbs %v3, %v24, %v25 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -581,7 +581,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdbs %v4, %v25, %v24 +; vfchdbs %v3, %v25, %v24 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -594,7 +594,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchdbs %v4, %v25, %v24 +; vfchdbs %v3, %v25, %v24 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -607,7 +607,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedbs %v4, %v25, %v24 +; vfchedbs %v3, %v25, %v24 ; lhi %r2, 0 ; lochie %r2, 1 ; br %r14 @@ -620,7 +620,7 @@ block0(v0: f64x2, v1: f64x2): } ; block0: -; vfchedbs %v4, %v25, %v24 +; vfchedbs %v3, %v25, %v24 ; lhi %r2, 0 ; lochio %r2, 1 ; br %r14 @@ -632,9 +632,9 @@ block0(v0: i64x2): } ; block0: -; bras %r1, 20 ; data.u128 0x80808080808080808080808080804000 ; vl %v3, 0(%r1) -; vbperm %v5, %v24, %v3 -; lgdr %r2, %f5 +; bras %r1, 20 ; data.u128 0x80808080808080808080808080804000 ; vl %v2, 0(%r1) +; vbperm %v4, %v24, %v2 +; lgdr %r2, %f4 ; br %r14 function %vhigh_bits_be(i32x4) -> i64 { @@ -644,9 +644,9 @@ block0(v0: i32x4): } ; block0: -; bras %r1, 20 ; data.u128 0x80808080808080808080808060402000 ; vl %v3, 0(%r1) -; vbperm %v5, %v24, %v3 -; lgdr %r2, %f5 +; bras %r1, 20 ; data.u128 0x80808080808080808080808060402000 ; vl %v2, 0(%r1) +; vbperm %v4, %v24, %v2 +; lgdr %r2, %f4 ; br %r14 function %vhigh_bits_be(i16x8) -> i64 { @@ -656,9 +656,9 @@ block0(v0: i16x8): } ; block0: -; bras %r1, 20 ; data.u128 0x80808080808080807060504030201000 ; vl %v3, 0(%r1) -; vbperm %v5, %v24, %v3 -; lgdr %r2, %f5 +; bras %r1, 20 ; data.u128 0x80808080808080807060504030201000 ; vl %v2, 0(%r1) +; vbperm %v4, %v24, %v2 +; lgdr %r2, %f4 ; br %r14 function %vhigh_bits_be(i8x16) -> i64 { @@ -668,9 +668,9 @@ block0(v0: i8x16): } ; block0: -; bras %r1, 20 ; data.u128 0x78706860585048403830282018100800 ; vl %v3, 0(%r1) -; vbperm %v5, %v24, %v3 -; lgdr %r2, %f5 +; bras %r1, 20 ; data.u128 0x78706860585048403830282018100800 ; vl %v2, 0(%r1) +; vbperm %v4, %v24, %v2 +; lgdr %r2, %f4 ; br %r14 function %vhigh_bits_le(i64x2) -> i64 wasmtime_system_v { @@ -680,9 +680,9 @@ block0(v0: i64x2): } ; block0: -; bras %r1, 20 ; data.u128 0x80808080808080808080808080800040 ; vl %v3, 0(%r1) -; vbperm %v5, %v24, %v3 -; lgdr %r2, %f5 +; bras %r1, 20 ; data.u128 0x80808080808080808080808080800040 ; vl %v2, 0(%r1) +; vbperm %v4, %v24, %v2 +; lgdr %r2, %f4 ; br %r14 function %vhigh_bits_le(i32x4) -> i64 wasmtime_system_v { @@ -692,9 +692,9 @@ block0(v0: i32x4): } ; block0: -; bras %r1, 20 ; data.u128 0x80808080808080808080808000204060 ; vl %v3, 0(%r1) -; vbperm %v5, %v24, %v3 -; lgdr %r2, %f5 +; bras %r1, 20 ; data.u128 0x80808080808080808080808000204060 ; vl %v2, 0(%r1) +; vbperm %v4, %v24, %v2 +; lgdr %r2, %f4 ; br %r14 function %vhigh_bits_le(i16x8) -> i64 wasmtime_system_v { @@ -704,9 +704,9 @@ block0(v0: i16x8): } ; block0: -; bras %r1, 20 ; data.u128 0x80808080808080800010203040506070 ; vl %v3, 0(%r1) -; vbperm %v5, %v24, %v3 -; lgdr %r2, %f5 +; bras %r1, 20 ; data.u128 0x80808080808080800010203040506070 ; vl %v2, 0(%r1) +; vbperm %v4, %v24, %v2 +; lgdr %r2, %f4 ; br %r14 function %vhigh_bits_le(i8x16) -> i64 wasmtime_system_v { @@ -716,8 +716,8 @@ block0(v0: i8x16): } ; block0: -; bras %r1, 20 ; data.u128 0x00081018202830384048505860687078 ; vl %v3, 0(%r1) -; vbperm %v5, %v24, %v3 -; lgdr %r2, %f5 +; bras %r1, 20 ; data.u128 0x00081018202830384048505860687078 ; vl %v2, 0(%r1) +; vbperm %v4, %v24, %v2 +; lgdr %r2, %f4 ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/vec-permute-le-lane.clif b/cranelift/filetests/filetests/isa/s390x/vec-permute-le-lane.clif index 0280857b2b..5faacca81b 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-permute-le-lane.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-permute-le-lane.clif @@ -8,11 +8,11 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vgbm %v4, 0 -; vrepib %v6, 239 -; vno %v16, %v25, %v25 -; vmxlb %v18, %v6, %v16 -; vperm %v24, %v4, %v24, %v18 +; vgbm %v3, 0 +; vrepib %v5, 239 +; vno %v7, %v25, %v25 +; vmxlb %v17, %v5, %v7 +; vperm %v24, %v3, %v24, %v17 ; br %r14 function %shuffle_0(i8x16, i8x16) -> i8x16 wasmtime_system_v { @@ -22,8 +22,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vrepib %v4, 15 -; vperm %v24, %v24, %v25, %v4 +; vrepib %v3, 15 +; vperm %v24, %v24, %v25, %v3 ; br %r14 function %shuffle_1(i8x16, i8x16) -> i8x16 wasmtime_system_v { @@ -33,8 +33,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; bras %r1, 20 ; data.u128 0x0a1e000d0b1702180403090b15100f0c ; vl %v4, 0(%r1) -; vperm %v24, %v24, %v25, %v4 +; bras %r1, 20 ; data.u128 0x0a1e000d0b1702180403090b15100f0c ; vl %v3, 0(%r1) +; vperm %v24, %v24, %v25, %v3 ; br %r14 function %shuffle_2(i8x16, i8x16) -> i8x16 wasmtime_system_v { @@ -44,10 +44,10 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vgbm %v4, 1 -; bras %r1, 20 ; data.u128 0x8080808080808080808080808080800f ; vl %v6, 0(%r1) -; vperm %v16, %v24, %v25, %v6 -; vn %v24, %v4, %v16 +; vgbm %v3, 1 +; bras %r1, 20 ; data.u128 0x8080808080808080808080808080800f ; vl %v5, 0(%r1) +; vperm %v7, %v24, %v25, %v5 +; vn %v24, %v3, %v7 ; br %r14 function %shuffle_vmrhg_xy(i8x16, i8x16) -> i8x16 wasmtime_system_v { diff --git a/cranelift/filetests/filetests/isa/s390x/vec-permute.clif b/cranelift/filetests/filetests/isa/s390x/vec-permute.clif index 52df85b78b..96af760111 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-permute.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-permute.clif @@ -8,10 +8,10 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vgbm %v4, 0 -; vrepib %v6, 16 -; vmnlb %v16, %v6, %v25 -; vperm %v24, %v24, %v4, %v16 +; vgbm %v3, 0 +; vrepib %v5, 16 +; vmnlb %v7, %v5, %v25 +; vperm %v24, %v24, %v3, %v7 ; br %r14 function %shuffle_0(i8x16, i8x16) -> i8x16 { @@ -21,8 +21,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vgbm %v4, 0 -; vperm %v24, %v24, %v25, %v4 +; vgbm %v3, 0 +; vperm %v24, %v24, %v25, %v3 ; br %r14 function %shuffle_1(i8x16, i8x16) -> i8x16 { @@ -32,8 +32,8 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; bras %r1, 20 ; data.u128 0x03001f1a04060c0b170d1804020f1105 ; vl %v4, 0(%r1) -; vperm %v24, %v24, %v25, %v4 +; bras %r1, 20 ; data.u128 0x03001f1a04060c0b170d1804020f1105 ; vl %v3, 0(%r1) +; vperm %v24, %v24, %v25, %v3 ; br %r14 function %shuffle_2(i8x16, i8x16) -> i8x16 { @@ -43,10 +43,10 @@ block0(v0: i8x16, v1: i8x16): } ; block0: -; vgbm %v4, 32768 -; bras %r1, 20 ; data.u128 0x00808080808080808080808080808080 ; vl %v6, 0(%r1) -; vperm %v16, %v24, %v25, %v6 -; vn %v24, %v4, %v16 +; vgbm %v3, 32768 +; bras %r1, 20 ; data.u128 0x00808080808080808080808080808080 ; vl %v5, 0(%r1) +; vperm %v7, %v24, %v25, %v5 +; vn %v24, %v3, %v7 ; br %r14 function %shuffle_vmrhg_xy(i8x16, i8x16) -> i8x16 { diff --git a/cranelift/filetests/filetests/isa/s390x/vec-shift-rotate.clif b/cranelift/filetests/filetests/isa/s390x/vec-shift-rotate.clif index 404154fa05..74445bbac4 100644 --- a/cranelift/filetests/filetests/isa/s390x/vec-shift-rotate.clif +++ b/cranelift/filetests/filetests/isa/s390x/vec-shift-rotate.clif @@ -8,8 +8,8 @@ block0(v0: i64x2, v1: i64): } ; block0: -; lcr %r2, %r2 -; verllg %v24, %v24, 0(%r2) +; lcr %r5, %r2 +; verllg %v24, %v24, 0(%r5) ; br %r14 function %rotr_i64x4_imm(i64x2) -> i64x2 { @@ -30,8 +30,8 @@ block0(v0: i32x4, v1: i32): } ; block0: -; lcr %r2, %r2 -; verllf %v24, %v24, 0(%r2) +; lcr %r5, %r2 +; verllf %v24, %v24, 0(%r5) ; br %r14 function %rotr_i32x4_imm(i32x4) -> i32x4 { @@ -52,8 +52,8 @@ block0(v0: i16x8, v1: i16): } ; block0: -; lcr %r2, %r2 -; verllh %v24, %v24, 0(%r2) +; lcr %r5, %r2 +; verllh %v24, %v24, 0(%r5) ; br %r14 function %rotr_i16x8_imm(i16x8) -> i16x8 { @@ -74,8 +74,8 @@ block0(v0: i8x16, v1: i8): } ; block0: -; lcr %r2, %r2 -; verllb %v24, %v24, 0(%r2) +; lcr %r5, %r2 +; verllb %v24, %v24, 0(%r5) ; br %r14 function %rotr_i8x16_imm(i8x16) -> i8x16 { diff --git a/cranelift/filetests/filetests/isa/s390x/vecmem-arch13.clif b/cranelift/filetests/filetests/isa/s390x/vecmem-arch13.clif index d6ba01b983..6c00ca43a1 100644 --- a/cranelift/filetests/filetests/isa/s390x/vecmem-arch13.clif +++ b/cranelift/filetests/filetests/isa/s390x/vecmem-arch13.clif @@ -8,8 +8,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuplhb %v24, %v3 +; ld %f2, 0(%r2) +; vuplhb %v24, %v2 ; br %r14 function %uload16x4_big(i64) -> i32x4 { @@ -19,8 +19,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuplhh %v24, %v3 +; ld %f2, 0(%r2) +; vuplhh %v24, %v2 ; br %r14 function %uload32x2_big(i64) -> i64x2 { @@ -30,8 +30,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuplhf %v24, %v3 +; ld %f2, 0(%r2) +; vuplhf %v24, %v2 ; br %r14 function %sload8x8_big(i64) -> i16x8 { @@ -41,8 +41,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuphb %v24, %v3 +; ld %f2, 0(%r2) +; vuphb %v24, %v2 ; br %r14 function %sload16x4_big(i64) -> i32x4 { @@ -52,8 +52,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuphh %v24, %v3 +; ld %f2, 0(%r2) +; vuphh %v24, %v2 ; br %r14 function %sload32x2_big(i64) -> i64x2 { @@ -63,8 +63,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuphf %v24, %v3 +; ld %f2, 0(%r2) +; vuphf %v24, %v2 ; br %r14 function %load_i8x16_big(i64) -> i8x16 { @@ -114,8 +114,8 @@ block0(v0: i64): } ; block0: -; vl %v4, 0(%r3) -; vst %v4, 0(%r2) +; vl %v3, 0(%r3) +; vst %v3, 0(%r2) ; br %r14 function %load_f32x4_big(i64) -> f32x4 { @@ -216,8 +216,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuplhb %v24, %v3 +; ld %f2, 0(%r2) +; vuplhb %v24, %v2 ; br %r14 function %uload16x4_little(i64) -> i32x4 { @@ -227,9 +227,9 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; verllh %v5, %v3, 8 -; vuplhh %v24, %v5 +; ld %f2, 0(%r2) +; verllh %v4, %v2, 8 +; vuplhh %v24, %v4 ; br %r14 function %uload32x2_little(i64) -> i64x2 { @@ -239,9 +239,9 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; verllg %v5, %v3, 32 -; vuplhf %v24, %v5 +; vlebrg %v2, 0(%r2), 0 +; verllg %v4, %v2, 32 +; vuplhf %v24, %v4 ; br %r14 function %sload8x8_little(i64) -> i16x8 { @@ -251,8 +251,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuphb %v24, %v3 +; ld %f2, 0(%r2) +; vuphb %v24, %v2 ; br %r14 function %sload16x4_little(i64) -> i32x4 { @@ -262,9 +262,9 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; verllh %v5, %v3, 8 -; vuphh %v24, %v5 +; ld %f2, 0(%r2) +; verllh %v4, %v2, 8 +; vuphh %v24, %v4 ; br %r14 function %sload32x2_little(i64) -> i64x2 { @@ -274,9 +274,9 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; verllg %v5, %v3, 32 -; vuphf %v24, %v5 +; vlebrg %v2, 0(%r2), 0 +; verllg %v4, %v2, 32 +; vuphf %v24, %v4 ; br %r14 function %load_i8x16_little(i64) -> i8x16 { @@ -326,8 +326,8 @@ block0(v0: i64): } ; block0: -; vlbrq %v4, 0(%r3) -; vst %v4, 0(%r2) +; vlbrq %v3, 0(%r3) +; vst %v3, 0(%r2) ; br %r14 function %load_f32x4_little(i64) -> f32x4 { diff --git a/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane-arch13.clif b/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane-arch13.clif index d2f56f9cc0..19211d0855 100644 --- a/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane-arch13.clif +++ b/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane-arch13.clif @@ -8,8 +8,8 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; vuplhb %v24, %v3 +; vlebrg %v2, 0(%r2), 0 +; vuplhb %v24, %v2 ; br %r14 function %uload16x4_big(i64) -> i32x4 wasmtime_system_v { @@ -19,9 +19,9 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; verllh %v5, %v3, 8 -; vuplhh %v24, %v5 +; vlebrg %v2, 0(%r2), 0 +; verllh %v4, %v2, 8 +; vuplhh %v24, %v4 ; br %r14 function %uload32x2_big(i64) -> i64x2 wasmtime_system_v { @@ -31,9 +31,9 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; verllg %v5, %v3, 32 -; vuplhf %v24, %v5 +; ld %f2, 0(%r2) +; verllg %v4, %v2, 32 +; vuplhf %v24, %v4 ; br %r14 function %sload8x8_big(i64) -> i16x8 wasmtime_system_v { @@ -43,8 +43,8 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; vuphb %v24, %v3 +; vlebrg %v2, 0(%r2), 0 +; vuphb %v24, %v2 ; br %r14 function %sload16x4_big(i64) -> i32x4 wasmtime_system_v { @@ -54,9 +54,9 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; verllh %v5, %v3, 8 -; vuphh %v24, %v5 +; vlebrg %v2, 0(%r2), 0 +; verllh %v4, %v2, 8 +; vuphh %v24, %v4 ; br %r14 function %sload32x2_big(i64) -> i64x2 wasmtime_system_v { @@ -66,9 +66,9 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; verllg %v5, %v3, 32 -; vuphf %v24, %v5 +; ld %f2, 0(%r2) +; verllg %v4, %v2, 32 +; vuphf %v24, %v4 ; br %r14 function %load_i8x16_big(i64) -> i8x16 wasmtime_system_v { @@ -198,8 +198,8 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; vuplhb %v24, %v3 +; vlebrg %v2, 0(%r2), 0 +; vuplhb %v24, %v2 ; br %r14 function %uload16x4_little(i64) -> i32x4 wasmtime_system_v { @@ -209,8 +209,8 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; vuplhh %v24, %v3 +; vlebrg %v2, 0(%r2), 0 +; vuplhh %v24, %v2 ; br %r14 function %uload32x2_little(i64) -> i64x2 wasmtime_system_v { @@ -220,8 +220,8 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; vuplhf %v24, %v3 +; vlebrg %v2, 0(%r2), 0 +; vuplhf %v24, %v2 ; br %r14 function %sload8x8_little(i64) -> i16x8 wasmtime_system_v { @@ -231,8 +231,8 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; vuphb %v24, %v3 +; vlebrg %v2, 0(%r2), 0 +; vuphb %v24, %v2 ; br %r14 function %sload16x4_little(i64) -> i32x4 wasmtime_system_v { @@ -242,8 +242,8 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; vuphh %v24, %v3 +; vlebrg %v2, 0(%r2), 0 +; vuphh %v24, %v2 ; br %r14 function %sload32x2_little(i64) -> i64x2 wasmtime_system_v { @@ -253,8 +253,8 @@ block0(v0: i64): } ; block0: -; vlebrg %v3, 0(%r2), 0 -; vuphf %v24, %v3 +; vlebrg %v2, 0(%r2), 0 +; vuphf %v24, %v2 ; br %r14 function %load_i8x16_little(i64) -> i8x16 wasmtime_system_v { diff --git a/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane.clif b/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane.clif index b48245751d..8f989d11a3 100644 --- a/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane.clif +++ b/cranelift/filetests/filetests/isa/s390x/vecmem-le-lane.clif @@ -8,9 +8,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vuplhb %v24, %v5 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vuplhb %v24, %v4 ; br %r14 function %uload16x4_big(i64) -> i32x4 wasmtime_system_v { @@ -20,10 +20,10 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; verllh %v7, %v5, 8 -; vuplhh %v24, %v7 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; verllh %v6, %v4, 8 +; vuplhh %v24, %v6 ; br %r14 function %uload32x2_big(i64) -> i64x2 wasmtime_system_v { @@ -33,9 +33,9 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; verllg %v5, %v3, 32 -; vuplhf %v24, %v5 +; ld %f2, 0(%r2) +; verllg %v4, %v2, 32 +; vuplhf %v24, %v4 ; br %r14 function %sload8x8_big(i64) -> i16x8 wasmtime_system_v { @@ -45,9 +45,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vuphb %v24, %v5 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vuphb %v24, %v4 ; br %r14 function %sload16x4_big(i64) -> i32x4 wasmtime_system_v { @@ -57,10 +57,10 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; verllh %v7, %v5, 8 -; vuphh %v24, %v7 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; verllh %v6, %v4, 8 +; vuphh %v24, %v6 ; br %r14 function %sload32x2_big(i64) -> i64x2 wasmtime_system_v { @@ -70,9 +70,9 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; verllg %v5, %v3, 32 -; vuphf %v24, %v5 +; ld %f2, 0(%r2) +; verllg %v4, %v2, 32 +; vuphf %v24, %v4 ; br %r14 function %load_i8x16_big(i64) -> i8x16 wasmtime_system_v { @@ -82,9 +82,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v24, %r3, %r5 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v24, %r2, %r4 ; br %r14 function %load_i16x8_big(i64) -> i16x8 wasmtime_system_v { @@ -94,10 +94,10 @@ block0(v0: i64): } ; block0: -; vl %v3, 0(%r2) -; vpdi %v5, %v3, %v3, 4 -; verllg %v7, %v5, 32 -; verllf %v24, %v7, 16 +; vl %v2, 0(%r2) +; vpdi %v4, %v2, %v2, 4 +; verllg %v6, %v4, 32 +; verllf %v24, %v6, 16 ; br %r14 function %load_i32x4_big(i64) -> i32x4 wasmtime_system_v { @@ -107,9 +107,9 @@ block0(v0: i64): } ; block0: -; vl %v3, 0(%r2) -; vpdi %v5, %v3, %v3, 4 -; verllg %v24, %v5, 32 +; vl %v2, 0(%r2) +; vpdi %v4, %v2, %v2, 4 +; verllg %v24, %v4, 32 ; br %r14 function %load_i64x2_big(i64) -> i64x2 wasmtime_system_v { @@ -119,8 +119,8 @@ block0(v0: i64): } ; block0: -; vl %v3, 0(%r2) -; vpdi %v24, %v3, %v3, 4 +; vl %v2, 0(%r2) +; vpdi %v24, %v2, %v2, 4 ; br %r14 function %load_f32x4_big(i64) -> f32x4 wasmtime_system_v { @@ -130,9 +130,9 @@ block0(v0: i64): } ; block0: -; vl %v3, 0(%r2) -; vpdi %v5, %v3, %v3, 4 -; verllg %v24, %v5, 32 +; vl %v2, 0(%r2) +; vpdi %v4, %v2, %v2, 4 +; verllg %v24, %v4, 32 ; br %r14 function %load_f64x2_big(i64) -> f64x2 wasmtime_system_v { @@ -142,8 +142,8 @@ block0(v0: i64): } ; block0: -; vl %v3, 0(%r2) -; vpdi %v24, %v3, %v3, 4 +; vl %v2, 0(%r2) +; vpdi %v24, %v2, %v2, 4 ; br %r14 function %store_i8x16_big(i8x16, i64) wasmtime_system_v { @@ -225,9 +225,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vuplhb %v24, %v5 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vuplhb %v24, %v4 ; br %r14 function %uload16x4_little(i64) -> i32x4 wasmtime_system_v { @@ -237,9 +237,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vuplhh %v24, %v5 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vuplhh %v24, %v4 ; br %r14 function %uload32x2_little(i64) -> i64x2 wasmtime_system_v { @@ -249,9 +249,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vuplhf %v24, %v5 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vuplhf %v24, %v4 ; br %r14 function %sload8x8_little(i64) -> i16x8 wasmtime_system_v { @@ -261,9 +261,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vuphb %v24, %v5 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vuphb %v24, %v4 ; br %r14 function %sload16x4_little(i64) -> i32x4 wasmtime_system_v { @@ -273,9 +273,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vuphh %v24, %v5 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vuphh %v24, %v4 ; br %r14 function %sload32x2_little(i64) -> i64x2 wasmtime_system_v { @@ -285,9 +285,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; vuphf %v24, %v5 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; vuphf %v24, %v4 ; br %r14 function %load_i8x16_little(i64) -> i8x16 wasmtime_system_v { @@ -297,9 +297,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v24, %r3, %r5 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v24, %r2, %r4 ; br %r14 function %load_i16x8_little(i64) -> i16x8 wasmtime_system_v { @@ -309,9 +309,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v24, %r3, %r5 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v24, %r2, %r4 ; br %r14 function %load_i32x4_little(i64) -> i32x4 wasmtime_system_v { @@ -321,9 +321,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v24, %r3, %r5 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v24, %r2, %r4 ; br %r14 function %load_i64x2_little(i64) -> i64x2 wasmtime_system_v { @@ -333,9 +333,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v24, %r3, %r5 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v24, %r2, %r4 ; br %r14 function %load_f32x4_little(i64) -> f32x4 wasmtime_system_v { @@ -345,9 +345,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v24, %r3, %r5 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v24, %r2, %r4 ; br %r14 function %load_f64x2_little(i64) -> f64x2 wasmtime_system_v { @@ -357,9 +357,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v24, %r3, %r5 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v24, %r2, %r4 ; br %r14 function %load_f64x2_sum_little(i64, i64) -> f64x2 wasmtime_system_v { @@ -370,9 +370,9 @@ block0(v0: i64, v1: i64): } ; block0: -; lrvg %r4, 0(%r3,%r2) -; lrvg %r5, 8(%r3,%r2) -; vlvgp %v24, %r5, %r4 +; lrvg %r5, 0(%r3,%r2) +; lrvg %r3, 8(%r3,%r2) +; vlvgp %v24, %r3, %r5 ; br %r14 function %load_f64x2_off_little(i64) -> f64x2 wasmtime_system_v { @@ -382,9 +382,9 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 128(%r2) -; lrvg %r3, 136(%r2) -; vlvgp %v24, %r3, %r5 +; lrvg %r4, 128(%r2) +; lrvg %r2, 136(%r2) +; vlvgp %v24, %r2, %r4 ; br %r14 function %store_i8x16_little(i8x16, i64) wasmtime_system_v { diff --git a/cranelift/filetests/filetests/isa/s390x/vecmem.clif b/cranelift/filetests/filetests/isa/s390x/vecmem.clif index 2dba0bbbd3..6da198044f 100644 --- a/cranelift/filetests/filetests/isa/s390x/vecmem.clif +++ b/cranelift/filetests/filetests/isa/s390x/vecmem.clif @@ -8,8 +8,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuplhb %v24, %v3 +; ld %f2, 0(%r2) +; vuplhb %v24, %v2 ; br %r14 function %uload16x4_big(i64) -> i32x4 { @@ -19,8 +19,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuplhh %v24, %v3 +; ld %f2, 0(%r2) +; vuplhh %v24, %v2 ; br %r14 function %uload32x2_big(i64) -> i64x2 { @@ -30,8 +30,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuplhf %v24, %v3 +; ld %f2, 0(%r2) +; vuplhf %v24, %v2 ; br %r14 function %sload8x8_big(i64) -> i16x8 { @@ -41,8 +41,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuphb %v24, %v3 +; ld %f2, 0(%r2) +; vuphb %v24, %v2 ; br %r14 function %sload16x4_big(i64) -> i32x4 { @@ -52,8 +52,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuphh %v24, %v3 +; ld %f2, 0(%r2) +; vuphh %v24, %v2 ; br %r14 function %sload32x2_big(i64) -> i64x2 { @@ -63,8 +63,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuphf %v24, %v3 +; ld %f2, 0(%r2) +; vuphf %v24, %v2 ; br %r14 function %load_i8x16_big(i64) -> i8x16 { @@ -114,8 +114,8 @@ block0(v0: i64): } ; block0: -; vl %v4, 0(%r3) -; vst %v4, 0(%r2) +; vl %v3, 0(%r3) +; vst %v3, 0(%r2) ; br %r14 function %load_f32x4_big(i64) -> f32x4 { @@ -216,8 +216,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuplhb %v24, %v3 +; ld %f2, 0(%r2) +; vuplhb %v24, %v2 ; br %r14 function %uload16x4_little(i64) -> i32x4 { @@ -227,9 +227,9 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; verllh %v5, %v3, 8 -; vuplhh %v24, %v5 +; ld %f2, 0(%r2) +; verllh %v4, %v2, 8 +; vuplhh %v24, %v4 ; br %r14 function %uload32x2_little(i64) -> i64x2 { @@ -239,10 +239,10 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; verllg %v7, %v5, 32 -; vuplhf %v24, %v7 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; verllg %v6, %v4, 32 +; vuplhf %v24, %v6 ; br %r14 function %sload8x8_little(i64) -> i16x8 { @@ -252,8 +252,8 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; vuphb %v24, %v3 +; ld %f2, 0(%r2) +; vuphb %v24, %v2 ; br %r14 function %sload16x4_little(i64) -> i32x4 { @@ -263,9 +263,9 @@ block0(v0: i64): } ; block0: -; ld %f3, 0(%r2) -; verllh %v5, %v3, 8 -; vuphh %v24, %v5 +; ld %f2, 0(%r2) +; verllh %v4, %v2, 8 +; vuphh %v24, %v4 ; br %r14 function %sload32x2_little(i64) -> i64x2 { @@ -275,10 +275,10 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; ldgr %f5, %r5 -; verllg %v7, %v5, 32 -; vuphf %v24, %v7 +; lrvg %r4, 0(%r2) +; ldgr %f4, %r4 +; verllg %v6, %v4, 32 +; vuphf %v24, %v6 ; br %r14 function %load_i8x16_little(i64) -> i8x16 { @@ -298,12 +298,12 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v7, %r3, %r5 -; vpdi %v17, %v7, %v7, 4 -; verllg %v19, %v17, 32 -; verllf %v24, %v19, 16 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v6, %r2, %r4 +; vpdi %v16, %v6, %v6, 4 +; verllg %v18, %v16, 32 +; verllf %v24, %v18, 16 ; br %r14 function %load_i32x4_little(i64) -> i32x4 { @@ -313,11 +313,11 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v7, %r3, %r5 -; vpdi %v17, %v7, %v7, 4 -; verllg %v24, %v17, 32 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v6, %r2, %r4 +; vpdi %v16, %v6, %v6, 4 +; verllg %v24, %v16, 32 ; br %r14 function %load_i64x2_little(i64) -> i64x2 { @@ -327,10 +327,10 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v7, %r3, %r5 -; vpdi %v24, %v7, %v7, 4 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v6, %r2, %r4 +; vpdi %v24, %v6, %v6, 4 ; br %r14 function %load_i128_little(i64) -> i128 { @@ -340,10 +340,10 @@ block0(v0: i64): } ; block0: -; lrvg %r4, 0(%r3) -; lrvg %r5, 8(%r3) -; vlvgp %v16, %r5, %r4 -; vst %v16, 0(%r2) +; lrvg %r5, 0(%r3) +; lrvg %r3, 8(%r3) +; vlvgp %v7, %r3, %r5 +; vst %v7, 0(%r2) ; br %r14 function %load_f32x4_little(i64) -> f32x4 { @@ -353,11 +353,11 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v7, %r3, %r5 -; vpdi %v17, %v7, %v7, 4 -; verllg %v24, %v17, 32 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v6, %r2, %r4 +; vpdi %v16, %v6, %v6, 4 +; verllg %v24, %v16, 32 ; br %r14 function %load_f64x2_little(i64) -> f64x2 { @@ -367,10 +367,10 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 0(%r2) -; lrvg %r3, 8(%r2) -; vlvgp %v7, %r3, %r5 -; vpdi %v24, %v7, %v7, 4 +; lrvg %r4, 0(%r2) +; lrvg %r2, 8(%r2) +; vlvgp %v6, %r2, %r4 +; vpdi %v24, %v6, %v6, 4 ; br %r14 function %load_f64x2_sum_little(i64, i64) -> f64x2 { @@ -381,10 +381,10 @@ block0(v0: i64, v1: i64): } ; block0: -; lrvg %r4, 0(%r3,%r2) -; lrvg %r5, 8(%r3,%r2) -; vlvgp %v16, %r5, %r4 -; vpdi %v24, %v16, %v16, 4 +; lrvg %r5, 0(%r3,%r2) +; lrvg %r3, 8(%r3,%r2) +; vlvgp %v7, %r3, %r5 +; vpdi %v24, %v7, %v7, 4 ; br %r14 function %load_f64x2_off_little(i64) -> f64x2 { @@ -394,10 +394,10 @@ block0(v0: i64): } ; block0: -; lrvg %r5, 128(%r2) -; lrvg %r3, 136(%r2) -; vlvgp %v7, %r3, %r5 -; vpdi %v24, %v7, %v7, 4 +; lrvg %r4, 128(%r2) +; lrvg %r2, 136(%r2) +; vlvgp %v6, %r2, %r4 +; vpdi %v24, %v6, %v6, 4 ; br %r14 function %store_i8x16_little(i8x16, i64) { diff --git a/cranelift/filetests/filetests/isa/x64/amode-opt.clif b/cranelift/filetests/filetests/isa/x64/amode-opt.clif index 72bb63d321..be955ae566 100644 --- a/cranelift/filetests/filetests/isa/x64/amode-opt.clif +++ b/cranelift/filetests/filetests/isa/x64/amode-opt.clif @@ -132,8 +132,8 @@ block0(v0: i64, v1: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl %esi, %edx -; movq -1(%rdi,%rdx,8), %rax +; movl %esi, %ecx +; movq -1(%rdi,%rcx,8), %rax ; movq %rbp, %rsp ; popq %rbp ; ret @@ -153,9 +153,9 @@ block0(v0: i64, v1: i32, v2: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rsi, %r9 -; addl %r9d, %edx, %r9d -; movq -1(%rdi,%r9,4), %rax +; movq %rsi, %r8 +; addl %r8d, %edx, %r8d +; movq -1(%rdi,%r8,4), %rax ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/bmask.clif b/cranelift/filetests/filetests/isa/x64/bmask.clif index 390d5a8678..9ac3e81af3 100644 --- a/cranelift/filetests/filetests/isa/x64/bmask.clif +++ b/cranelift/filetests/filetests/isa/x64/bmask.clif @@ -12,8 +12,8 @@ block0(v0: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negq %rcx, %rcx +; movq %rdi, %rax +; negq %rax, %rax ; movq %rdi, %rax ; sbbq %rax, %rdi, %rax ; movq %rbp, %rsp @@ -29,8 +29,8 @@ block0(v0: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negq %rcx, %rcx +; movq %rdi, %rax +; negq %rax, %rax ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -46,8 +46,8 @@ block0(v0: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negq %rcx, %rcx +; movq %rdi, %rax +; negq %rax, %rax ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -63,8 +63,8 @@ block0(v0: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negq %rcx, %rcx +; movq %rdi, %rax +; negq %rax, %rax ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -80,8 +80,8 @@ block0(v0: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negl %ecx, %ecx +; movq %rdi, %rax +; negl %eax, %eax ; movq %rdi, %rax ; sbbq %rax, %rdi, %rax ; movq %rbp, %rsp @@ -97,8 +97,8 @@ block0(v0: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negl %ecx, %ecx +; movq %rdi, %rax +; negl %eax, %eax ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -114,8 +114,8 @@ block0(v0: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negl %ecx, %ecx +; movq %rdi, %rax +; negl %eax, %eax ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -131,8 +131,8 @@ block0(v0: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negl %ecx, %ecx +; movq %rdi, %rax +; negl %eax, %eax ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -148,8 +148,8 @@ block0(v0: i16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negw %cx, %cx +; movq %rdi, %rax +; negw %ax, %ax ; movq %rdi, %rax ; sbbq %rax, %rdi, %rax ; movq %rbp, %rsp @@ -165,8 +165,8 @@ block0(v0: i16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negw %cx, %cx +; movq %rdi, %rax +; negw %ax, %ax ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -182,8 +182,8 @@ block0(v0: i16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negw %cx, %cx +; movq %rdi, %rax +; negw %ax, %ax ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -199,8 +199,8 @@ block0(v0: i16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negw %cx, %cx +; movq %rdi, %rax +; negw %ax, %ax ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -216,8 +216,8 @@ block0(v0: i8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negb %cl, %cl +; movq %rdi, %rax +; negb %al, %al ; movq %rdi, %rax ; sbbq %rax, %rdi, %rax ; movq %rbp, %rsp @@ -233,8 +233,8 @@ block0(v0: i8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negb %cl, %cl +; movq %rdi, %rax +; negb %al, %al ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -250,8 +250,8 @@ block0(v0: i8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negb %cl, %cl +; movq %rdi, %rax +; negb %al, %al ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -267,8 +267,8 @@ block0(v0: i8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rcx -; negb %cl, %cl +; movq %rdi, %rax +; negb %al, %al ; movq %rdi, %rax ; sbbl %eax, %edi, %eax ; movq %rbp, %rsp @@ -286,8 +286,8 @@ block0(v0: i128): ; block0: ; movq %rdi, %rdx ; orq %rdx, %rsi, %rdx -; movq %rdx, %r10 -; negq %r10, %r10 +; movq %rdx, %r8 +; negq %r8, %r8 ; sbbq %rdx, %rdx, %rdx ; movq %rdx, %rax ; movq %rbp, %rsp @@ -305,8 +305,8 @@ block0(v0: i128): ; block0: ; movq %rdi, %rax ; orq %rax, %rsi, %rax -; movq %rax, %r9 -; negq %r9, %r9 +; movq %rax, %r8 +; negq %r8, %r8 ; sbbq %rax, %rax, %rax ; movq %rbp, %rsp ; popq %rbp @@ -323,8 +323,8 @@ block0(v0: i128): ; block0: ; movq %rdi, %rax ; orq %rax, %rsi, %rax -; movq %rax, %r9 -; negq %r9, %r9 +; movq %rax, %r8 +; negq %r8, %r8 ; sbbl %eax, %eax, %eax ; movq %rbp, %rsp ; popq %rbp @@ -341,8 +341,8 @@ block0(v0: i128): ; block0: ; movq %rdi, %rax ; orq %rax, %rsi, %rax -; movq %rax, %r9 -; negq %r9, %r9 +; movq %rax, %r8 +; negq %r8, %r8 ; sbbl %eax, %eax, %eax ; movq %rbp, %rsp ; popq %rbp @@ -359,8 +359,8 @@ block0(v0: i128): ; block0: ; movq %rdi, %rax ; orq %rax, %rsi, %rax -; movq %rax, %r9 -; negq %r9, %r9 +; movq %rax, %r8 +; negq %r8, %r8 ; sbbl %eax, %eax, %eax ; movq %rbp, %rsp ; popq %rbp @@ -375,8 +375,8 @@ block0(v0: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rdx -; negq %rdx, %rdx +; movq %rdi, %rax +; negq %rax, %rax ; movq %rdi, %rdx ; sbbq %rdx, %rdi, %rdx ; movq %rdx, %rax @@ -393,8 +393,8 @@ block0(v0: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rdx -; negl %edx, %edx +; movq %rdi, %rax +; negl %eax, %eax ; movq %rdi, %rdx ; sbbq %rdx, %rdi, %rdx ; movq %rdx, %rax @@ -411,8 +411,8 @@ block0(v0: i16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rdx -; negw %dx, %dx +; movq %rdi, %rax +; negw %ax, %ax ; movq %rdi, %rdx ; sbbq %rdx, %rdi, %rdx ; movq %rdx, %rax @@ -429,8 +429,8 @@ block0(v0: i8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rdx -; negb %dl, %dl +; movq %rdi, %rax +; negb %al, %al ; movq %rdi, %rdx ; sbbq %rdx, %rdi, %rdx ; movq %rdx, %rax diff --git a/cranelift/filetests/filetests/isa/x64/branches.clif b/cranelift/filetests/filetests/isa/x64/branches.clif index 269fef8b8a..3ec1d27d08 100644 --- a/cranelift/filetests/filetests/isa/x64/branches.clif +++ b/cranelift/filetests/filetests/isa/x64/branches.clif @@ -206,7 +206,7 @@ block2: ; movq %rsp, %rbp ; block0: ; cmpl $2, %edi -; br_table %rdi, %r9, %r10 +; br_table %rdi, %r8, %r9 ; block1: ; jmp label3 ; block2: diff --git a/cranelift/filetests/filetests/isa/x64/call-conv.clif b/cranelift/filetests/filetests/isa/x64/call-conv.clif index 6586bacce9..cfeded95f9 100644 --- a/cranelift/filetests/filetests/isa/x64/call-conv.clif +++ b/cranelift/filetests/filetests/isa/x64/call-conv.clif @@ -264,11 +264,11 @@ block0: ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl $1, %eax +; movl $1, %esi ; subq %rsp, $16, %rsp ; virtual_sp_offset_adjust 16 ; lea 0(%rsp), %rdi -; call *%rax +; call *%rsi ; movq 0(%rsp), %rdx ; addq %rsp, $16, %rsp ; virtual_sp_offset_adjust -16 @@ -287,15 +287,14 @@ block0: ; pushq %rbp ; movq %rsp, %rbp ; subq %rsp, $16, %rsp -; movq %r13, 0(%rsp) +; movq %rbx, 0(%rsp) ; block0: -; movq %rdi, %r13 -; movl $1, %edx -; call *%rdx -; movq %rdx, %r9 -; movq %r13, %rdi -; movl %r9d, 0(%rdi) -; movq 0(%rsp), %r13 +; movq %rdi, %rbx +; movl $1, %eax +; call *%rax +; movq %rbx, %rdi +; movl %edx, 0(%rdi) +; movq 0(%rsp), %rbx ; addq %rsp, $16, %rsp ; movq %rbp, %rsp ; popq %rbp @@ -312,22 +311,21 @@ block0: ; pushq %rbp ; movq %rsp, %rbp ; subq %rsp, $16, %rsp -; movq %rbx, 0(%rsp) +; movq %r13, 0(%rsp) ; block0: -; movq %rdi, %rbx -; movl $1, %r8d +; movq %rdi, %r13 +; movl $1, %eax ; subq %rsp, $16, %rsp ; virtual_sp_offset_adjust 16 ; lea 0(%rsp), %rdi -; call *%r8 -; movq %rdx, %rcx -; movq 0(%rsp), %rdx +; call *%rax +; movq 0(%rsp), %rdi ; addq %rsp, $16, %rsp ; virtual_sp_offset_adjust -16 -; movq %rbx, %rdi -; movq %rcx, 0(%rdi) -; movl %edx, 8(%rdi) -; movq 0(%rsp), %rbx +; movq %r13, %r9 +; movq %rdx, 0(%r9) +; movl %edi, 8(%r9) +; movq 0(%rsp), %r13 ; addq %rsp, $16, %rsp ; movq %rbp, %rsp ; popq %rbp @@ -344,19 +342,16 @@ block0: ; pushq %rbp ; movq %rsp, %rbp ; subq %rsp, $16, %rsp -; movq %r12, 0(%rsp) +; movq %r13, 0(%rsp) ; block0: -; movq %rdi, %r12 -; movl $1, %r9d -; call *%r9 -; movq %rax, %r9 -; movq %rdx, %r11 -; movdqa %xmm1, %xmm10 -; movq %r12, %rdi -; movq %r9, 0(%rdi) -; movl %r11d, 8(%rdi) -; movss %xmm10, 12(%rdi) -; movq 0(%rsp), %r12 +; movq %rdi, %r13 +; movl $1, %eax +; call *%rax +; movq %r13, %rdi +; movq %rax, 0(%rdi) +; movl %edx, 8(%rdi) +; movss %xmm1, 12(%rdi) +; movq 0(%rsp), %r13 ; addq %rsp, $16, %rsp ; movq %rbp, %rsp ; popq %rbp @@ -373,19 +368,16 @@ block0(v0: f32, v1: i64, v2: i32, v3: f32): ; pushq %rbp ; movq %rsp, %rbp ; subq %rsp, $16, %rsp -; movq %r13, 0(%rsp) +; movq %r12, 0(%rsp) ; block0: -; movq %rdx, %r13 -; movl $1, %eax -; call *%rax -; movq %rax, %rdi -; movq %rdx, %rcx -; movdqa %xmm1, %xmm14 -; movq %r13, %rdx -; movq %rdi, 0(%rdx) -; movl %ecx, 8(%rdx) -; movss %xmm14, 12(%rdx) -; movq 0(%rsp), %r13 +; movq %rdx, %r12 +; movl $1, %r9d +; call *%r9 +; movq %r12, %r8 +; movq %rax, 0(%r8) +; movl %edx, 8(%r8) +; movss %xmm1, 12(%r8) +; movq 0(%rsp), %r12 ; addq %rsp, $16, %rsp ; movq %rbp, %rsp ; popq %rbp diff --git a/cranelift/filetests/filetests/isa/x64/ceil-libcall.clif b/cranelift/filetests/filetests/isa/x64/ceil-libcall.clif index 2041ba21a9..f45525d33e 100644 --- a/cranelift/filetests/filetests/isa/x64/ceil-libcall.clif +++ b/cranelift/filetests/filetests/isa/x64/ceil-libcall.clif @@ -10,8 +10,8 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; load_ext_name %CeilF32+0, %rdx -; call *%rdx +; load_ext_name %CeilF32+0, %rcx +; call *%rcx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -25,8 +25,8 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; load_ext_name %CeilF64+0, %rdx -; call *%rdx +; load_ext_name %CeilF64+0, %rcx +; call *%rcx ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/cmp-mem-bug.clif b/cranelift/filetests/filetests/isa/x64/cmp-mem-bug.clif index db699e341c..50cb04ebed 100644 --- a/cranelift/filetests/filetests/isa/x64/cmp-mem-bug.clif +++ b/cranelift/filetests/filetests/isa/x64/cmp-mem-bug.clif @@ -13,11 +13,11 @@ block0(v0: i64, v1: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq 0(%rsi), %r11 -; cmpq %r11, %rdi -; setz %al -; movzbq %al, %rax -; cmpq %r11, %rdi +; movq 0(%rsi), %r9 +; cmpq %r9, %rdi +; setz %r10b +; movzbq %r10b, %rax +; cmpq %r9, %rdi ; movq %rsi, %rdx ; cmovzq %rdi, %rdx, %rdx ; movq %rbp, %rsp @@ -36,19 +36,16 @@ block0(v0: f64, v1: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movsd 0(%rdi), %xmm11 -; ucomisd %xmm11, %xmm0 -; setnp %cl -; setz %dl -; andl %ecx, %edx, %ecx -; movzbq %cl, %rax -; ucomisd %xmm0, %xmm11 -; movdqa %xmm0, %xmm12 -; mov z, sd; j%xmm0 $next; mov%xmm12 %xmm12, %xmm12; $next: -; movdqa %xmm12, %xmm4 -; mov np, sd; j%xmm0 $next; mov%xmm4 %xmm4, %xmm4; $next: -; movdqa %xmm4, %xmm12 -; movdqa %xmm12, %xmm0 +; movsd 0(%rdi), %xmm9 +; ucomisd %xmm9, %xmm0 +; setnp %dil +; setz %al +; andl %edi, %eax, %edi +; movzbq %dil, %rax +; ucomisd %xmm0, %xmm9 +; movdqa %xmm0, %xmm2 +; mov z, sd; j%xmm2 $next; mov%xmm0 %xmm0, %xmm0; $next: +; mov np, sd; j%xmm2 $next; mov%xmm0 %xmm0, %xmm0; $next: ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/conditional-values.clif b/cranelift/filetests/filetests/isa/x64/conditional-values.clif index f90d19a652..f367c4211e 100644 --- a/cranelift/filetests/filetests/isa/x64/conditional-values.clif +++ b/cranelift/filetests/filetests/isa/x64/conditional-values.clif @@ -91,8 +91,8 @@ block2: ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl 0(%rdi), %r8d -; cmpl $1, %r8d +; movl 0(%rdi), %edx +; cmpl $1, %edx ; jz label1; j label2 ; block1: ; movl $1, %eax @@ -123,8 +123,8 @@ block2: ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl 0(%rdi), %r8d -; cmpl $1, %r8d +; movl 0(%rdi), %edx +; cmpl $1, %edx ; jz label1; j label2 ; block1: ; movl $1, %eax diff --git a/cranelift/filetests/filetests/isa/x64/fabs.clif b/cranelift/filetests/filetests/isa/x64/fabs.clif index 89ab1d42b0..88c7909590 100644 --- a/cranelift/filetests/filetests/isa/x64/fabs.clif +++ b/cranelift/filetests/filetests/isa/x64/fabs.clif @@ -10,9 +10,9 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl $2147483647, %ecx -; movd %ecx, %xmm5 -; andps %xmm0, %xmm5, %xmm0 +; movl $2147483647, %eax +; movd %eax, %xmm4 +; andps %xmm0, %xmm4, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -26,9 +26,9 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movabsq $9223372036854775807, %rcx -; movq %rcx, %xmm5 -; andpd %xmm0, %xmm5, %xmm0 +; movabsq $9223372036854775807, %rax +; movq %rax, %xmm4 +; andpd %xmm0, %xmm4, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -42,9 +42,9 @@ block0(v0: f32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; pcmpeqd %xmm4, %xmm4, %xmm4 -; psrld %xmm4, $1, %xmm4 -; andps %xmm0, %xmm4, %xmm0 +; pcmpeqd %xmm3, %xmm3, %xmm3 +; psrld %xmm3, $1, %xmm3 +; andps %xmm0, %xmm3, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -58,9 +58,9 @@ block0(v0: f64x2): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; pcmpeqd %xmm4, %xmm4, %xmm4 -; psrlq %xmm4, $1, %xmm4 -; andpd %xmm0, %xmm4, %xmm0 +; pcmpeqd %xmm3, %xmm3, %xmm3 +; psrlq %xmm3, $1, %xmm3 +; andpd %xmm0, %xmm3, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/fastcall.clif b/cranelift/filetests/filetests/isa/x64/fastcall.clif index efe8a5f2c6..af565635f8 100644 --- a/cranelift/filetests/filetests/isa/x64/fastcall.clif +++ b/cranelift/filetests/filetests/isa/x64/fastcall.clif @@ -149,10 +149,7 @@ block0(v0: i64): ; pushq %rbp ; unwind PushFrameRegs { offset_upward_to_caller_sp: 16 } ; movq %rsp, %rbp -; unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 16 } -; subq %rsp, $16, %rsp -; movq %rsi, 0(%rsp) -; unwind SaveReg { clobber_offset: 0, reg: p6i } +; unwind DefineNewFrame { offset_upward_to_caller_sp: 16, offset_downward_to_clobbers: 0 } ; block0: ; cvtsi2sd %rcx, %xmm3 ; subq %rsp, $48, %rsp @@ -160,14 +157,12 @@ block0(v0: i64): ; movq %rcx, 32(%rsp) ; movq %rcx, 40(%rsp) ; movq %rcx, %rdx -; load_ext_name %g+0, %rsi +; load_ext_name %g+0, %r11 ; movq %rdx, %rcx ; movdqa %xmm3, %xmm2 -; call *%rsi +; call *%r11 ; addq %rsp, $48, %rsp ; virtual_sp_offset_adjust -48 -; movq 0(%rsp), %rsi -; addq %rsp, $16, %rsp ; movq %rbp, %rsp ; popq %rbp ; ret @@ -249,56 +244,56 @@ block0(v0: i64): ; unwind SaveReg { clobber_offset: 144, reg: p15f } ; block0: ; movsd 0(%rcx), %xmm0 -; movsd 8(%rcx), %xmm11 -; movdqu %xmm11, rsp(80 + virtual offset) -; movsd 16(%rcx), %xmm3 -; movdqu %xmm3, rsp(0 + virtual offset) -; movsd 24(%rcx), %xmm15 -; movdqu %xmm15, rsp(64 + virtual offset) -; movsd 32(%rcx), %xmm14 -; movsd 40(%rcx), %xmm1 -; movdqu %xmm1, rsp(48 + virtual offset) -; movsd 48(%rcx), %xmm8 -; movsd 56(%rcx), %xmm6 -; movdqu %xmm6, rsp(32 + virtual offset) -; movsd 64(%rcx), %xmm13 -; movsd 72(%rcx), %xmm5 -; movdqu %xmm5, rsp(16 + virtual offset) -; movsd 80(%rcx), %xmm10 -; movsd 88(%rcx), %xmm5 -; movsd 96(%rcx), %xmm4 -; movsd 104(%rcx), %xmm9 -; movsd 112(%rcx), %xmm12 -; movsd 120(%rcx), %xmm11 -; movsd 128(%rcx), %xmm7 -; movsd 136(%rcx), %xmm15 -; movsd 144(%rcx), %xmm2 -; movsd 152(%rcx), %xmm1 -; movdqu rsp(80 + virtual offset), %xmm3 -; addsd %xmm0, %xmm3, %xmm0 -; movdqu rsp(0 + virtual offset), %xmm3 -; movdqu rsp(64 + virtual offset), %xmm6 -; addsd %xmm3, %xmm6, %xmm3 -; movdqu rsp(48 + virtual offset), %xmm6 -; addsd %xmm14, %xmm6, %xmm14 -; movdqu rsp(32 + virtual offset), %xmm6 -; addsd %xmm8, %xmm6, %xmm8 -; movdqu rsp(16 + virtual offset), %xmm6 -; addsd %xmm13, %xmm6, %xmm13 -; addsd %xmm10, %xmm5, %xmm10 -; addsd %xmm4, %xmm9, %xmm4 -; addsd %xmm12, %xmm11, %xmm12 -; addsd %xmm7, %xmm15, %xmm7 -; addsd %xmm2, %xmm1, %xmm2 -; addsd %xmm0, %xmm3, %xmm0 -; addsd %xmm14, %xmm8, %xmm14 -; addsd %xmm13, %xmm10, %xmm13 -; addsd %xmm4, %xmm12, %xmm4 -; addsd %xmm7, %xmm2, %xmm7 -; addsd %xmm0, %xmm14, %xmm0 -; addsd %xmm13, %xmm4, %xmm13 +; movsd 8(%rcx), %xmm10 +; movdqu %xmm10, rsp(80 + virtual offset) +; movsd 16(%rcx), %xmm2 +; movdqu %xmm2, rsp(0 + virtual offset) +; movsd 24(%rcx), %xmm14 +; movdqu %xmm14, rsp(64 + virtual offset) +; movsd 32(%rcx), %xmm13 +; movsd 40(%rcx), %xmm15 +; movdqu %xmm15, rsp(48 + virtual offset) +; movsd 48(%rcx), %xmm7 +; movsd 56(%rcx), %xmm5 +; movdqu %xmm5, rsp(32 + virtual offset) +; movsd 64(%rcx), %xmm12 +; movsd 72(%rcx), %xmm4 +; movdqu %xmm4, rsp(16 + virtual offset) +; movsd 80(%rcx), %xmm9 +; movsd 88(%rcx), %xmm4 +; movsd 96(%rcx), %xmm3 +; movsd 104(%rcx), %xmm8 +; movsd 112(%rcx), %xmm11 +; movsd 120(%rcx), %xmm10 +; movsd 128(%rcx), %xmm6 +; movsd 136(%rcx), %xmm14 +; movsd 144(%rcx), %xmm1 +; movsd 152(%rcx), %xmm15 +; movdqu rsp(80 + virtual offset), %xmm2 +; addsd %xmm0, %xmm2, %xmm0 +; movdqu rsp(0 + virtual offset), %xmm2 +; movdqu rsp(64 + virtual offset), %xmm5 +; addsd %xmm2, %xmm5, %xmm2 +; movdqu rsp(48 + virtual offset), %xmm5 +; addsd %xmm13, %xmm5, %xmm13 +; movdqu rsp(32 + virtual offset), %xmm5 +; addsd %xmm7, %xmm5, %xmm7 +; movdqu rsp(16 + virtual offset), %xmm5 +; addsd %xmm12, %xmm5, %xmm12 +; addsd %xmm9, %xmm4, %xmm9 +; addsd %xmm3, %xmm8, %xmm3 +; addsd %xmm11, %xmm10, %xmm11 +; addsd %xmm6, %xmm14, %xmm6 +; addsd %xmm1, %xmm15, %xmm1 +; addsd %xmm0, %xmm2, %xmm0 +; addsd %xmm13, %xmm7, %xmm13 +; addsd %xmm12, %xmm9, %xmm12 +; addsd %xmm3, %xmm11, %xmm3 +; addsd %xmm6, %xmm1, %xmm6 ; addsd %xmm0, %xmm13, %xmm0 -; addsd %xmm0, %xmm7, %xmm0 +; addsd %xmm12, %xmm3, %xmm12 +; addsd %xmm0, %xmm12, %xmm0 +; addsd %xmm0, %xmm6, %xmm0 ; movdqu 96(%rsp), %xmm6 ; movdqu 112(%rsp), %xmm7 ; movdqu 128(%rsp), %xmm8 diff --git a/cranelift/filetests/filetests/isa/x64/fcopysign.clif b/cranelift/filetests/filetests/isa/x64/fcopysign.clif index a24a7994bb..344159440e 100644 --- a/cranelift/filetests/filetests/isa/x64/fcopysign.clif +++ b/cranelift/filetests/filetests/isa/x64/fcopysign.clif @@ -10,13 +10,13 @@ block0(v0: f32, v1: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl $-2147483648, %edx -; movd %edx, %xmm8 -; movdqa %xmm0, %xmm11 -; movdqa %xmm8, %xmm0 -; andnps %xmm0, %xmm11, %xmm0 -; andps %xmm8, %xmm1, %xmm8 -; orps %xmm0, %xmm8, %xmm0 +; movl $-2147483648, %ecx +; movd %ecx, %xmm7 +; movdqa %xmm0, %xmm10 +; movdqa %xmm7, %xmm0 +; andnps %xmm0, %xmm10, %xmm0 +; andps %xmm7, %xmm1, %xmm7 +; orps %xmm0, %xmm7, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -30,13 +30,13 @@ block0(v0: f64, v1: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movabsq $-9223372036854775808, %rdx -; movq %rdx, %xmm8 -; movdqa %xmm0, %xmm11 -; movdqa %xmm8, %xmm0 -; andnpd %xmm0, %xmm11, %xmm0 -; andpd %xmm8, %xmm1, %xmm8 -; orpd %xmm0, %xmm8, %xmm0 +; movabsq $-9223372036854775808, %rcx +; movq %rcx, %xmm7 +; movdqa %xmm0, %xmm10 +; movdqa %xmm7, %xmm0 +; andnpd %xmm0, %xmm10, %xmm0 +; andpd %xmm7, %xmm1, %xmm7 +; orpd %xmm0, %xmm7, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/fcvt.clif b/cranelift/filetests/filetests/isa/x64/fcvt.clif index 88725b01da..87b5e21a16 100644 --- a/cranelift/filetests/filetests/isa/x64/fcvt.clif +++ b/cranelift/filetests/filetests/isa/x64/fcvt.clif @@ -10,8 +10,8 @@ block0(v0: i8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movsbl %dil, %ecx -; cvtsi2ss %ecx, %xmm0 +; movsbl %dil, %eax +; cvtsi2ss %eax, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -25,8 +25,8 @@ block0(v0: i16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movswl %di, %ecx -; cvtsi2ss %ecx, %xmm0 +; movswl %di, %eax +; cvtsi2ss %eax, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -68,8 +68,8 @@ block0(v0: i8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movsbl %dil, %ecx -; cvtsi2sd %ecx, %xmm0 +; movsbl %dil, %eax +; cvtsi2sd %eax, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -83,8 +83,8 @@ block0(v0: i16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movswl %di, %ecx -; cvtsi2sd %ecx, %xmm0 +; movswl %di, %eax +; cvtsi2sd %eax, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -146,16 +146,16 @@ block0(v0: i8, v1: i16, v2: i32, v3: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movzbq %dil, %r10 -; cvtsi2ss %r10, %xmm0 -; movzwq %si, %r10 -; cvtsi2ss %r10, %xmm2 -; movl %edx, %r10d -; cvtsi2ss %r10, %xmm3 -; u64_to_f32_seq %rcx, %xmm15, %r10, %r11 +; movzbq %dil, %r9 +; cvtsi2ss %r9, %xmm0 +; movzwq %si, %r9 +; cvtsi2ss %r9, %xmm1 +; movl %edx, %r9d +; cvtsi2ss %r9, %xmm2 +; u64_to_f32_seq %rcx, %xmm14, %r9, %r10 +; addss %xmm0, %xmm1, %xmm0 ; addss %xmm0, %xmm2, %xmm0 -; addss %xmm0, %xmm3, %xmm0 -; addss %xmm0, %xmm15, %xmm0 +; addss %xmm0, %xmm14, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -170,10 +170,10 @@ block0(v0: i32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqu const(0), %xmm3 -; unpcklps %xmm0, %xmm3, %xmm0 -; movdqu const(1), %xmm7 -; subpd %xmm0, %xmm7, %xmm0 +; movdqu const(0), %xmm2 +; unpcklps %xmm0, %xmm2, %xmm0 +; movdqu const(1), %xmm6 +; subpd %xmm0, %xmm6, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -187,16 +187,16 @@ block0(v0: i32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm4 -; pslld %xmm4, $16, %xmm4 -; psrld %xmm4, $16, %xmm4 -; movdqa %xmm0, %xmm10 -; psubd %xmm10, %xmm4, %xmm10 -; cvtdq2ps %xmm4, %xmm9 -; psrld %xmm10, $1, %xmm10 -; cvtdq2ps %xmm10, %xmm0 +; movdqa %xmm0, %xmm3 +; pslld %xmm3, $16, %xmm3 +; psrld %xmm3, $16, %xmm3 +; movdqa %xmm0, %xmm9 +; psubd %xmm9, %xmm3, %xmm9 +; cvtdq2ps %xmm3, %xmm8 +; psrld %xmm9, $1, %xmm9 +; cvtdq2ps %xmm9, %xmm0 ; addps %xmm0, %xmm0, %xmm0 -; addps %xmm0, %xmm9, %xmm0 +; addps %xmm0, %xmm8, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -210,7 +210,7 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float32_to_uint32_seq %xmm0, %eax, %r9, %xmm4, %xmm5 +; cvt_float32_to_uint32_seq %xmm0, %eax, %r8, %xmm3, %xmm4 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -224,7 +224,7 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float32_to_uint64_seq %xmm0, %rax, %r9, %xmm4, %xmm5 +; cvt_float32_to_uint64_seq %xmm0, %rax, %r8, %xmm3, %xmm4 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -238,7 +238,7 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float64_to_uint32_seq %xmm0, %eax, %r9, %xmm4, %xmm5 +; cvt_float64_to_uint32_seq %xmm0, %eax, %r8, %xmm3, %xmm4 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -252,7 +252,7 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float64_to_uint64_seq %xmm0, %rax, %r9, %xmm4, %xmm5 +; cvt_float64_to_uint64_seq %xmm0, %rax, %r8, %xmm3, %xmm4 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -266,7 +266,7 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float32_to_uint32_sat_seq %xmm0, %eax, %r9, %xmm4, %xmm5 +; cvt_float32_to_uint32_sat_seq %xmm0, %eax, %r8, %xmm3, %xmm4 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -280,7 +280,7 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float32_to_uint64_sat_seq %xmm0, %rax, %r9, %xmm4, %xmm5 +; cvt_float32_to_uint64_sat_seq %xmm0, %rax, %r8, %xmm3, %xmm4 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -294,7 +294,7 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float64_to_uint32_sat_seq %xmm0, %eax, %r9, %xmm4, %xmm5 +; cvt_float64_to_uint32_sat_seq %xmm0, %eax, %r8, %xmm3, %xmm4 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -308,7 +308,7 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float64_to_uint64_sat_seq %xmm0, %rax, %r9, %xmm4, %xmm5 +; cvt_float64_to_uint64_sat_seq %xmm0, %rax, %r8, %xmm3, %xmm4 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -322,7 +322,7 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float32_to_sint32_seq %xmm0, %eax, %r8, %xmm4 +; cvt_float32_to_sint32_seq %xmm0, %eax, %rdx, %xmm3 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -336,7 +336,7 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float32_to_sint64_seq %xmm0, %rax, %r8, %xmm4 +; cvt_float32_to_sint64_seq %xmm0, %rax, %rdx, %xmm3 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -350,7 +350,7 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float64_to_sint32_seq %xmm0, %eax, %r8, %xmm4 +; cvt_float64_to_sint32_seq %xmm0, %eax, %rdx, %xmm3 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -364,7 +364,7 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float64_to_sint64_seq %xmm0, %rax, %r8, %xmm4 +; cvt_float64_to_sint64_seq %xmm0, %rax, %rdx, %xmm3 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -378,7 +378,7 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float32_to_sint32_sat_seq %xmm0, %eax, %r8, %xmm4 +; cvt_float32_to_sint32_sat_seq %xmm0, %eax, %rdx, %xmm3 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -392,7 +392,7 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float32_to_sint64_sat_seq %xmm0, %rax, %r8, %xmm4 +; cvt_float32_to_sint64_sat_seq %xmm0, %rax, %rdx, %xmm3 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -406,7 +406,7 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float64_to_sint32_sat_seq %xmm0, %eax, %r8, %xmm4 +; cvt_float64_to_sint32_sat_seq %xmm0, %eax, %rdx, %xmm3 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -420,7 +420,7 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; cvt_float64_to_sint64_sat_seq %xmm0, %rax, %r8, %xmm4 +; cvt_float64_to_sint64_sat_seq %xmm0, %rax, %rdx, %xmm3 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -434,20 +434,20 @@ block0(v0: f32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; pxor %xmm3, %xmm3, %xmm3 -; movdqa %xmm0, %xmm10 -; maxps %xmm10, %xmm3, %xmm10 -; pcmpeqd %xmm8, %xmm8, %xmm8 -; psrld %xmm8, $1, %xmm8 -; cvtdq2ps %xmm8, %xmm14 -; cvttps2dq %xmm10, %xmm13 -; subps %xmm10, %xmm14, %xmm10 -; cmpps $2, %xmm14, %xmm10, %xmm14 -; cvttps2dq %xmm10, %xmm0 -; pxor %xmm0, %xmm14, %xmm0 -; pxor %xmm7, %xmm7, %xmm7 -; pmaxsd %xmm0, %xmm7, %xmm0 -; paddd %xmm0, %xmm13, %xmm0 +; pxor %xmm2, %xmm2, %xmm2 +; movdqa %xmm0, %xmm9 +; maxps %xmm9, %xmm2, %xmm9 +; pcmpeqd %xmm7, %xmm7, %xmm7 +; psrld %xmm7, $1, %xmm7 +; cvtdq2ps %xmm7, %xmm13 +; cvttps2dq %xmm9, %xmm12 +; subps %xmm9, %xmm13, %xmm9 +; cmpps $2, %xmm13, %xmm9, %xmm13 +; cvttps2dq %xmm9, %xmm0 +; pxor %xmm0, %xmm13, %xmm0 +; pxor %xmm6, %xmm6, %xmm6 +; pmaxsd %xmm0, %xmm6, %xmm0 +; paddd %xmm0, %xmm12, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -461,16 +461,16 @@ block0(v0: f32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: +; movdqa %xmm0, %xmm4 +; cmpps $0, %xmm4, %xmm0, %xmm4 ; movdqa %xmm0, %xmm5 -; cmpps $0, %xmm5, %xmm0, %xmm5 -; movdqa %xmm0, %xmm6 -; andps %xmm6, %xmm5, %xmm6 -; pxor %xmm5, %xmm6, %xmm5 -; cvttps2dq %xmm6, %xmm9 -; movdqa %xmm9, %xmm0 -; pand %xmm0, %xmm5, %xmm0 +; andps %xmm5, %xmm4, %xmm5 +; pxor %xmm4, %xmm5, %xmm4 +; cvttps2dq %xmm5, %xmm8 +; movdqa %xmm8, %xmm0 +; pand %xmm0, %xmm4, %xmm0 ; psrad %xmm0, $31, %xmm0 -; pxor %xmm0, %xmm9, %xmm0 +; pxor %xmm0, %xmm8, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/floating-point.clif b/cranelift/filetests/filetests/isa/x64/floating-point.clif index b5b25b5ab6..b0ec687594 100644 --- a/cranelift/filetests/filetests/isa/x64/floating-point.clif +++ b/cranelift/filetests/filetests/isa/x64/floating-point.clif @@ -10,9 +10,9 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movabsq $9223372036854775807, %rcx -; movq %rcx, %xmm5 -; andpd %xmm0, %xmm5, %xmm0 +; movabsq $9223372036854775807, %rax +; movq %rax, %xmm4 +; andpd %xmm0, %xmm4, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -28,9 +28,9 @@ block0(v0: i64): ; movq %rsp, %rbp ; block0: ; movsd 0(%rdi), %xmm0 -; movabsq $9223372036854775807, %rdx -; movq %rdx, %xmm6 -; andpd %xmm0, %xmm6, %xmm0 +; movabsq $9223372036854775807, %rcx +; movq %rcx, %xmm5 +; andpd %xmm0, %xmm5, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/floor-libcall.clif b/cranelift/filetests/filetests/isa/x64/floor-libcall.clif index 745426d716..6cc482baa6 100644 --- a/cranelift/filetests/filetests/isa/x64/floor-libcall.clif +++ b/cranelift/filetests/filetests/isa/x64/floor-libcall.clif @@ -10,8 +10,8 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; load_ext_name %FloorF32+0, %rdx -; call *%rdx +; load_ext_name %FloorF32+0, %rcx +; call *%rcx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -25,8 +25,8 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; load_ext_name %FloorF64+0, %rdx -; call *%rdx +; load_ext_name %FloorF64+0, %rcx +; call *%rcx ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/fma-call.clif b/cranelift/filetests/filetests/isa/x64/fma-call.clif index 9bc580f656..d6ef54022c 100644 --- a/cranelift/filetests/filetests/isa/x64/fma-call.clif +++ b/cranelift/filetests/filetests/isa/x64/fma-call.clif @@ -10,8 +10,8 @@ block0(v0: f32, v1: f32, v2: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; load_ext_name %FmaF32+0, %r9 -; call *%r9 +; load_ext_name %FmaF32+0, %r8 +; call *%r8 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -25,8 +25,8 @@ block0(v0: f64, v1: f64, v2: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; load_ext_name %FmaF64+0, %r9 -; call *%r9 +; load_ext_name %FmaF64+0, %r8 +; call *%r8 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/fneg.clif b/cranelift/filetests/filetests/isa/x64/fneg.clif index 6b76b9d2ad..7af500eb4f 100644 --- a/cranelift/filetests/filetests/isa/x64/fneg.clif +++ b/cranelift/filetests/filetests/isa/x64/fneg.clif @@ -10,9 +10,9 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl $-2147483648, %ecx -; movd %ecx, %xmm5 -; xorps %xmm0, %xmm5, %xmm0 +; movl $-2147483648, %eax +; movd %eax, %xmm4 +; xorps %xmm0, %xmm4, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -26,9 +26,9 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movabsq $-9223372036854775808, %rcx -; movq %rcx, %xmm5 -; xorpd %xmm0, %xmm5, %xmm0 +; movabsq $-9223372036854775808, %rax +; movq %rax, %xmm4 +; xorpd %xmm0, %xmm4, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -42,9 +42,9 @@ block0(v0: f32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; pcmpeqd %xmm4, %xmm4, %xmm4 -; pslld %xmm4, $31, %xmm4 -; xorps %xmm0, %xmm4, %xmm0 +; pcmpeqd %xmm3, %xmm3, %xmm3 +; pslld %xmm3, $31, %xmm3 +; xorps %xmm0, %xmm3, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -58,9 +58,9 @@ block0(v0: f64x2): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; pcmpeqd %xmm4, %xmm4, %xmm4 -; psllq %xmm4, $63, %xmm4 -; xorpd %xmm0, %xmm4, %xmm0 +; pcmpeqd %xmm3, %xmm3, %xmm3 +; psllq %xmm3, $63, %xmm3 +; xorpd %xmm0, %xmm3, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/fp_sp_pc.clif b/cranelift/filetests/filetests/isa/x64/fp_sp_pc.clif index 04315658b8..a443691eeb 100644 --- a/cranelift/filetests/filetests/isa/x64/fp_sp_pc.clif +++ b/cranelift/filetests/filetests/isa/x64/fp_sp_pc.clif @@ -39,8 +39,8 @@ block0: ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rbp, %rdi -; movq 8(%rdi), %rax +; movq %rbp, %rsi +; movq 8(%rsi), %rax ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/heap-no-spectre.clif b/cranelift/filetests/filetests/isa/x64/heap-no-spectre.clif index 2e8740afbb..652742df8b 100644 --- a/cranelift/filetests/filetests/isa/x64/heap-no-spectre.clif +++ b/cranelift/filetests/filetests/isa/x64/heap-no-spectre.clif @@ -20,11 +20,11 @@ block0(v0: i32, v1: i64): ; movq %rsp, %rbp ; block0: ; movl %edi, %eax -; movq 8(%rsi), %r10 -; movq %rax, %r11 -; addq %r11, $32768, %r11 +; movq 8(%rsi), %r9 +; movq %rax, %r10 +; addq %r10, $32768, %r10 ; jnb ; ud2 heap_oob ; -; cmpq %r10, %r11 +; cmpq %r9, %r10 ; jbe label1; j label2 ; block1: ; addq %rax, 0(%rsi), %rax diff --git a/cranelift/filetests/filetests/isa/x64/heap.clif b/cranelift/filetests/filetests/isa/x64/heap.clif index 01d3dd97b9..b1eaaf15ff 100644 --- a/cranelift/filetests/filetests/isa/x64/heap.clif +++ b/cranelift/filetests/filetests/isa/x64/heap.clif @@ -33,17 +33,17 @@ block0(v0: i32, v1: i64): ; movq %rsp, %rbp ; block0: ; movl %edi, %eax -; movq 8(%rsi), %rdi -; movq %rax, %rcx -; addq %rcx, $32768, %rcx +; movq 8(%rsi), %r11 +; movq %rax, %rdi +; addq %rdi, $32768, %rdi ; jnb ; ud2 heap_oob ; -; cmpq %rdi, %rcx +; cmpq %r11, %rdi ; jbe label1; j label2 ; block1: ; addq %rax, 0(%rsi), %rax -; xorq %rdx, %rdx, %rdx -; cmpq %rdi, %rcx -; cmovnbeq %rdx, %rax, %rax +; xorq %rcx, %rcx, %rcx +; cmpq %r11, %rdi +; cmovnbeq %rcx, %rax, %rax ; movq %rbp, %rsp ; popq %rbp ; ret @@ -67,15 +67,15 @@ block0(v0: i64, v1: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl %esi, %r10d -; cmpq $4096, %r10 +; movl %esi, %r9d +; cmpq $4096, %r9 ; jbe label1; j label2 ; block1: -; movq %r10, %rax +; movq %r9, %rax ; addq %rax, 0(%rdi), %rax -; xorq %r11, %r11, %r11 -; cmpq $4096, %r10 -; cmovnbeq %r11, %rax, %rax +; xorq %r10, %r10, %r10 +; cmpq $4096, %r9 +; cmovnbeq %r10, %rax, %rax ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/i128.clif b/cranelift/filetests/filetests/isa/x64/i128.clif index 1fb9ffddb9..cd2fce2020 100644 --- a/cranelift/filetests/filetests/isa/x64/i128.clif +++ b/cranelift/filetests/filetests/isa/x64/i128.clif @@ -113,18 +113,19 @@ block0(v0: i128, v1: i128): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %r8 -; imulq %r8, %rcx, %r8 +; movq %rdx, %rax +; movq %rdi, %rdx +; imulq %rdx, %rcx, %rdx +; movq %rax, %rcx ; movq %rdi, %rax -; imulq %rsi, %rdx, %rsi -; movq %r8, %r9 -; addq %r9, %rsi, %r9 -; movq %r9, %r8 -; mul %rax, %rdx, %rax, %rdx -; movq %r8, %rdi -; addq %rdi, %rdx, %rdi -; movq %rdi, %r8 -; movq %r8, %rdx +; movq %rsi, %r10 +; imulq %r10, %rcx, %r10 +; addq %rdx, %r10, %rdx +; movq %rdx, %r9 +; mul %rax, %rcx, %rax, %rdx +; movq %rdx, %rcx +; movq %r9, %rdx +; addq %rdx, %rcx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -138,8 +139,8 @@ block0(v0: i64, v1: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rax ; movq %rsi, %rdx +; movq %rdi, %rax ; movq %rbp, %rsp ; popq %rbp ; ret @@ -153,8 +154,8 @@ block0(v0: i128): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rax ; movq %rsi, %rdx +; movq %rdi, %rax ; movq %rbp, %rsp ; popq %rbp ; ret @@ -193,11 +194,11 @@ block0(v0: i128, v1: i128): ; movq %r15, 48(%rsp) ; block0: ; cmpq %rdx, %rdi -; setz %r10b +; setz %r9b ; cmpq %rcx, %rsi -; setz %r11b -; andq %r10, %r11, %r10 -; testq $1, %r10 +; setz %r10b +; andq %r9, %r10, %r9 +; testq $1, %r9 ; setnz %al ; cmpq %rdx, %rdi ; setnz %r8b @@ -205,72 +206,72 @@ block0(v0: i128, v1: i128): ; setnz %r9b ; orq %r8, %r9, %r8 ; testq $1, %r8 -; setnz %r10b -; movq %r10, rsp(0 + virtual offset) +; setnz %r9b +; movq %r9, rsp(0 + virtual offset) ; cmpq %rcx, %rsi ; setl %r8b -; setz %r9b +; setz %r10b ; cmpq %rdx, %rdi ; setb %r11b -; andq %r9, %r11, %r9 -; orq %r8, %r9, %r8 +; andq %r10, %r11, %r10 +; orq %r8, %r10, %r8 ; testq $1, %r8 -; setnz %r11b +; setnz %r10b ; cmpq %rcx, %rsi -; setl %r8b -; setz %r9b +; setl %r11b +; setz %r8b ; cmpq %rdx, %rdi -; setbe %bl -; andq %r9, %rbx, %r9 -; orq %r8, %r9, %r8 -; testq $1, %r8 -; setnz %r9b -; cmpq %rcx, %rsi -; setnle %r8b -; setz %r13b -; cmpq %rdx, %rdi -; setnbe %r14b -; andq %r13, %r14, %r13 -; orq %r8, %r13, %r8 -; testq $1, %r8 +; setbe %r15b +; andq %r8, %r15, %r8 +; orq %r11, %r8, %r11 +; testq $1, %r11 ; setnz %r8b ; cmpq %rcx, %rsi -; setnle %bl +; setnle %r11b ; setz %r12b ; cmpq %rdx, %rdi -; setnb %r13b +; setnbe %r13b ; andq %r12, %r13, %r12 -; orq %rbx, %r12, %rbx -; testq $1, %rbx -; setnz %r14b +; orq %r11, %r12, %r11 +; testq $1, %r11 +; setnz %r11b ; cmpq %rcx, %rsi -; setb %r15b +; setnle %r15b ; setz %bl ; cmpq %rdx, %rdi -; setb %r12b +; setnb %r12b ; andq %rbx, %r12, %rbx ; orq %r15, %rbx, %r15 ; testq $1, %r15 +; setnz %r13b +; cmpq %rcx, %rsi +; setb %r14b +; setz %r15b +; cmpq %rdx, %rdi +; setb %bl +; andq %r15, %rbx, %r15 +; orq %r14, %r15, %r14 +; testq $1, %r14 +; setnz %r14b +; cmpq %rcx, %rsi +; setb %bl +; setz %r12b +; cmpq %rdx, %rdi +; setbe %r15b +; andq %r12, %r15, %r12 +; orq %rbx, %r12, %rbx +; testq $1, %rbx ; setnz %r15b ; cmpq %rcx, %rsi -; setb %r12b -; setz %r13b +; setnbe %bl +; setz %r12b ; cmpq %rdx, %rdi -; setbe %bl -; andq %r13, %rbx, %r13 -; orq %r12, %r13, %r12 -; testq $1, %r12 +; setnbe %r9b +; andq %r12, %r9, %r12 +; orq %rbx, %r12, %rbx +; testq $1, %rbx ; setnz %bl ; cmpq %rcx, %rsi -; setnbe %r12b -; setz %r13b -; cmpq %rdx, %rdi -; setnbe %r10b -; andq %r13, %r10, %r13 -; orq %r12, %r13, %r12 -; testq $1, %r12 -; setnz %r12b -; cmpq %rcx, %rsi ; setnbe %sil ; setz %cl ; cmpq %rdx, %rdi @@ -279,16 +280,16 @@ block0(v0: i128, v1: i128): ; orq %rsi, %rcx, %rsi ; testq $1, %rsi ; setnz %sil -; movq rsp(0 + virtual offset), %rdx -; andl %eax, %edx, %eax -; andl %r11d, %r9d, %r11d -; andl %r8d, %r14d, %r8d -; andl %r15d, %ebx, %r15d -; andl %r12d, %esi, %r12d +; movq rsp(0 + virtual offset), %rcx +; andl %eax, %ecx, %eax +; andl %r10d, %r8d, %r10d +; andl %r11d, %r13d, %r11d +; andl %r14d, %r15d, %r14d +; andl %ebx, %esi, %ebx +; andl %eax, %r10d, %eax +; andl %r11d, %r14d, %r11d ; andl %eax, %r11d, %eax -; andl %r8d, %r15d, %r8d -; andl %eax, %r8d, %eax -; andl %eax, %r12d, %eax +; andl %eax, %ebx, %eax ; movq 16(%rsp), %rbx ; movq 24(%rsp), %r12 ; movq 32(%rsp), %r13 @@ -317,10 +318,10 @@ block2: ; movq %rsp, %rbp ; block0: ; cmpq $0, %rdi -; setz %r10b +; setz %r9b ; cmpq $0, %rsi -; setz %dil -; testb %r10b, %dil +; setz %sil +; testb %r9b, %sil ; jnz label1; j label2 ; block1: ; movl $1, %eax @@ -351,10 +352,10 @@ block2: ; movq %rsp, %rbp ; block0: ; cmpq $0, %rdi -; setz %r10b +; setz %r9b ; cmpq $0, %rsi -; setz %dil -; testb %r10b, %dil +; setz %sil +; testb %r9b, %sil ; jz label1; j label2 ; block1: ; movl $1, %eax @@ -376,8 +377,8 @@ block0(v0: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; xorq %rdx, %rdx, %rdx ; movq %rdi, %rax +; xorq %rdx, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -481,47 +482,47 @@ block0(v0: i128): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rdx -; shrq $1, %rdx, %rdx -; movabsq $8608480567731124087, %r10 -; andq %rdx, %r10, %rdx -; movq %rdi, %r11 -; subq %r11, %rdx, %r11 -; shrq $1, %rdx, %rdx -; andq %rdx, %r10, %rdx -; subq %r11, %rdx, %r11 -; shrq $1, %rdx, %rdx -; andq %rdx, %r10, %rdx -; subq %r11, %rdx, %r11 -; movq %r11, %rax -; shrq $4, %rax, %rax -; addq %rax, %r11, %rax -; movabsq $1085102592571150095, %rcx -; andq %rax, %rcx, %rax -; movabsq $72340172838076673, %r9 -; imulq %rax, %r9, %rax -; shrq $56, %rax, %rax -; movq %rsi, %rcx -; shrq $1, %rcx, %rcx +; movq %rdi, %rax +; shrq $1, %rax, %rax ; movabsq $8608480567731124087, %r8 -; andq %rcx, %r8, %rcx -; movq %rsi, %r9 -; subq %r9, %rcx, %r9 -; shrq $1, %rcx, %rcx -; andq %rcx, %r8, %rcx -; subq %r9, %rcx, %r9 -; shrq $1, %rcx, %rcx -; andq %rcx, %r8, %rcx -; subq %r9, %rcx, %r9 -; movq %r9, %rcx -; shrq $4, %rcx, %rcx -; addq %rcx, %r9, %rcx -; movabsq $1085102592571150095, %rsi -; andq %rcx, %rsi, %rcx +; andq %rax, %r8, %rax +; movq %rdi, %r9 +; subq %r9, %rax, %r9 +; shrq $1, %rax, %rax +; andq %rax, %r8, %rax +; subq %r9, %rax, %r9 +; shrq $1, %rax, %rax +; andq %rax, %r8, %rax +; subq %r9, %rax, %r9 +; movq %r9, %rax +; shrq $4, %rax, %rax +; addq %rax, %r9, %rax +; movabsq $1085102592571150095, %rdi +; andq %rax, %rdi, %rax ; movabsq $72340172838076673, %rdx -; imulq %rcx, %rdx, %rcx -; shrq $56, %rcx, %rcx -; addq %rax, %rcx, %rax +; imulq %rax, %rdx, %rax +; shrq $56, %rax, %rax +; movq %rsi, %rdi +; shrq $1, %rdi, %rdi +; movabsq $8608480567731124087, %rcx +; andq %rdi, %rcx, %rdi +; movq %rsi, %rdx +; subq %rdx, %rdi, %rdx +; shrq $1, %rdi, %rdi +; andq %rdi, %rcx, %rdi +; subq %rdx, %rdi, %rdx +; shrq $1, %rdi, %rdi +; andq %rdi, %rcx, %rdi +; subq %rdx, %rdi, %rdx +; movq %rdx, %rsi +; shrq $4, %rsi, %rsi +; addq %rsi, %rdx, %rsi +; movabsq $1085102592571150095, %r10 +; andq %rsi, %r10, %rsi +; movabsq $72340172838076673, %rcx +; imulq %rsi, %rcx, %rsi +; shrq $56, %rsi, %rsi +; addq %rax, %rsi, %rax ; xorq %rdx, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp @@ -536,52 +537,10 @@ block0(v0: i128): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movabsq $6148914691236517205, %r8 -; movq %rsi, %r9 -; andq %r9, %r8, %r9 -; movq %rsi, %rax -; shrq $1, %rax, %rax -; andq %rax, %r8, %rax -; shlq $1, %r9, %r9 -; orq %r9, %rax, %r9 -; movabsq $3689348814741910323, %r11 -; movq %r9, %rsi -; andq %rsi, %r11, %rsi -; shrq $2, %r9, %r9 -; andq %r9, %r11, %r9 -; shlq $2, %rsi, %rsi -; orq %rsi, %r9, %rsi -; movabsq $1085102592571150095, %rax -; movq %rsi, %rcx -; andq %rcx, %rax, %rcx -; shrq $4, %rsi, %rsi -; andq %rsi, %rax, %rsi -; shlq $4, %rcx, %rcx -; orq %rcx, %rsi, %rcx -; movabsq $71777214294589695, %r8 -; movq %rcx, %r9 -; andq %r9, %r8, %r9 -; shrq $8, %rcx, %rcx -; andq %rcx, %r8, %rcx -; shlq $8, %r9, %r9 -; orq %r9, %rcx, %r9 -; movabsq $281470681808895, %rsi -; movq %r9, %r11 -; andq %r11, %rsi, %r11 -; shrq $16, %r9, %r9 -; andq %r9, %rsi, %r9 -; shlq $16, %r11, %r11 -; orq %r11, %r9, %r11 -; movabsq $4294967295, %rcx -; movq %r11, %rax -; andq %rax, %rcx, %rax -; shrq $32, %r11, %r11 -; shlq $32, %rax, %rax -; orq %rax, %r11, %rax ; movabsq $6148914691236517205, %rcx -; movq %rdi, %rdx +; movq %rsi, %rdx ; andq %rdx, %rcx, %rdx -; movq %rdi, %r11 +; movq %rsi, %r11 ; shrq $1, %r11, %r11 ; andq %r11, %rcx, %r11 ; shlq $1, %rdx, %rdx @@ -594,19 +553,19 @@ block0(v0: i128): ; shlq $2, %r10, %r10 ; orq %r10, %rdx, %r10 ; movabsq $1085102592571150095, %rsi -; movq %r10, %rdi -; andq %rdi, %rsi, %rdi +; movq %r10, %rax +; andq %rax, %rsi, %rax ; shrq $4, %r10, %r10 ; andq %r10, %rsi, %r10 -; shlq $4, %rdi, %rdi -; orq %rdi, %r10, %rdi +; shlq $4, %rax, %rax +; orq %rax, %r10, %rax ; movabsq $71777214294589695, %rcx -; movq %rdi, %rdx +; movq %rax, %rdx ; andq %rdx, %rcx, %rdx -; shrq $8, %rdi, %rdi -; andq %rdi, %rcx, %rdi +; shrq $8, %rax, %rax +; andq %rax, %rcx, %rax ; shlq $8, %rdx, %rdx -; orq %rdx, %rdi, %rdx +; orq %rdx, %rax, %rdx ; movabsq $281470681808895, %r10 ; movq %rdx, %r9 ; andq %r9, %r10, %r9 @@ -615,11 +574,53 @@ block0(v0: i128): ; shlq $16, %r9, %r9 ; orq %r9, %rdx, %r9 ; movabsq $4294967295, %rsi -; movq %r9, %rdx -; andq %rdx, %rsi, %rdx +; movq %r9, %rax +; andq %rax, %rsi, %rax ; shrq $32, %r9, %r9 +; shlq $32, %rax, %rax +; orq %rax, %r9, %rax +; movabsq $6148914691236517205, %rdx +; movq %rdi, %rcx +; andq %rcx, %rdx, %rcx +; movq %rdi, %r9 +; shrq $1, %r9, %r9 +; andq %r9, %rdx, %r9 +; shlq $1, %rcx, %rcx +; orq %rcx, %r9, %rcx +; movabsq $3689348814741910323, %rdx +; movq %rcx, %r8 +; andq %r8, %rdx, %r8 +; shrq $2, %rcx, %rcx +; andq %rcx, %rdx, %rcx +; shlq $2, %r8, %r8 +; orq %r8, %rcx, %r8 +; movabsq $1085102592571150095, %r10 +; movq %r8, %r11 +; andq %r11, %r10, %r11 +; shrq $4, %r8, %r8 +; andq %r8, %r10, %r8 +; shlq $4, %r11, %r11 +; orq %r11, %r8, %r11 +; movabsq $71777214294589695, %rdi +; movq %r11, %rcx +; andq %rcx, %rdi, %rcx +; shrq $8, %r11, %r11 +; andq %r11, %rdi, %r11 +; shlq $8, %rcx, %rcx +; orq %rcx, %r11, %rcx +; movabsq $281470681808895, %rdx +; movq %rcx, %r8 +; andq %r8, %rdx, %r8 +; shrq $16, %rcx, %rcx +; andq %rcx, %rdx, %rcx +; shlq $16, %r8, %r8 +; orq %r8, %rcx, %r8 +; movabsq $4294967295, %r10 +; movq %r8, %rdx +; andq %rdx, %r10, %rdx +; shrq $32, %r8, %r8 ; shlq $32, %rdx, %rdx -; orq %rdx, %r9, %rdx +; orq %rdx, %r8, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -678,24 +679,24 @@ block2(v8: i128): ; movq %rsp, %rbp ; block0: ; xorq %rax, %rax, %rax -; xorq %r11, %r11, %r11 +; xorq %r9, %r9, %r9 ; testb %dl, %dl ; jnz label1; j label2 ; block1: -; movl $1, %r10d -; xorq %rsi, %rsi, %rsi -; addq %rax, %r10, %rax -; movq %r11, %rdx -; adcq %rdx, %rsi, %rdx +; movl $1, %r8d +; xorq %r10, %r10, %r10 +; addq %rax, %r8, %rax +; movq %r9, %rdx +; adcq %rdx, %r10, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret ; block2: -; movq %r11, %rdx -; movl $2, %ecx -; xorq %r8, %r8, %r8 -; addq %rax, %rcx, %rax -; adcq %rdx, %r8, %rdx +; movq %r9, %rdx +; movl $2, %r9d +; xorq %r11, %r11, %r11 +; addq %rax, %r9, %rax +; adcq %rdx, %r11, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -715,40 +716,33 @@ block0(v0: i128, v1: i128, v2: i64, v3: i128, v4: i128, v5: i128): ; pushq %rbp ; movq %rsp, %rbp ; subq %rsp, $32, %rsp -; movq %rbx, 0(%rsp) -; movq %r12, 8(%rsp) -; movq %r13, 16(%rsp) +; movq %r13, 0(%rsp) +; movq %r14, 8(%rsp) +; movq %r15, 16(%rsp) ; block0: -; movq %r9, %r13 -; movq %rcx, %rax -; movq %r8, %rcx -; movq %rax, %r8 -; movq 16(%rbp), %rbx +; movq %rcx, %r15 +; movq %rdx, %rcx +; movq 16(%rbp), %r14 ; movq 24(%rbp), %rax -; movq 32(%rbp), %r9 -; movq %r9, %r12 -; movq 40(%rbp), %r10 -; movq 48(%rbp), %r11 -; movq %rdi, %r9 -; addq %r9, %rdx, %r9 -; movq %r8, %rdi -; movq %rsi, %r8 -; adcq %r8, %rdi, %r8 -; xorq %rdx, %rdx, %rdx -; movq %rcx, %rsi -; movq %r13, %rdi +; movq 32(%rbp), %rdx +; movq 40(%rbp), %r11 +; movq 48(%rbp), %r10 +; addq %rdi, %rcx, %rdi +; movq %rsi, %rcx +; adcq %rcx, %r15, %rcx +; xorq %r13, %r13, %r13 +; movq %r9, %rsi +; addq %rsi, %r8, %rsi +; adcq %r14, %r13, %r14 +; addq %rax, %r11, %rax +; adcq %rdx, %r10, %rdx ; addq %rdi, %rsi, %rdi -; adcq %rbx, %rdx, %rbx -; addq %rax, %r10, %rax -; movq %r12, %rdx -; adcq %rdx, %r11, %rdx -; addq %r9, %rdi, %r9 -; adcq %r8, %rbx, %r8 -; addq %rax, %r9, %rax -; adcq %rdx, %r8, %rdx -; movq 0(%rsp), %rbx -; movq 8(%rsp), %r12 -; movq 16(%rsp), %r13 +; adcq %rcx, %r14, %rcx +; addq %rax, %rdi, %rax +; adcq %rdx, %rcx, %rdx +; movq 0(%rsp), %r13 +; movq 8(%rsp), %r14 +; movq 16(%rsp), %r15 ; addq %rsp, $32, %rsp ; movq %rbp, %rsp ; popq %rbp @@ -762,41 +756,18 @@ block0(v0: i128): ; pushq %rbp ; movq %rsp, %rbp -; subq %rsp, $48, %rsp -; movq %rbx, 0(%rsp) -; movq %r12, 8(%rsp) -; movq %r13, 16(%rsp) -; movq %r14, 24(%rsp) -; movq %r15, 32(%rsp) ; block0: -; movq %rdx, %r12 +; movq %rdi, 0(%rdx) +; movq %rsi, 8(%rdx) +; movq %rdi, 16(%rdx) +; movq %rsi, 24(%rdx) +; movq %rdi, 32(%rdx) +; movq %rdi, 40(%rdx) +; movq %rsi, 48(%rdx) +; movq %rdi, 56(%rdx) ; movq %rdi, %rax +; movq %rsi, 64(%rdx) ; movq %rsi, %rdx -; movq %rdi, %r14 -; movq %rsi, %rbx -; movq %rdi, %r13 -; movq %rsi, %r15 -; movq %rdi, %r11 -; movq %rdi, %r10 -; movq %rsi, %rcx -; movq %rdi, %r8 -; movq %rsi, %r9 -; movq %r12, %rdi -; movq %r14, 0(%rdi) -; movq %rbx, 8(%rdi) -; movq %r13, 16(%rdi) -; movq %r15, 24(%rdi) -; movq %r11, 32(%rdi) -; movq %r10, 40(%rdi) -; movq %rcx, 48(%rdi) -; movq %r8, 56(%rdi) -; movq %r9, 64(%rdi) -; movq 0(%rsp), %rbx -; movq 8(%rsp), %r12 -; movq 16(%rsp), %r13 -; movq 24(%rsp), %r14 -; movq 32(%rsp), %r15 -; addq %rsp, $48, %rsp ; movq %rbp, %rsp ; popq %rbp ; ret @@ -811,22 +782,22 @@ block0(v0: i128, v1: i128): ; pushq %rbp ; movq %rsp, %rbp ; subq %rsp, $16, %rsp -; movq %r12, 0(%rsp) +; movq %r13, 0(%rsp) ; block0: -; movq %r8, %r12 +; movq %r8, %r13 ; subq %rsp, $16, %rsp ; virtual_sp_offset_adjust 16 ; lea 0(%rsp), %r8 -; load_ext_name %g+0, %rax -; call *%rax -; movq 0(%rsp), %r11 -; movq 8(%rsp), %rdi +; load_ext_name %g+0, %r9 +; call *%r9 +; movq 0(%rsp), %r8 +; movq 8(%rsp), %r9 ; addq %rsp, $16, %rsp ; virtual_sp_offset_adjust -16 -; movq %r12, %r8 -; movq %r11, 0(%r8) -; movq %rdi, 8(%r8) -; movq 0(%rsp), %r12 +; movq %r13, %rcx +; movq %r8, 0(%rcx) +; movq %r9, 8(%rcx) +; movq 0(%rsp), %r13 ; addq %rsp, $16, %rsp ; movq %rbp, %rsp ; popq %rbp @@ -841,19 +812,20 @@ block0(v0: i128): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movabsq $-1, %r8 -; bsrq %rsi, %r11 -; cmovzq %r8, %r11, %r11 -; movl $63, %ecx -; subq %rcx, %r11, %rcx -; movabsq $-1, %r9 -; bsrq %rdi, %rsi -; cmovzq %r9, %rsi, %rsi +; movq %rdi, %r8 +; movabsq $-1, %rcx +; bsrq %rsi, %r9 +; cmovzq %rcx, %r9, %r9 +; movl $63, %edi +; subq %rdi, %r9, %rdi +; movabsq $-1, %rdx +; bsrq %r8, %r10 +; cmovzq %rdx, %r10, %r10 ; movl $63, %eax -; subq %rax, %rsi, %rax +; subq %rax, %r10, %rax ; addq %rax, $64, %rax -; cmpq $64, %rcx -; cmovnzq %rcx, %rax, %rax +; cmpq $64, %rdi +; cmovnzq %rdi, %rax, %rax ; xorq %rdx, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp @@ -868,15 +840,15 @@ block0(v0: i128): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl $64, %r8d -; bsfq %rdi, %rax -; cmovzq %r8, %rax, %rax ; movl $64, %ecx -; bsfq %rsi, %r9 -; cmovzq %rcx, %r9, %r9 -; addq %r9, $64, %r9 +; bsfq %rdi, %rax +; cmovzq %rcx, %rax, %rax +; movl $64, %edi +; bsfq %rsi, %rdx +; cmovzq %rdi, %rdx, %rdx +; addq %rdx, $64, %rdx ; cmpq $64, %rax -; cmovzq %r9, %rax, %rax +; cmovzq %rdx, %rax, %rax ; xorq %rdx, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp @@ -911,21 +883,21 @@ block0(v0: i128, v1: i128): ; movq %rdx, %rcx ; movq %rdi, %rdx ; shlq %cl, %rdx, %rdx -; movq %rsi, %r8 -; shlq %cl, %r8, %r8 -; movq %rcx, %rsi +; movq %rsi, %r11 +; shlq %cl, %r11, %r11 +; movq %rcx, %r10 ; movl $64, %ecx -; movq %rsi, %r9 -; subq %rcx, %r9, %rcx -; movq %rdi, %rsi -; shrq %cl, %rsi, %rsi +; movq %r10, %r8 +; subq %rcx, %r8, %rcx +; movq %rdi, %r10 +; shrq %cl, %r10, %r10 ; xorq %rax, %rax, %rax -; testq $127, %r9 -; cmovzq %rax, %rsi, %rsi -; orq %rsi, %r8, %rsi -; testq $64, %r9 +; testq $127, %r8 +; cmovzq %rax, %r10, %r10 +; orq %r10, %r11, %r10 +; testq $64, %r8 ; cmovzq %rdx, %rax, %rax -; cmovzq %rsi, %rdx, %rdx +; cmovzq %r10, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -940,24 +912,24 @@ block0(v0: i128, v1: i128): ; movq %rsp, %rbp ; block0: ; movq %rdx, %rcx -; movq %rdi, %r10 -; shrq %cl, %r10, %r10 -; movq %rsi, %r8 +; movq %rdi, %r8 ; shrq %cl, %r8, %r8 +; movq %rsi, %r10 +; shrq %cl, %r10, %r10 ; movl $64, %ecx -; movq %rdx, %r9 -; subq %rcx, %r9, %rcx -; movq %rsi, %rdi -; shlq %cl, %rdi, %rdi -; xorq %r11, %r11, %r11 -; testq $127, %r9 -; cmovzq %r11, %rdi, %rdi -; orq %rdi, %r10, %rdi +; movq %rdx, %rax +; subq %rcx, %rax, %rcx +; movq %rsi, %r11 +; shlq %cl, %r11, %r11 +; xorq %r9, %r9, %r9 +; testq $127, %rax +; cmovzq %r9, %r11, %r11 +; orq %r11, %r8, %r11 ; xorq %rdx, %rdx, %rdx -; testq $64, %r9 -; movq %r8, %rax -; cmovzq %rdi, %rax, %rax -; cmovzq %r8, %rdx, %rdx +; testq $64, %rax +; movq %r10, %rax +; cmovzq %r11, %rax, %rax +; cmovzq %r10, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -974,23 +946,23 @@ block0(v0: i128, v1: i128): ; movq %rdx, %rcx ; movq %rdi, %r8 ; shrq %cl, %r8, %r8 -; movq %rsi, %rdi -; sarq %cl, %rdi, %rdi +; movq %rsi, %r10 +; sarq %cl, %r10, %r10 ; movl $64, %ecx -; movq %rdx, %r9 -; subq %rcx, %r9, %rcx -; movq %rsi, %r11 -; shlq %cl, %r11, %r11 -; xorq %rax, %rax, %rax -; testq $127, %r9 -; cmovzq %rax, %r11, %r11 -; orq %r8, %r11, %r8 +; movq %rdx, %rax +; subq %rcx, %rax, %rcx +; movq %rsi, %r9 +; shlq %cl, %r9, %r9 +; xorq %r11, %r11, %r11 +; testq $127, %rax +; cmovzq %r11, %r9, %r9 +; orq %r8, %r9, %r8 ; movq %rsi, %rdx ; sarq $63, %rdx, %rdx -; testq $64, %r9 -; movq %rdi, %rax +; testq $64, %rax +; movq %r10, %rax ; cmovzq %r8, %rax, %rax -; cmovzq %rdi, %rdx, %rdx +; cmovzq %r10, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -1007,42 +979,44 @@ block0(v0: i128, v1: i128): ; movq %rdx, %rcx ; movq %rdi, %rdx ; shlq %cl, %rdx, %rdx -; movq %rsi, %r9 -; shlq %cl, %r9, %r9 -; movq %rcx, %r10 +; movq %rsi, %r11 +; shlq %cl, %r11, %r11 +; movq %rcx, %r8 ; movl $64, %ecx -; subq %rcx, %r10, %rcx +; subq %rcx, %r8, %rcx +; movq %rdi, %r10 +; shrq %cl, %r10, %r10 +; xorq %rax, %rax, %rax +; testq $127, %r8 +; cmovzq %rax, %r10, %r10 +; orq %r10, %r11, %r10 +; testq $64, %r8 +; cmovzq %rdx, %rax, %rax +; cmovzq %r10, %rdx, %rdx +; movl $128, %ecx +; movq %r8, %r11 +; subq %rcx, %r11, %rcx ; movq %rdi, %r8 ; shrq %cl, %r8, %r8 -; xorq %rax, %rax, %rax -; testq $127, %r10 -; cmovzq %rax, %r8, %r8 -; orq %r8, %r9, %r8 -; testq $64, %r10 -; cmovzq %rdx, %rax, %rax -; cmovzq %r8, %rdx, %rdx -; movl $128, %ecx -; movq %r10, %r8 -; subq %rcx, %r8, %rcx -; movq %rdi, %r9 +; movq %rsi, %r9 ; shrq %cl, %r9, %r9 -; movq %rsi, %r11 -; shrq %cl, %r11, %r11 -; movq %rcx, %rdi +; movq %rcx, %r10 ; movl $64, %ecx +; movq %r10, %rdi ; subq %rcx, %rdi, %rcx -; shlq %cl, %rsi, %rsi -; xorq %r10, %r10, %r10 +; movq %rsi, %r10 +; shlq %cl, %r10, %r10 +; xorq %r11, %r11, %r11 ; testq $127, %rdi -; cmovzq %r10, %rsi, %rsi -; orq %rsi, %r9, %rsi -; xorq %r10, %r10, %r10 -; testq $64, %rdi -; movq %r11, %rdi -; cmovzq %rsi, %rdi, %rdi ; cmovzq %r11, %r10, %r10 -; orq %rax, %rdi, %rax -; orq %rdx, %r10, %rdx +; orq %r10, %r8, %r10 +; xorq %r8, %r8, %r8 +; testq $64, %rdi +; movq %r9, %r11 +; cmovzq %r10, %r11, %r11 +; cmovzq %r9, %r8, %r8 +; orq %rax, %r11, %rax +; orq %rdx, %r8, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -1057,46 +1031,46 @@ block0(v0: i128, v1: i128): ; movq %rsp, %rbp ; block0: ; movq %rdx, %rcx -; movq %rdi, %r10 -; shrq %cl, %r10, %r10 -; movq %rsi, %r8 +; movq %rdi, %r8 ; shrq %cl, %r8, %r8 -; movq %rcx, %r11 +; movq %rsi, %r10 +; shrq %cl, %r10, %r10 +; movq %rcx, %r9 ; movl $64, %ecx -; movq %r11, %rax +; movq %r9, %rax ; subq %rcx, %rax, %rcx -; movq %rsi, %r9 -; shlq %cl, %r9, %r9 -; xorq %r11, %r11, %r11 +; movq %rsi, %r11 +; shlq %cl, %r11, %r11 +; xorq %r9, %r9, %r9 ; testq $127, %rax -; cmovzq %r11, %r9, %r9 -; orq %r9, %r10, %r9 +; cmovzq %r9, %r11, %r11 +; orq %r11, %r8, %r11 ; xorq %rdx, %rdx, %rdx ; testq $64, %rax -; movq %rax, %r11 -; movq %r8, %rax -; cmovzq %r9, %rax, %rax -; cmovzq %r8, %rdx, %rdx +; movq %rax, %r9 +; movq %r10, %rax +; cmovzq %r11, %rax, %rax +; cmovzq %r10, %rdx, %rdx ; movl $128, %ecx -; movq %r11, %r8 +; movq %r9, %r8 ; subq %rcx, %r8, %rcx -; movq %rdi, %r11 -; shlq %cl, %r11, %r11 -; movq %rsi, %r9 +; movq %rdi, %r9 ; shlq %cl, %r9, %r9 -; movq %rcx, %rsi +; shlq %cl, %rsi, %rsi +; movq %rcx, %r10 ; movl $64, %ecx -; subq %rcx, %rsi, %rcx -; shrq %cl, %rdi, %rdi -; xorq %r8, %r8, %r8 -; testq $127, %rsi -; cmovzq %r8, %rdi, %rdi -; orq %rdi, %r9, %rdi -; testq $64, %rsi -; cmovzq %r11, %r8, %r8 +; subq %rcx, %r10, %rcx +; movq %rdi, %r11 +; shrq %cl, %r11, %r11 +; xorq %rdi, %rdi, %rdi +; testq $127, %r10 ; cmovzq %rdi, %r11, %r11 -; orq %rax, %r8, %rax -; orq %rdx, %r11, %rdx +; orq %r11, %rsi, %r11 +; testq $64, %r10 +; cmovzq %r9, %rdi, %rdi +; cmovzq %r11, %r9, %r9 +; orq %rax, %rdi, %rax +; orq %rdx, %r9, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/ishl.clif b/cranelift/filetests/filetests/isa/x64/ishl.clif index e171cf9774..f162592975 100644 --- a/cranelift/filetests/filetests/isa/x64/ishl.clif +++ b/cranelift/filetests/filetests/isa/x64/ishl.clif @@ -20,21 +20,21 @@ block0(v0: i128, v1: i8): ; movzbq %dl, %rcx ; movq %rdi, %rdx ; shlq %cl, %rdx, %rdx -; movq %rsi, %r8 -; shlq %cl, %r8, %r8 -; movq %rcx, %r11 +; movq %rsi, %r11 +; shlq %cl, %r11, %r11 +; movq %rcx, %r9 ; movl $64, %ecx -; movq %r11, %r9 -; subq %rcx, %r9, %rcx -; movq %rdi, %rsi -; shrq %cl, %rsi, %rsi +; movq %r9, %r8 +; subq %rcx, %r8, %rcx +; movq %rdi, %r10 +; shrq %cl, %r10, %r10 ; xorq %rax, %rax, %rax -; testq $127, %r9 -; cmovzq %rax, %rsi, %rsi -; orq %rsi, %r8, %rsi -; testq $64, %r9 +; testq $127, %r8 +; cmovzq %rax, %r10, %r10 +; orq %r10, %r11, %r10 +; testq $64, %r8 ; cmovzq %rdx, %rax, %rax -; cmovzq %rsi, %rdx, %rdx +; cmovzq %r10, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -51,20 +51,21 @@ block0(v0: i128, v1: i64): ; movq %rdx, %rcx ; movq %rdi, %rdx ; shlq %cl, %rdx, %rdx -; shlq %cl, %rsi, %rsi -; movq %rcx, %r11 +; movq %rsi, %r10 +; shlq %cl, %r10, %r10 +; movq %rcx, %r9 ; movl $64, %ecx -; movq %r11, %r8 -; subq %rcx, %r8, %rcx -; movq %rdi, %r11 -; shrq %cl, %r11, %r11 +; movq %r9, %rsi +; subq %rcx, %rsi, %rcx +; movq %rdi, %r9 +; shrq %cl, %r9, %r9 ; xorq %rax, %rax, %rax -; testq $127, %r8 -; cmovzq %rax, %r11, %r11 -; orq %r11, %rsi, %r11 -; testq $64, %r8 +; testq $127, %rsi +; cmovzq %rax, %r9, %r9 +; orq %r9, %r10, %r9 +; testq $64, %rsi ; cmovzq %rdx, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -81,20 +82,21 @@ block0(v0: i128, v1: i32): ; movq %rdx, %rcx ; movq %rdi, %rdx ; shlq %cl, %rdx, %rdx -; shlq %cl, %rsi, %rsi -; movq %rcx, %r11 +; movq %rsi, %r10 +; shlq %cl, %r10, %r10 +; movq %rcx, %r9 ; movl $64, %ecx -; movq %r11, %r8 -; subq %rcx, %r8, %rcx -; movq %rdi, %r11 -; shrq %cl, %r11, %r11 +; movq %r9, %rsi +; subq %rcx, %rsi, %rcx +; movq %rdi, %r9 +; shrq %cl, %r9, %r9 ; xorq %rax, %rax, %rax -; testq $127, %r8 -; cmovzq %rax, %r11, %r11 -; orq %r11, %rsi, %r11 -; testq $64, %r8 +; testq $127, %rsi +; cmovzq %rax, %r9, %r9 +; orq %r9, %r10, %r9 +; testq $64, %rsi ; cmovzq %rdx, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -111,20 +113,21 @@ block0(v0: i128, v1: i16): ; movq %rdx, %rcx ; movq %rdi, %rdx ; shlq %cl, %rdx, %rdx -; shlq %cl, %rsi, %rsi -; movq %rcx, %r11 +; movq %rsi, %r10 +; shlq %cl, %r10, %r10 +; movq %rcx, %r9 ; movl $64, %ecx -; movq %r11, %r8 -; subq %rcx, %r8, %rcx -; movq %rdi, %r11 -; shrq %cl, %r11, %r11 +; movq %r9, %rsi +; subq %rcx, %rsi, %rcx +; movq %rdi, %r9 +; shrq %cl, %r9, %r9 ; xorq %rax, %rax, %rax -; testq $127, %r8 -; cmovzq %rax, %r11, %r11 -; orq %r11, %rsi, %r11 -; testq $64, %r8 +; testq $127, %rsi +; cmovzq %rax, %r9, %r9 +; orq %r9, %r10, %r9 +; testq $64, %rsi ; cmovzq %rdx, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -141,20 +144,21 @@ block0(v0: i128, v1: i8): ; movq %rdx, %rcx ; movq %rdi, %rdx ; shlq %cl, %rdx, %rdx -; shlq %cl, %rsi, %rsi -; movq %rcx, %r11 +; movq %rsi, %r10 +; shlq %cl, %r10, %r10 +; movq %rcx, %r9 ; movl $64, %ecx -; movq %r11, %r8 -; subq %rcx, %r8, %rcx -; movq %rdi, %r11 -; shrq %cl, %r11, %r11 +; movq %r9, %rsi +; subq %rcx, %rsi, %rcx +; movq %rdi, %r9 +; shrq %cl, %r9, %r9 ; xorq %rax, %rax, %rax -; testq $127, %r8 -; cmovzq %rax, %r11, %r11 -; orq %r11, %rsi, %r11 -; testq $64, %r8 +; testq $127, %rsi +; cmovzq %rax, %r9, %r9 +; orq %r9, %r10, %r9 +; testq $64, %rsi ; cmovzq %rdx, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/load-op.clif b/cranelift/filetests/filetests/isa/x64/load-op.clif index 69a7d4feaa..030a0f1881 100644 --- a/cranelift/filetests/filetests/isa/x64/load-op.clif +++ b/cranelift/filetests/filetests/isa/x64/load-op.clif @@ -93,11 +93,11 @@ block0(v0: i64, v1: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq 0(%rdi), %r9 -; movq %r9, %r10 -; addq %r10, %rdi, %r10 -; movq %r10, 0(%rsi) -; movq 0(%r9,%rdi,1), %rax +; movq 0(%rdi), %r8 +; movq %r8, %r9 +; addq %r9, %rdi, %r9 +; movq %r9, 0(%rsi) +; movq 0(%r8,%rdi,1), %rax ; movq %rbp, %rsp ; popq %rbp ; ret @@ -134,8 +134,8 @@ block0(v0: i64): ; movq %rsp, %rbp ; block0: ; cmpq 0(%rdi), %rdi -; setz %r8b -; movzbq %r8b, %rax +; setz %dl +; movzbq %dl, %rax ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/narrowing.clif b/cranelift/filetests/filetests/isa/x64/narrowing.clif index 7ca0306967..62646deba8 100644 --- a/cranelift/filetests/filetests/isa/x64/narrowing.clif +++ b/cranelift/filetests/filetests/isa/x64/narrowing.clif @@ -40,13 +40,13 @@ block0(v0: f64x2): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm5 -; cmppd $0, %xmm5, %xmm0, %xmm5 -; movupd const(0), %xmm6 -; andps %xmm5, %xmm6, %xmm5 -; movdqa %xmm0, %xmm9 -; minpd %xmm9, %xmm5, %xmm9 -; cvttpd2dq %xmm9, %xmm0 +; movdqa %xmm0, %xmm4 +; cmppd $0, %xmm4, %xmm0, %xmm4 +; movupd const(0), %xmm5 +; andps %xmm4, %xmm5, %xmm4 +; movdqa %xmm0, %xmm8 +; minpd %xmm8, %xmm4, %xmm8 +; cvttpd2dq %xmm8, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/nearest-libcall.clif b/cranelift/filetests/filetests/isa/x64/nearest-libcall.clif index 53df3468aa..f4c656ab6b 100644 --- a/cranelift/filetests/filetests/isa/x64/nearest-libcall.clif +++ b/cranelift/filetests/filetests/isa/x64/nearest-libcall.clif @@ -10,8 +10,8 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; load_ext_name %NearestF32+0, %rdx -; call *%rdx +; load_ext_name %NearestF32+0, %rcx +; call *%rcx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -25,8 +25,8 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; load_ext_name %NearestF64+0, %rdx -; call *%rdx +; load_ext_name %NearestF64+0, %rcx +; call *%rcx ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/popcnt.clif b/cranelift/filetests/filetests/isa/x64/popcnt.clif index 4230200d15..491be3077b 100644 --- a/cranelift/filetests/filetests/isa/x64/popcnt.clif +++ b/cranelift/filetests/filetests/isa/x64/popcnt.clif @@ -10,25 +10,25 @@ block0(v0: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq %rdi, %rax -; shrq $1, %rax, %rax -; movabsq $8608480567731124087, %r8 -; andq %rax, %r8, %rax -; movq %rdi, %r9 -; subq %r9, %rax, %r9 -; shrq $1, %rax, %rax -; andq %rax, %r8, %rax -; subq %r9, %rax, %r9 -; shrq $1, %rax, %rax -; andq %rax, %r8, %rax -; subq %r9, %rax, %r9 -; movq %r9, %rax +; movq %rdi, %rcx +; shrq $1, %rdi, %rdi +; movq %rcx, %r8 +; movabsq $8608480567731124087, %rdx +; andq %rdi, %rdx, %rdi +; subq %r8, %rdi, %r8 +; shrq $1, %rdi, %rdi +; andq %rdi, %rdx, %rdi +; subq %r8, %rdi, %r8 +; shrq $1, %rdi, %rdi +; andq %rdi, %rdx, %rdi +; subq %r8, %rdi, %r8 +; movq %r8, %rax ; shrq $4, %rax, %rax -; addq %rax, %r9, %rax -; movabsq $1085102592571150095, %rsi -; andq %rax, %rsi, %rax -; movabsq $72340172838076673, %rdx -; imulq %rax, %rdx, %rax +; addq %rax, %r8, %rax +; movabsq $1085102592571150095, %r11 +; andq %rax, %r11, %rax +; movabsq $72340172838076673, %rcx +; imulq %rax, %rcx, %rax ; shrq $56, %rax, %rax ; movq %rbp, %rsp ; popq %rbp @@ -44,25 +44,25 @@ block0(v0: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movq 0(%rdi), %rcx -; movq %rcx, %rdx -; shrq $1, %rdx, %rdx -; movabsq $8608480567731124087, %r9 -; andq %rdx, %r9, %rdx -; subq %rcx, %rdx, %rcx -; shrq $1, %rdx, %rdx -; andq %rdx, %r9, %rdx -; subq %rcx, %rdx, %rcx -; shrq $1, %rdx, %rdx -; andq %rdx, %r9, %rdx -; subq %rcx, %rdx, %rcx -; movq %rcx, %rax +; movq 0(%rdi), %rdx +; movq %rdx, %rcx +; shrq $1, %rcx, %rcx +; movabsq $8608480567731124087, %r8 +; andq %rcx, %r8, %rcx +; subq %rdx, %rcx, %rdx +; shrq $1, %rcx, %rcx +; andq %rcx, %r8, %rcx +; subq %rdx, %rcx, %rdx +; shrq $1, %rcx, %rcx +; andq %rcx, %r8, %rcx +; subq %rdx, %rcx, %rdx +; movq %rdx, %rax ; shrq $4, %rax, %rax -; addq %rax, %rcx, %rax -; movabsq $1085102592571150095, %rdi -; andq %rax, %rdi, %rax -; movabsq $72340172838076673, %r8 -; imulq %rax, %r8, %rax +; addq %rax, %rdx, %rax +; movabsq $1085102592571150095, %rsi +; andq %rax, %rsi, %rax +; movabsq $72340172838076673, %rdx +; imulq %rax, %rdx, %rax ; shrq $56, %rax, %rax ; movq %rbp, %rsp ; popq %rbp @@ -78,20 +78,20 @@ block0(v0: i32): ; movq %rsp, %rbp ; block0: ; movq %rdi, %rax -; shrl $1, %eax, %eax -; movl $2004318071, %r8d -; andl %eax, %r8d, %eax -; movq %rdi, %r9 -; subl %r9d, %eax, %r9d -; shrl $1, %eax, %eax -; andl %eax, %r8d, %eax -; subl %r9d, %eax, %r9d -; shrl $1, %eax, %eax -; andl %eax, %r8d, %eax -; subl %r9d, %eax, %r9d -; movq %r9, %rax +; shrl $1, %edi, %edi +; movl $2004318071, %edx +; andl %edi, %edx, %edi +; movq %rax, %r8 +; subl %r8d, %edi, %r8d +; shrl $1, %edi, %edi +; andl %edi, %edx, %edi +; subl %r8d, %edi, %r8d +; shrl $1, %edi, %edi +; andl %edi, %edx, %edi +; subl %r8d, %edi, %r8d +; movq %r8, %rax ; shrl $4, %eax, %eax -; addl %eax, %r9d, %eax +; addl %eax, %r8d, %eax ; andl %eax, $252645135, %eax ; imull %eax, $16843009, %eax ; shrl $24, %eax, %eax @@ -109,21 +109,21 @@ block0(v0: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl 0(%rdi), %ecx -; movq %rcx, %rdx -; shrl $1, %edx, %edx -; movl $2004318071, %r9d -; andl %edx, %r9d, %edx -; subl %ecx, %edx, %ecx -; shrl $1, %edx, %edx -; andl %edx, %r9d, %edx -; subl %ecx, %edx, %ecx -; shrl $1, %edx, %edx -; andl %edx, %r9d, %edx -; subl %ecx, %edx, %ecx -; movq %rcx, %rax +; movl 0(%rdi), %edx +; movq %rdx, %rcx +; shrl $1, %ecx, %ecx +; movl $2004318071, %r8d +; andl %ecx, %r8d, %ecx +; subl %edx, %ecx, %edx +; shrl $1, %ecx, %ecx +; andl %ecx, %r8d, %ecx +; subl %edx, %ecx, %edx +; shrl $1, %ecx, %ecx +; andl %ecx, %r8d, %ecx +; subl %edx, %ecx, %edx +; movq %rdx, %rax ; shrl $4, %eax, %eax -; addl %eax, %ecx, %eax +; addl %eax, %edx, %eax ; andl %eax, $252645135, %eax ; imull %eax, $16843009, %eax ; shrl $24, %eax, %eax diff --git a/cranelift/filetests/filetests/isa/x64/select-i128.clif b/cranelift/filetests/filetests/isa/x64/select-i128.clif index 14dd0a352f..33d1a371ee 100644 --- a/cranelift/filetests/filetests/isa/x64/select-i128.clif +++ b/cranelift/filetests/filetests/isa/x64/select-i128.clif @@ -16,9 +16,9 @@ block0(v0: i32, v1: i128, v2: i128): ; cmpl $42, %edi ; movq %rcx, %rax ; cmovzq %rsi, %rax, %rax -; movq %r8, %rcx -; cmovzq %rdx, %rcx, %rcx -; movq %rcx, %rdx +; movq %rdx, %rdi +; movq %r8, %rdx +; cmovzq %rdi, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/shuffle-avx512.clif b/cranelift/filetests/filetests/isa/x64/shuffle-avx512.clif index 153943dde4..c596618c7c 100644 --- a/cranelift/filetests/filetests/isa/x64/shuffle-avx512.clif +++ b/cranelift/filetests/filetests/isa/x64/shuffle-avx512.clif @@ -12,10 +12,10 @@ block0(v0: i8x16, v1: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm6 +; movdqa %xmm0, %xmm5 ; movdqu const(0), %xmm0 -; movdqa %xmm6, %xmm7 -; vpermi2b %xmm1, %xmm7, %xmm0, %xmm0 +; movdqa %xmm5, %xmm6 +; vpermi2b %xmm1, %xmm6, %xmm0, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -32,12 +32,12 @@ block0(v0: i8x16, v1: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm8 +; movdqa %xmm0, %xmm7 ; movdqu const(1), %xmm0 -; movdqu const(0), %xmm7 -; movdqa %xmm8, %xmm10 -; vpermi2b %xmm1, %xmm10, %xmm7, %xmm7 -; andps %xmm0, %xmm7, %xmm0 +; movdqu const(0), %xmm6 +; movdqa %xmm7, %xmm9 +; vpermi2b %xmm1, %xmm9, %xmm6, %xmm6 +; andps %xmm0, %xmm6, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -51,10 +51,10 @@ block0(v0: i8x16, v1: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm6 +; movdqa %xmm0, %xmm5 ; movdqu const(0), %xmm0 -; movdqa %xmm6, %xmm7 -; vpermi2b %xmm1, %xmm7, %xmm0, %xmm0 +; movdqa %xmm5, %xmm6 +; vpermi2b %xmm1, %xmm6, %xmm0, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/simd-bitselect.clif b/cranelift/filetests/filetests/isa/x64/simd-bitselect.clif index 11c4907c23..3a56d97a2f 100644 --- a/cranelift/filetests/filetests/isa/x64/simd-bitselect.clif +++ b/cranelift/filetests/filetests/isa/x64/simd-bitselect.clif @@ -12,13 +12,13 @@ block0(v0: i8x16, v1: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm5 -; pcmpeqb %xmm5, %xmm1, %xmm5 -; movdqa %xmm0, %xmm8 +; movdqa %xmm0, %xmm4 +; pcmpeqb %xmm4, %xmm1, %xmm4 +; movdqa %xmm0, %xmm7 +; movdqa %xmm4, %xmm0 +; movdqa %xmm1, %xmm5 +; pblendvb %xmm5, %xmm7, %xmm5 ; movdqa %xmm5, %xmm0 -; movdqa %xmm1, %xmm6 -; pblendvb %xmm6, %xmm8, %xmm6 -; movdqa %xmm6, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -34,9 +34,9 @@ block0(v0: f32x4, v1: f32x4, v2: i32x4, v3: i32x4): ; movq %rsp, %rbp ; block0: ; cmpps $0, %xmm0, %xmm1, %xmm0 -; movdqa %xmm3, %xmm8 -; pblendvb %xmm8, %xmm2, %xmm8 -; movdqa %xmm8, %xmm0 +; movdqa %xmm3, %xmm7 +; pblendvb %xmm7, %xmm2, %xmm7 +; movdqa %xmm7, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -51,11 +51,11 @@ block0(v0: i8x16, v1: i8x16, v2: i32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm5 -; pand %xmm5, %xmm2, %xmm5 +; movdqa %xmm0, %xmm4 +; pand %xmm4, %xmm2, %xmm4 ; movdqa %xmm2, %xmm0 ; pandn %xmm0, %xmm1, %xmm0 -; por %xmm0, %xmm5, %xmm0 +; por %xmm0, %xmm4, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -70,12 +70,12 @@ block0(v0: i8x16, v1: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm6 +; movdqa %xmm0, %xmm5 ; movdqu const(0), %xmm0 -; movdqa %xmm6, %xmm8 -; movdqa %xmm1, %xmm6 -; pblendvb %xmm6, %xmm8, %xmm6 -; movdqa %xmm6, %xmm0 +; movdqa %xmm5, %xmm7 +; movdqa %xmm1, %xmm5 +; pblendvb %xmm5, %xmm7, %xmm5 +; movdqa %xmm5, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -90,12 +90,12 @@ block0(v0: i16x8, v1: i16x8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm6 +; movdqa %xmm0, %xmm5 ; movdqu const(0), %xmm0 -; movdqa %xmm6, %xmm8 -; movdqa %xmm1, %xmm6 -; pblendvb %xmm6, %xmm8, %xmm6 -; movdqa %xmm6, %xmm0 +; movdqa %xmm5, %xmm7 +; movdqa %xmm1, %xmm5 +; pblendvb %xmm5, %xmm7, %xmm5 +; movdqa %xmm5, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -110,13 +110,12 @@ block0(v0: i8x16, v1: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqu const(0), %xmm6 -; movdqa %xmm6, %xmm9 -; movdqa %xmm0, %xmm5 -; pand %xmm5, %xmm9, %xmm5 -; movdqa %xmm9, %xmm0 +; movdqa %xmm0, %xmm8 +; movdqu const(0), %xmm0 +; movdqa %xmm8, %xmm4 +; pand %xmm4, %xmm0, %xmm4 ; pandn %xmm0, %xmm1, %xmm0 -; por %xmm0, %xmm5, %xmm0 +; por %xmm0, %xmm4, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif b/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif index c35942613a..d4e613198c 100644 --- a/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif +++ b/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif @@ -137,9 +137,9 @@ block0(v0: i16x8, v1: i16x8, v2: i16x8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm2, %xmm6 -; pblendvb %xmm6, %xmm1, %xmm6 -; movdqa %xmm6, %xmm0 +; movdqa %xmm2, %xmm5 +; pblendvb %xmm5, %xmm1, %xmm5 +; movdqa %xmm5, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -153,9 +153,9 @@ block0(v0: i32x4, v1: f32x4, v2: f32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm2, %xmm6 -; blendvps %xmm6, %xmm1, %xmm6 -; movdqa %xmm6, %xmm0 +; movdqa %xmm2, %xmm5 +; blendvps %xmm5, %xmm1, %xmm5 +; movdqa %xmm5, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -169,9 +169,9 @@ block0(v0: i64x2, v1: f64x2, v2: f64x2): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm2, %xmm6 -; blendvpd %xmm6, %xmm1, %xmm6 -; movdqa %xmm6, %xmm0 +; movdqa %xmm2, %xmm5 +; blendvpd %xmm5, %xmm1, %xmm5 +; movdqa %xmm5, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -187,14 +187,14 @@ block0(v0: i32): ; movq %rsp, %rbp ; block0: ; movdqu const(1), %xmm0 -; movq %rdi, %r11 -; andq %r11, $7, %r11 -; movd %r11d, %xmm6 -; psllw %xmm0, %xmm6, %xmm0 -; lea const(0), %rdi -; shlq $4, %r11, %r11 -; movdqu 0(%rdi,%r11,1), %xmm14 -; pand %xmm0, %xmm14, %xmm0 +; movq %rdi, %r10 +; andq %r10, $7, %r10 +; movd %r10d, %xmm5 +; psllw %xmm0, %xmm5, %xmm0 +; lea const(0), %rsi +; shlq $4, %r10, %r10 +; movdqu 0(%rsi,%r10,1), %xmm13 +; pand %xmm0, %xmm13, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -211,14 +211,14 @@ block0: ; movq %rsp, %rbp ; block0: ; movdqu const(1), %xmm0 -; movl $1, %r10d -; andq %r10, $7, %r10 -; movd %r10d, %xmm6 -; psrlw %xmm0, %xmm6, %xmm0 -; lea const(0), %rdi -; shlq $4, %r10, %r10 -; movdqu 0(%rdi,%r10,1), %xmm14 -; pand %xmm0, %xmm14, %xmm0 +; movl $1, %r9d +; andq %r9, $7, %r9 +; movd %r9d, %xmm5 +; psrlw %xmm0, %xmm5, %xmm0 +; lea const(0), %rsi +; shlq $4, %r9, %r9 +; movdqu 0(%rsi,%r9,1), %xmm13 +; pand %xmm0, %xmm13, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -233,17 +233,17 @@ block0(v0: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqu const(0), %xmm9 -; movq %rdi, %r10 -; andq %r10, $7, %r10 -; movdqa %xmm9, %xmm0 -; punpcklbw %xmm0, %xmm9, %xmm0 -; punpckhbw %xmm9, %xmm9, %xmm9 -; addl %r10d, $8, %r10d -; movd %r10d, %xmm12 -; psraw %xmm0, %xmm12, %xmm0 -; psraw %xmm9, %xmm12, %xmm9 -; packsswb %xmm0, %xmm9, %xmm0 +; movdqu const(0), %xmm8 +; movq %rdi, %r9 +; andq %r9, $7, %r9 +; movdqa %xmm8, %xmm0 +; punpcklbw %xmm0, %xmm8, %xmm0 +; punpckhbw %xmm8, %xmm8, %xmm8 +; addl %r9d, $8, %r9d +; movd %r9d, %xmm11 +; psraw %xmm0, %xmm11, %xmm0 +; psraw %xmm8, %xmm11, %xmm8 +; packsswb %xmm0, %xmm8, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -257,19 +257,19 @@ block0(v0: i8x16, v1: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl $3, %r11d -; andq %r11, $7, %r11 -; movdqa %xmm0, %xmm14 -; punpcklbw %xmm14, %xmm0, %xmm14 -; movdqa %xmm14, %xmm13 -; movdqa %xmm0, %xmm14 -; punpckhbw %xmm14, %xmm0, %xmm14 -; addl %r11d, $8, %r11d -; movd %r11d, %xmm15 -; movdqa %xmm13, %xmm0 -; psraw %xmm0, %xmm15, %xmm0 -; psraw %xmm14, %xmm15, %xmm14 -; packsswb %xmm0, %xmm14, %xmm0 +; movl $3, %r10d +; andq %r10, $7, %r10 +; movdqa %xmm0, %xmm13 +; punpcklbw %xmm13, %xmm0, %xmm13 +; movdqa %xmm13, %xmm12 +; movdqa %xmm0, %xmm13 +; punpckhbw %xmm13, %xmm0, %xmm13 +; addl %r10d, $8, %r10d +; movd %r10d, %xmm14 +; movdqa %xmm12, %xmm0 +; psraw %xmm0, %xmm14, %xmm0 +; psraw %xmm13, %xmm14, %xmm13 +; packsswb %xmm0, %xmm13, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -283,14 +283,14 @@ block0(v0: i64x2, v1: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; pextrd.w $0, %xmm0, %r9 -; pextrd.w $1, %xmm0, %r11 +; pextrd.w $0, %xmm0, %r8 +; pextrd.w $1, %xmm0, %r10 ; movq %rdi, %rcx -; sarq %cl, %r9, %r9 -; sarq %cl, %r11, %r11 +; sarq %cl, %r8, %r8 +; sarq %cl, %r10, %r10 ; uninit %xmm0 -; pinsrd.w $0, %xmm0, %r9, %xmm0 -; pinsrd.w $1, %xmm0, %r11, %xmm0 +; pinsrd.w $0, %xmm0, %r8, %xmm0 +; pinsrd.w $1, %xmm0, %r10, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif b/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif index f1e049735b..5357180789 100644 --- a/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif +++ b/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif @@ -12,8 +12,8 @@ block0(v0: i32x4, v1: i32x4): ; movq %rsp, %rbp ; block0: ; pcmpeqd %xmm0, %xmm1, %xmm0 -; pcmpeqd %xmm6, %xmm6, %xmm6 -; pxor %xmm0, %xmm6, %xmm0 +; pcmpeqd %xmm5, %xmm5, %xmm5 +; pxor %xmm0, %xmm5, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -29,8 +29,8 @@ block0(v0: i32x4, v1: i32x4): ; block0: ; pmaxud %xmm0, %xmm1, %xmm0 ; pcmpeqd %xmm0, %xmm1, %xmm0 -; pcmpeqd %xmm8, %xmm8, %xmm8 -; pxor %xmm0, %xmm8, %xmm0 +; pcmpeqd %xmm7, %xmm7, %xmm7 +; pxor %xmm0, %xmm7, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -44,9 +44,9 @@ block0(v0: i16x8, v1: i16x8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm4 -; pmaxsw %xmm4, %xmm1, %xmm4 -; pcmpeqw %xmm0, %xmm4, %xmm0 +; movdqa %xmm0, %xmm3 +; pmaxsw %xmm3, %xmm1, %xmm3 +; pcmpeqw %xmm0, %xmm3, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -60,9 +60,9 @@ block0(v0: i8x16, v1: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm4 -; pmaxub %xmm4, %xmm1, %xmm4 -; pcmpeqb %xmm0, %xmm4, %xmm0 +; movdqa %xmm0, %xmm3 +; pmaxub %xmm3, %xmm1, %xmm3 +; pcmpeqb %xmm0, %xmm3, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif b/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif index 6022d99b08..70250c3280 100644 --- a/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif +++ b/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif @@ -16,12 +16,12 @@ block0: ; movq %rsp, %rbp ; block0: ; movdqu const(3), %xmm0 -; movdqu const(2), %xmm5 -; movdqu const(0), %xmm3 -; pshufb %xmm0, %xmm3, %xmm0 -; movdqu const(1), %xmm7 -; pshufb %xmm5, %xmm7, %xmm5 -; por %xmm0, %xmm5, %xmm0 +; movdqu const(2), %xmm4 +; movdqu const(0), %xmm2 +; pshufb %xmm0, %xmm2, %xmm0 +; movdqu const(1), %xmm6 +; pshufb %xmm4, %xmm6, %xmm4 +; por %xmm0, %xmm4, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -37,8 +37,8 @@ block0: ; movq %rsp, %rbp ; block0: ; movdqu const(1), %xmm0 -; movdqu const(0), %xmm2 -; pshufb %xmm0, %xmm2, %xmm0 +; movdqu const(0), %xmm1 +; pshufb %xmm0, %xmm1, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -55,10 +55,10 @@ block0: ; movq %rsp, %rbp ; block0: ; movdqu const(1), %xmm0 -; movdqu const(1), %xmm3 -; movdqu const(0), %xmm4 -; paddusb %xmm3, %xmm4, %xmm3 -; pshufb %xmm0, %xmm3, %xmm0 +; movdqu const(1), %xmm2 +; movdqu const(0), %xmm3 +; paddusb %xmm2, %xmm3, %xmm2 +; pshufb %xmm0, %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -74,8 +74,8 @@ block0(v0: i8): ; block0: ; uninit %xmm0 ; pinsrb $0, %xmm0, %rdi, %xmm0 -; pxor %xmm7, %xmm7, %xmm7 -; pshufb %xmm0, %xmm7, %xmm0 +; pxor %xmm6, %xmm6, %xmm6 +; pshufb %xmm0, %xmm6, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -90,11 +90,11 @@ block0: ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl $-1, %edi -; uninit %xmm5 -; pinsrw $0, %xmm5, %rdi, %xmm5 -; pinsrw $1, %xmm5, %rdi, %xmm5 -; pshufd $0, %xmm5, %xmm0 +; movl $-1, %esi +; uninit %xmm4 +; pinsrw $0, %xmm4, %rsi, %xmm4 +; pinsrw $1, %xmm4, %rsi, %xmm4 +; pshufd $0, %xmm4, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -108,9 +108,9 @@ block0(v0: i32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; uninit %xmm4 -; pinsrd $0, %xmm4, %rdi, %xmm4 -; pshufd $0, %xmm4, %xmm0 +; uninit %xmm3 +; pinsrd $0, %xmm3, %rdi, %xmm3 +; pshufd $0, %xmm3, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -124,11 +124,11 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm6 +; movdqa %xmm0, %xmm5 ; uninit %xmm0 -; movdqa %xmm6, %xmm7 -; movsd %xmm0, %xmm7, %xmm0 -; movlhps %xmm0, %xmm7, %xmm0 +; movdqa %xmm5, %xmm6 +; movsd %xmm0, %xmm6, %xmm0 +; movlhps %xmm0, %xmm6, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/simd-logical-compile.clif b/cranelift/filetests/filetests/isa/x64/simd-logical-compile.clif index acb12c809a..1bffe9ac28 100644 --- a/cranelift/filetests/filetests/isa/x64/simd-logical-compile.clif +++ b/cranelift/filetests/filetests/isa/x64/simd-logical-compile.clif @@ -11,8 +11,8 @@ block0(v0: i32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; pcmpeqd %xmm3, %xmm3, %xmm3 -; pxor %xmm0, %xmm3, %xmm0 +; pcmpeqd %xmm2, %xmm2, %xmm2 +; pxor %xmm0, %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -41,10 +41,10 @@ block0(v0: i64x2): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; pxor %xmm3, %xmm3, %xmm3 -; movdqa %xmm0, %xmm5 -; pcmpeqq %xmm5, %xmm3, %xmm5 -; ptest %xmm5, %xmm5 +; pxor %xmm2, %xmm2, %xmm2 +; movdqa %xmm0, %xmm4 +; pcmpeqq %xmm4, %xmm2, %xmm4 +; ptest %xmm4, %xmm4 ; setz %al ; movq %rbp, %rsp ; popq %rbp diff --git a/cranelift/filetests/filetests/isa/x64/simd-pairwise-add.clif b/cranelift/filetests/filetests/isa/x64/simd-pairwise-add.clif index 3abf721f02..f69921386d 100644 --- a/cranelift/filetests/filetests/isa/x64/simd-pairwise-add.clif +++ b/cranelift/filetests/filetests/isa/x64/simd-pairwise-add.clif @@ -12,10 +12,10 @@ block0(v0: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm5 +; movdqa %xmm0, %xmm4 ; movdqu const(0), %xmm0 -; movdqa %xmm5, %xmm6 -; pmaddubsw %xmm0, %xmm6, %xmm0 +; movdqa %xmm4, %xmm5 +; pmaddubsw %xmm0, %xmm5, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -31,8 +31,8 @@ block0(v0: i16x8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqu const(0), %xmm3 -; pmaddwd %xmm0, %xmm3, %xmm0 +; movdqu const(0), %xmm2 +; pmaddwd %xmm0, %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -48,8 +48,8 @@ block0(v0: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqu const(0), %xmm3 -; pmaddubsw %xmm0, %xmm3, %xmm0 +; movdqu const(0), %xmm2 +; pmaddubsw %xmm0, %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -65,12 +65,12 @@ block0(v0: i16x8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqu const(0), %xmm3 -; pxor %xmm0, %xmm3, %xmm0 -; movdqu const(1), %xmm7 -; pmaddwd %xmm0, %xmm7, %xmm0 -; movdqu const(2), %xmm11 -; paddd %xmm0, %xmm11, %xmm0 +; movdqu const(0), %xmm2 +; pxor %xmm0, %xmm2, %xmm0 +; movdqu const(1), %xmm6 +; pmaddwd %xmm0, %xmm6, %xmm0 +; movdqu const(2), %xmm10 +; paddd %xmm0, %xmm10, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif b/cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif index 534ceb733c..83469f9644 100644 --- a/cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif +++ b/cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif @@ -10,10 +10,10 @@ block0(v0: i16x8, v1: i16x8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqu const(0), %xmm6 +; movdqu const(0), %xmm5 ; pmulhrsw %xmm0, %xmm1, %xmm0 -; pcmpeqw %xmm6, %xmm0, %xmm6 -; pxor %xmm0, %xmm6, %xmm0 +; pcmpeqw %xmm5, %xmm0, %xmm5 +; pxor %xmm0, %xmm5, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/sshr.clif b/cranelift/filetests/filetests/isa/x64/sshr.clif index 50f88e0612..8f66e59472 100644 --- a/cranelift/filetests/filetests/isa/x64/sshr.clif +++ b/cranelift/filetests/filetests/isa/x64/sshr.clif @@ -19,24 +19,24 @@ block0(v0: i128, v1: i8): ; movzbq %dl, %rcx ; movq %rdi, %r8 ; shrq %cl, %r8, %r8 -; movq %rsi, %rdi -; sarq %cl, %rdi, %rdi -; movq %rcx, %rax +; movq %rsi, %r10 +; sarq %cl, %r10, %r10 +; movq %rcx, %r11 ; movl $64, %ecx -; movq %rax, %r9 -; subq %rcx, %r9, %rcx -; movq %rsi, %r11 -; shlq %cl, %r11, %r11 -; xorq %rax, %rax, %rax -; testq $127, %r9 -; cmovzq %rax, %r11, %r11 -; orq %r8, %r11, %r8 +; movq %r11, %rax +; subq %rcx, %rax, %rcx +; movq %rsi, %r9 +; shlq %cl, %r9, %r9 +; xorq %r11, %r11, %r11 +; testq $127, %rax +; cmovzq %r11, %r9, %r9 +; orq %r8, %r9, %r8 ; movq %rsi, %rdx ; sarq $63, %rdx, %rdx -; testq $64, %r9 -; movq %rdi, %rax +; testq $64, %rax +; movq %r10, %rax ; cmovzq %r8, %rax, %rax -; cmovzq %rdi, %rdx, %rdx +; cmovzq %r10, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -51,25 +51,25 @@ block0(v0: i128, v1: i64): ; movq %rsp, %rbp ; block0: ; movq %rdx, %rcx -; movq %rdi, %r8 -; shrq %cl, %r8, %r8 -; movq %rsi, %r11 -; sarq %cl, %r11, %r11 +; movq %rdi, %r11 +; shrq %cl, %r11, %r11 +; movq %rsi, %r9 +; sarq %cl, %r9, %r9 ; movl $64, %ecx -; movq %rdx, %r9 -; subq %rcx, %r9, %rcx -; movq %rsi, %r10 -; shlq %cl, %r10, %r10 -; xorq %rdi, %rdi, %rdi -; testq $127, %r9 -; cmovzq %rdi, %r10, %r10 -; orq %r8, %r10, %r8 +; movq %rdx, %rdi +; subq %rcx, %rdi, %rcx +; movq %rsi, %r8 +; shlq %cl, %r8, %r8 +; xorq %r10, %r10, %r10 +; testq $127, %rdi +; cmovzq %r10, %r8, %r8 +; orq %r11, %r8, %r11 ; movq %rsi, %rdx ; sarq $63, %rdx, %rdx -; testq $64, %r9 -; movq %r11, %rax -; cmovzq %r8, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; testq $64, %rdi +; movq %r9, %rax +; cmovzq %r11, %rax, %rax +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -84,25 +84,25 @@ block0(v0: i128, v1: i32): ; movq %rsp, %rbp ; block0: ; movq %rdx, %rcx -; movq %rdi, %r8 -; shrq %cl, %r8, %r8 -; movq %rsi, %r11 -; sarq %cl, %r11, %r11 +; movq %rdi, %r11 +; shrq %cl, %r11, %r11 +; movq %rsi, %r9 +; sarq %cl, %r9, %r9 ; movl $64, %ecx -; movq %rdx, %r9 -; subq %rcx, %r9, %rcx -; movq %rsi, %r10 -; shlq %cl, %r10, %r10 -; xorq %rdi, %rdi, %rdi -; testq $127, %r9 -; cmovzq %rdi, %r10, %r10 -; orq %r8, %r10, %r8 +; movq %rdx, %rdi +; subq %rcx, %rdi, %rcx +; movq %rsi, %r8 +; shlq %cl, %r8, %r8 +; xorq %r10, %r10, %r10 +; testq $127, %rdi +; cmovzq %r10, %r8, %r8 +; orq %r11, %r8, %r11 ; movq %rsi, %rdx ; sarq $63, %rdx, %rdx -; testq $64, %r9 -; movq %r11, %rax -; cmovzq %r8, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; testq $64, %rdi +; movq %r9, %rax +; cmovzq %r11, %rax, %rax +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -117,25 +117,25 @@ block0(v0: i128, v1: i16): ; movq %rsp, %rbp ; block0: ; movq %rdx, %rcx -; movq %rdi, %r8 -; shrq %cl, %r8, %r8 -; movq %rsi, %r11 -; sarq %cl, %r11, %r11 +; movq %rdi, %r11 +; shrq %cl, %r11, %r11 +; movq %rsi, %r9 +; sarq %cl, %r9, %r9 ; movl $64, %ecx -; movq %rdx, %r9 -; subq %rcx, %r9, %rcx -; movq %rsi, %r10 -; shlq %cl, %r10, %r10 -; xorq %rdi, %rdi, %rdi -; testq $127, %r9 -; cmovzq %rdi, %r10, %r10 -; orq %r8, %r10, %r8 +; movq %rdx, %rdi +; subq %rcx, %rdi, %rcx +; movq %rsi, %r8 +; shlq %cl, %r8, %r8 +; xorq %r10, %r10, %r10 +; testq $127, %rdi +; cmovzq %r10, %r8, %r8 +; orq %r11, %r8, %r11 ; movq %rsi, %rdx ; sarq $63, %rdx, %rdx -; testq $64, %r9 -; movq %r11, %rax -; cmovzq %r8, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; testq $64, %rdi +; movq %r9, %rax +; cmovzq %r11, %rax, %rax +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -150,25 +150,25 @@ block0(v0: i128, v1: i8): ; movq %rsp, %rbp ; block0: ; movq %rdx, %rcx -; movq %rdi, %r8 -; shrq %cl, %r8, %r8 -; movq %rsi, %r11 -; sarq %cl, %r11, %r11 +; movq %rdi, %r11 +; shrq %cl, %r11, %r11 +; movq %rsi, %r9 +; sarq %cl, %r9, %r9 ; movl $64, %ecx -; movq %rdx, %r9 -; subq %rcx, %r9, %rcx -; movq %rsi, %r10 -; shlq %cl, %r10, %r10 -; xorq %rdi, %rdi, %rdi -; testq $127, %r9 -; cmovzq %rdi, %r10, %r10 -; orq %r8, %r10, %r8 +; movq %rdx, %rdi +; subq %rcx, %rdi, %rcx +; movq %rsi, %r8 +; shlq %cl, %r8, %r8 +; xorq %r10, %r10, %r10 +; testq $127, %rdi +; cmovzq %r10, %r8, %r8 +; orq %r11, %r8, %r11 ; movq %rsi, %rdx ; sarq $63, %rdx, %rdx -; testq $64, %r9 -; movq %r11, %rax -; cmovzq %r8, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; testq $64, %rdi +; movq %r9, %rax +; cmovzq %r11, %rax, %rax +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/struct-arg.clif b/cranelift/filetests/filetests/isa/x64/struct-arg.clif index e4c5363071..c3055b76b7 100644 --- a/cranelift/filetests/filetests/isa/x64/struct-arg.clif +++ b/cranelift/filetests/filetests/isa/x64/struct-arg.clif @@ -29,8 +29,8 @@ block0(v0: i64, v1: i64): ; block0: ; lea 16(%rbp), %rsi ; movzbq 0(%rdi), %rax -; movzbq 0(%rsi), %r10 -; addl %eax, %r10d, %eax +; movzbq 0(%rsi), %r9 +; addl %eax, %r9d, %eax ; movq %rbp, %rsp ; popq %rbp ; ret @@ -71,20 +71,20 @@ block0(v0: i64, v1: i64): ; pushq %rbp ; movq %rsp, %rbp ; subq %rsp, $16, %rsp -; movq %r14, 0(%rsp) +; movq %r13, 0(%rsp) ; block0: -; movq %rdi, %r14 +; movq %rdi, %r13 ; subq %rsp, $64, %rsp ; virtual_sp_offset_adjust 64 ; lea 0(%rsp), %rdi ; movl $64, %edx -; load_ext_name %Memcpy+0, %rcx -; call *%rcx -; movq %r14, %rdi +; load_ext_name %Memcpy+0, %rax +; call *%rax +; movq %r13, %rdi ; call User(userextname0) ; addq %rsp, $64, %rsp ; virtual_sp_offset_adjust -64 -; movq 0(%rsp), %r14 +; movq 0(%rsp), %r13 ; addq %rsp, $16, %rsp ; movq %rbp, %rsp ; popq %rbp @@ -104,8 +104,8 @@ block0(v0: i64, v1: i64): ; lea 16(%rbp), %rsi ; lea 144(%rbp), %rdi ; movzbq 0(%rsi), %rax -; movzbq 0(%rdi), %r10 -; addl %eax, %r10d, %eax +; movzbq 0(%rdi), %r9 +; addl %eax, %r9d, %eax ; movq %rbp, %rsp ; popq %rbp ; ret @@ -121,29 +121,29 @@ block0(v0: i64, v1: i64, v2: i64): ; pushq %rbp ; movq %rsp, %rbp ; subq %rsp, $16, %rsp -; movq %r13, 0(%rsp) -; movq %r15, 8(%rsp) +; movq %r12, 0(%rsp) +; movq %r14, 8(%rsp) ; block0: -; movq %rdx, %r15 -; movq %rdi, %r13 +; movq %rdx, %r14 +; movq %rdi, %r12 ; subq %rsp, $192, %rsp ; virtual_sp_offset_adjust 192 ; lea 0(%rsp), %rdi ; movl $128, %edx -; load_ext_name %Memcpy+0, %r8 -; call *%r8 +; load_ext_name %Memcpy+0, %rcx +; call *%rcx ; lea 128(%rsp), %rdi -; movq %r15, %rsi +; movq %r14, %rsi ; movl $64, %edx -; load_ext_name %Memcpy+0, %r8 -; movq %r15, %rsi -; call *%r8 -; movq %r13, %rdi +; load_ext_name %Memcpy+0, %rcx +; movq %r14, %rsi +; call *%rcx +; movq %r12, %rdi ; call User(userextname0) ; addq %rsp, $192, %rsp ; virtual_sp_offset_adjust -192 -; movq 0(%rsp), %r13 -; movq 8(%rsp), %r15 +; movq 0(%rsp), %r12 +; movq 8(%rsp), %r14 ; addq %rsp, $16, %rsp ; movq %rbp, %rsp ; popq %rbp diff --git a/cranelift/filetests/filetests/isa/x64/struct-ret.clif b/cranelift/filetests/filetests/isa/x64/struct-ret.clif index a502546ce4..c5e6f68817 100644 --- a/cranelift/filetests/filetests/isa/x64/struct-ret.clif +++ b/cranelift/filetests/filetests/isa/x64/struct-ret.clif @@ -31,8 +31,8 @@ block0(v0: i64, v1: i64): ; movq %rsp, %rbp ; block0: ; movq %rsi, %rdi -; load_ext_name %f2+0, %r8 -; call *%r8 +; load_ext_name %f2+0, %rdx +; call *%rdx ; movq %rdx, %rax ; movq %rbp, %rsp ; popq %rbp diff --git a/cranelift/filetests/filetests/isa/x64/trunc-libcall.clif b/cranelift/filetests/filetests/isa/x64/trunc-libcall.clif index 5256edb2f1..d547627d89 100644 --- a/cranelift/filetests/filetests/isa/x64/trunc-libcall.clif +++ b/cranelift/filetests/filetests/isa/x64/trunc-libcall.clif @@ -10,8 +10,8 @@ block0(v0: f32): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; load_ext_name %TruncF32+0, %rdx -; call *%rdx +; load_ext_name %TruncF32+0, %rcx +; call *%rcx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -25,8 +25,8 @@ block0(v0: f64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; load_ext_name %TruncF64+0, %rdx -; call *%rdx +; load_ext_name %TruncF64+0, %rcx +; call *%rcx ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/umax-bug.clif b/cranelift/filetests/filetests/isa/x64/umax-bug.clif index 63ea9b4c6e..09b7c8106b 100644 --- a/cranelift/filetests/filetests/isa/x64/umax-bug.clif +++ b/cranelift/filetests/filetests/isa/x64/umax-bug.clif @@ -11,10 +11,10 @@ block0(v1: i32, v2: i64): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movl 0(%rsi), %r8d -; cmpl %edi, %r8d +; movl 0(%rsi), %edx +; cmpl %edi, %edx ; movq %rdi, %rax -; cmovnbl %r8d, %eax, %eax +; cmovnbl %edx, %eax, %eax ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/ushr.clif b/cranelift/filetests/filetests/isa/x64/ushr.clif index 401e6c9265..2d0f7f9324 100644 --- a/cranelift/filetests/filetests/isa/x64/ushr.clif +++ b/cranelift/filetests/filetests/isa/x64/ushr.clif @@ -16,25 +16,25 @@ block0(v0: i128, v1: i8): ; movq %rsp, %rbp ; block0: ; movzbq %dl, %rcx -; movq %rdi, %r10 -; shrq %cl, %r10, %r10 -; movq %rsi, %r8 +; movq %rdi, %r8 ; shrq %cl, %r8, %r8 -; movq %rcx, %rdi +; movq %rsi, %r10 +; shrq %cl, %r10, %r10 +; movq %rcx, %r11 ; movl $64, %ecx -; movq %rdi, %r9 -; subq %rcx, %r9, %rcx -; movq %rsi, %rdi -; shlq %cl, %rdi, %rdi -; xorq %r11, %r11, %r11 -; testq $127, %r9 -; cmovzq %r11, %rdi, %rdi -; orq %rdi, %r10, %rdi +; movq %r11, %rax +; subq %rcx, %rax, %rcx +; movq %rsi, %r11 +; shlq %cl, %r11, %r11 +; xorq %r9, %r9, %r9 +; testq $127, %rax +; cmovzq %r9, %r11, %r11 +; orq %r11, %r8, %r11 ; xorq %rdx, %rdx, %rdx -; testq $64, %r9 -; movq %r8, %rax -; cmovzq %rdi, %rax, %rax -; cmovzq %r8, %rdx, %rdx +; testq $64, %rax +; movq %r10, %rax +; cmovzq %r11, %rax, %rax +; cmovzq %r10, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -49,23 +49,25 @@ block0(v0: i128, v1: i64): ; movq %rsp, %rbp ; block0: ; movq %rdx, %rcx -; movq %rdi, %r9 +; movq %rdi, %rdx +; shrq %cl, %rdx, %rdx +; movq %rsi, %r9 ; shrq %cl, %r9, %r9 -; movq %rsi, %r11 -; shrq %cl, %r11, %r11 +; movq %rcx, %r10 ; movl $64, %ecx -; movq %rdx, %r8 -; subq %rcx, %r8, %rcx -; shlq %cl, %rsi, %rsi -; xorq %r10, %r10, %r10 -; testq $127, %r8 -; cmovzq %r10, %rsi, %rsi -; orq %rsi, %r9, %rsi +; movq %r10, %rdi +; subq %rcx, %rdi, %rcx +; movq %rsi, %r10 +; shlq %cl, %r10, %r10 +; xorq %r8, %r8, %r8 +; testq $127, %rdi +; cmovzq %r8, %r10, %r10 +; orq %r10, %rdx, %r10 ; xorq %rdx, %rdx, %rdx -; testq $64, %r8 -; movq %r11, %rax -; cmovzq %rsi, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; testq $64, %rdi +; movq %r9, %rax +; cmovzq %r10, %rax, %rax +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -80,23 +82,25 @@ block0(v0: i128, v1: i32): ; movq %rsp, %rbp ; block0: ; movq %rdx, %rcx -; movq %rdi, %r9 +; movq %rdi, %rdx +; shrq %cl, %rdx, %rdx +; movq %rsi, %r9 ; shrq %cl, %r9, %r9 -; movq %rsi, %r11 -; shrq %cl, %r11, %r11 +; movq %rcx, %r10 ; movl $64, %ecx -; movq %rdx, %r8 -; subq %rcx, %r8, %rcx -; shlq %cl, %rsi, %rsi -; xorq %r10, %r10, %r10 -; testq $127, %r8 -; cmovzq %r10, %rsi, %rsi -; orq %rsi, %r9, %rsi +; movq %r10, %rdi +; subq %rcx, %rdi, %rcx +; movq %rsi, %r10 +; shlq %cl, %r10, %r10 +; xorq %r8, %r8, %r8 +; testq $127, %rdi +; cmovzq %r8, %r10, %r10 +; orq %r10, %rdx, %r10 ; xorq %rdx, %rdx, %rdx -; testq $64, %r8 -; movq %r11, %rax -; cmovzq %rsi, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; testq $64, %rdi +; movq %r9, %rax +; cmovzq %r10, %rax, %rax +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -111,23 +115,25 @@ block0(v0: i128, v1: i16): ; movq %rsp, %rbp ; block0: ; movq %rdx, %rcx -; movq %rdi, %r9 +; movq %rdi, %rdx +; shrq %cl, %rdx, %rdx +; movq %rsi, %r9 ; shrq %cl, %r9, %r9 -; movq %rsi, %r11 -; shrq %cl, %r11, %r11 +; movq %rcx, %r10 ; movl $64, %ecx -; movq %rdx, %r8 -; subq %rcx, %r8, %rcx -; shlq %cl, %rsi, %rsi -; xorq %r10, %r10, %r10 -; testq $127, %r8 -; cmovzq %r10, %rsi, %rsi -; orq %rsi, %r9, %rsi +; movq %r10, %rdi +; subq %rcx, %rdi, %rcx +; movq %rsi, %r10 +; shlq %cl, %r10, %r10 +; xorq %r8, %r8, %r8 +; testq $127, %rdi +; cmovzq %r8, %r10, %r10 +; orq %r10, %rdx, %r10 ; xorq %rdx, %rdx, %rdx -; testq $64, %r8 -; movq %r11, %rax -; cmovzq %rsi, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; testq $64, %rdi +; movq %r9, %rax +; cmovzq %r10, %rax, %rax +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret @@ -142,23 +148,25 @@ block0(v0: i128, v1: i8): ; movq %rsp, %rbp ; block0: ; movq %rdx, %rcx -; movq %rdi, %r9 +; movq %rdi, %rdx +; shrq %cl, %rdx, %rdx +; movq %rsi, %r9 ; shrq %cl, %r9, %r9 -; movq %rsi, %r11 -; shrq %cl, %r11, %r11 +; movq %rcx, %r10 ; movl $64, %ecx -; movq %rdx, %r8 -; subq %rcx, %r8, %rcx -; shlq %cl, %rsi, %rsi -; xorq %r10, %r10, %r10 -; testq $127, %r8 -; cmovzq %r10, %rsi, %rsi -; orq %rsi, %r9, %rsi +; movq %r10, %rdi +; subq %rcx, %rdi, %rcx +; movq %rsi, %r10 +; shlq %cl, %r10, %r10 +; xorq %r8, %r8, %r8 +; testq $127, %rdi +; cmovzq %r8, %r10, %r10 +; orq %r10, %rdx, %r10 ; xorq %rdx, %rdx, %rdx -; testq $64, %r8 -; movq %r11, %rax -; cmovzq %rsi, %rax, %rax -; cmovzq %r11, %rdx, %rdx +; testq $64, %rdi +; movq %r9, %rax +; cmovzq %r10, %rax, %rax +; cmovzq %r9, %rdx, %rdx ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/uunarrow.clif b/cranelift/filetests/filetests/isa/x64/uunarrow.clif index facc115bd1..f42e52ee08 100644 --- a/cranelift/filetests/filetests/isa/x64/uunarrow.clif +++ b/cranelift/filetests/filetests/isa/x64/uunarrow.clif @@ -12,15 +12,15 @@ block0(v0: f64x2): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; xorpd %xmm3, %xmm3, %xmm3 -; movdqa %xmm0, %xmm7 -; maxpd %xmm7, %xmm3, %xmm7 -; movupd const(0), %xmm8 -; minpd %xmm7, %xmm8, %xmm7 -; roundpd $3, %xmm7, %xmm0 -; movupd const(1), %xmm13 -; addpd %xmm0, %xmm13, %xmm0 -; shufps $136, %xmm0, %xmm3, %xmm0 +; xorpd %xmm2, %xmm2, %xmm2 +; movdqa %xmm0, %xmm6 +; maxpd %xmm6, %xmm2, %xmm6 +; movupd const(0), %xmm7 +; minpd %xmm6, %xmm7, %xmm6 +; roundpd $3, %xmm6, %xmm0 +; movupd const(1), %xmm12 +; addpd %xmm0, %xmm12, %xmm0 +; shufps $136, %xmm0, %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/vhigh_bits.clif b/cranelift/filetests/filetests/isa/x64/vhigh_bits.clif index 538d6ddcd8..f0de62903f 100644 --- a/cranelift/filetests/filetests/isa/x64/vhigh_bits.clif +++ b/cranelift/filetests/filetests/isa/x64/vhigh_bits.clif @@ -38,9 +38,9 @@ block0(v0: i16x8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm3 -; packsswb %xmm3, %xmm0, %xmm3 -; pmovmskb %xmm3, %eax +; movdqa %xmm0, %xmm2 +; packsswb %xmm2, %xmm0, %xmm2 +; pmovmskb %xmm2, %eax ; shrq $8, %rax, %rax ; movq %rbp, %rsp ; popq %rbp diff --git a/cranelift/filetests/filetests/isa/x64/widen-high-bug.clif b/cranelift/filetests/filetests/isa/x64/widen-high-bug.clif index 22740e62e2..d6f381c85c 100644 --- a/cranelift/filetests/filetests/isa/x64/widen-high-bug.clif +++ b/cranelift/filetests/filetests/isa/x64/widen-high-bug.clif @@ -11,9 +11,9 @@ block0(v0: i64, v2: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqu 80(%rdi), %xmm4 -; palignr $8, %xmm4, %xmm4, %xmm4 -; pmovzxbw %xmm4, %xmm0 +; movdqu 80(%rdi), %xmm3 +; palignr $8, %xmm3, %xmm3, %xmm3 +; pmovzxbw %xmm3, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret diff --git a/cranelift/filetests/filetests/isa/x64/widening.clif b/cranelift/filetests/filetests/isa/x64/widening.clif index 9157cbff01..e432267d07 100644 --- a/cranelift/filetests/filetests/isa/x64/widening.clif +++ b/cranelift/filetests/filetests/isa/x64/widening.clif @@ -52,9 +52,9 @@ block0(v0: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm3 -; palignr $8, %xmm3, %xmm0, %xmm3 -; pmovsxbw %xmm3, %xmm0 +; movdqa %xmm0, %xmm2 +; palignr $8, %xmm2, %xmm0, %xmm2 +; pmovsxbw %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -68,9 +68,9 @@ block0(v0: i16x8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm3 -; palignr $8, %xmm3, %xmm0, %xmm3 -; pmovsxwd %xmm3, %xmm0 +; movdqa %xmm0, %xmm2 +; palignr $8, %xmm2, %xmm0, %xmm2 +; pmovsxwd %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -84,8 +84,8 @@ block0(v0: i32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; pshufd $238, %xmm0, %xmm3 -; pmovsxdq %xmm3, %xmm0 +; pshufd $238, %xmm0, %xmm2 +; pmovsxdq %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -141,9 +141,9 @@ block0(v0: i8x16): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm3 -; palignr $8, %xmm3, %xmm0, %xmm3 -; pmovzxbw %xmm3, %xmm0 +; movdqa %xmm0, %xmm2 +; palignr $8, %xmm2, %xmm0, %xmm2 +; pmovzxbw %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -157,9 +157,9 @@ block0(v0: i16x8): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; movdqa %xmm0, %xmm3 -; palignr $8, %xmm3, %xmm0, %xmm3 -; pmovzxwd %xmm3, %xmm0 +; movdqa %xmm0, %xmm2 +; palignr $8, %xmm2, %xmm0, %xmm2 +; pmovzxwd %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret @@ -173,8 +173,8 @@ block0(v0: i32x4): ; pushq %rbp ; movq %rsp, %rbp ; block0: -; pshufd $238, %xmm0, %xmm3 -; pmovzxdq %xmm3, %xmm0 +; pshufd $238, %xmm0, %xmm2 +; pmovzxdq %xmm2, %xmm0 ; movq %rbp, %rsp ; popq %rbp ; ret