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wasmtime/cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif
Trevor Elliott b077854b57 Generate SSA code from returns (#5172)
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
2022-11-08 16:00:49 -08:00

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test compile precise-output
target aarch64
function %f0(i32) -> i32 {
block0(v0: i32):
v1 = iconst.i32 127
v2 = uadd_overflow_trap v0, v1, user0
return v2
}
; block0:
; movz x2, #127
; adds w0, w0, w2
; b.lo 8 ; udf
; ret
function %f1(i32) -> i32 {
block0(v0: i32):
v1 = iconst.i32 127
v2 = uadd_overflow_trap v1, v0, user0
return v2
}
; block0:
; movz x2, #127
; adds w0, w2, w0
; b.lo 8 ; udf
; ret
function %f2(i32, i32) -> i32 {
block0(v0: i32, v1: i32):
v2 = uadd_overflow_trap v0, v1, user0
return v2
}
; block0:
; adds w0, w0, w1
; b.lo 8 ; udf
; ret
function %f3(i64) -> i64 {
block0(v0: i64):
v1 = iconst.i64 127
v2 = uadd_overflow_trap v0, v1, user0
return v2
}
; block0:
; movz x2, #127
; adds x0, x0, x2
; b.lo 8 ; udf
; ret
function %f3(i64) -> i64 {
block0(v0: i64):
v1 = iconst.i64 127
v2 = uadd_overflow_trap v1, v0, user0
return v2
}
; block0:
; movz x2, #127
; adds x0, x2, x0
; b.lo 8 ; udf
; ret
function %f4(i64, i64) -> i64 {
block0(v0: i64, v1: i64):
v2 = uadd_overflow_trap v0, v1, user0
return v2
}
; block0:
; adds x0, x0, x1
; b.lo 8 ; udf
; ret