add riscv64 backend for cranelift. (#4271)

Add a RISC-V 64 (`riscv64`, RV64GC) backend.

Co-authored-by: yuyang <756445638@qq.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
This commit is contained in:
yuyang-ok
2022-09-28 08:30:31 +08:00
committed by GitHub
parent 9715d91c50
commit cdecc858b4
182 changed files with 21024 additions and 36 deletions

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %alias(i8) -> i8 {
block0(v0: i8):

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64 has_m
function %add_i64(i64, i64) -> i64 {
block0(v0: i64,v1: i64):

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@@ -3,6 +3,7 @@ target s390x
target aarch64
target aarch64 has_lse
target x86_64
target riscv64
; We can't test that these instructions are right regarding atomicity, but we can
; test if they perform their operation correctly

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@@ -2,7 +2,8 @@ test run
target aarch64
target aarch64 has_lse
target x86_64
target s390x
target s390x
target riscv64 has_a
; We can't test that these instructions are right regarding atomicity, but we can
; test if they perform their operation correctly

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@@ -4,6 +4,7 @@ target s390x has_mie2
target aarch64
target aarch64 has_lse
target x86_64
target riscv64 has_a
; We can't test that these instructions are right regarding atomicity, but we can
; test if they perform their operation correctly

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@@ -4,6 +4,7 @@ target s390x has_mie2
target aarch64
target aarch64 has_lse
target x86_64
target riscv64
; We can't test that these instructions are right regarding atomicity, but we can
; test if they perform their operation correctly

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@@ -3,6 +3,7 @@ test run
target aarch64
target x86_64
target s390x
target riscv64
function %bextend_b1_b8(b1) -> b8 {
block0(v0: b1):

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %bint_b1_i8_true() -> i8 {
block0:

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@@ -1,6 +1,7 @@
test run
target aarch64
target s390x
target riscv64
target s390x has_mie2
; target x86_64 TODO: Not yet implemented on x86_64

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %bitrev_i8(i8) -> i8 {
block0(v0: i8):

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target s390x
target riscv64
function %bmask_b64_i64(b64) -> i64 {
block0(v0: b64):

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %jump() -> b1 {
block0:

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@@ -3,7 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %bricmp_eq_i64(i64, i64) -> b1 {
block0(v0: i64, v1: i64):

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@@ -4,6 +4,7 @@ target aarch64
target aarch64 use_bti
target x86_64
target s390x
target riscv64
function %br_table_i32(i32) -> i32 {
jt0 = jump_table [block1, block2, block2, block3]
@@ -38,4 +39,4 @@ block5(v5: i32):
; run: %br_table_i32(4) == 8
; run: %br_table_i32(5) == 9
; run: %br_table_i32(6) == 10
; run: %br_table_i32(-1) == 3
; run: %br_table_i32(-1) == 3

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@@ -3,6 +3,7 @@ test run
target aarch64
target x86_64
target s390x
target riscv64
function %breduce_b8_b1(b8) -> b1 {
block0(v0: b8):

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@@ -4,6 +4,7 @@ target x86_64
target x86_64 has_sse41=false
target aarch64
target s390x
target riscv64
function %ceil_f32(f32) -> f32 {
block0(v0: f32):

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@@ -1,6 +1,7 @@
test interpret
test run
target aarch64
target riscv64
target s390x
; not implemented on `x86_64`

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@@ -4,6 +4,7 @@ target aarch64
target s390x
target x86_64
target x86_64 has_lzcnt
target riscv64
function %clz_i8(i8) -> i8 {
block0(v0: i8):

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@@ -2,6 +2,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %i8_iconst_0() -> i8 {
block0:

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %fcvt_to_sint(f32) -> i32 {
block0(v0: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target s390x
target aarch64
;; target riscv64 vector type not supported.
function %fpromote_f32_f64(i64 vmctx, i64, f32) -> f64 {
gv0 = vmctx

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
target x86_64 has_bmi1
function %ctz_i8(i8) -> i8 {

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@@ -3,6 +3,8 @@ set avoid_div_traps=false
target aarch64
target s390x
target x86_64
target riscv64
; Tests that the `avoid_div_traps` flag prevents a trap when {s,u}rem is called
; with INT_MIN % -1.

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
;;;; basic uextend

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@@ -3,6 +3,7 @@ test run
target aarch64
target x86_64
target s390x
target riscv64
function %fabs_f32(f32) -> f32 {
block0(v0: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fadd_f32(f32, f32) -> f32 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fcmp_eq_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fcmp_ge_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fcmp_gt_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fcmp_le_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fcmp_lt_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fcmp_ne_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -2,6 +2,7 @@ test interpret
test run
target x86_64
target s390x
target riscv64
function %fcmp_one_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -2,6 +2,7 @@ test interpret
test run
target x86_64
target s390x
target riscv64
function %fcmp_ord_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -2,6 +2,7 @@ test interpret
test run
target x86_64
target s390x
target riscv64
function %fcmp_ueq_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -2,6 +2,7 @@ test interpret
test run
target x86_64
target s390x
target riscv64
function %fcmp_uge_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -2,6 +2,7 @@ test interpret
test run
target x86_64
target s390x
target riscv64
function %fcmp_ugt_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -2,6 +2,7 @@ test interpret
test run
target x86_64
target s390x
target riscv64
function %fcmp_ule_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -2,6 +2,7 @@ test interpret
test run
target x86_64
target s390x
target riscv64
function %fcmp_ult_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -2,6 +2,8 @@ test interpret
test run
target x86_64
target s390x
target riscv64
function %fcmp_uno_f32(f32, f32) -> b1 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target aarch64
target x86_64
target s390x
target riscv64
function %fcopysign_f32(f32, f32) -> f32 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fdiv_f32(f32, f32) -> f32 {
block0(v0: f32, v1: f32):

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@@ -4,6 +4,7 @@ target x86_64
target x86_64 has_sse41=false
target aarch64
target s390x
target riscv64
function %floor_f32(f32) -> f32 {
block0(v0: f32):

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@@ -4,6 +4,7 @@ target aarch64
target s390x
target x86_64 has_avx has_fma
target x86_64 has_avx=false has_fma=false
target riscv64
function %fma_f32(f32, f32, f32) -> f32 {
block0(v0: f32, v1: f32, v2: f32):
@@ -148,4 +149,4 @@ block0(v0: f32, v1: f32, v2: f32):
v4 = fma v0, v1, v3
return v4
}
; run: %fma_load_f32(0x9.0, 0x9.0, 0x9.0) == 0x1.680000p6
; run: %fma_load_f32(0x9.0, 0x9.0, 0x9.0) == 0x1.680000p6

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@@ -2,6 +2,7 @@ test interpret
test run
target x86_64
target aarch64
target riscv64
; target s390x FIXME: This currently fails under qemu due to a qemu bug
function %fmax_p_f32(f32, f32) -> f32 {

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fmax_f32(f32, f32) -> f32 {
block0(v0: f32, v1: f32):

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@@ -2,6 +2,7 @@ test interpret
test run
target x86_64
target aarch64
target riscv64
; target s390x FIXME: This currently fails under qemu due to a qemu bug
function %fmin_p_f32(f32, f32) -> f32 {

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fmin_f32(f32, f32) -> f32 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fmul_f32(f32, f32) -> f32 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target aarch64
target x86_64
target s390x
target riscv64
function %fneg_f32(f32) -> f32 {
block0(v0: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target aarch64
target s390x
target riscv64
function %fsub_f32(f32, f32) -> f32 {
block0(v0: f32, v1: f32):

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@@ -3,6 +3,7 @@ test run
target x86_64
target s390x
target aarch64
target riscv64
; Store a value in the heap using `heap_addr` and load it using `global_value`
function %store_load(i64 vmctx, i64, i32) -> i32 {

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@@ -3,7 +3,7 @@ test run
target x86_64
target s390x
target aarch64
target riscv64
function %static_heap_i64(i64 vmctx, i64, i32) -> i32 {
gv0 = vmctx

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@@ -4,6 +4,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %add_i128(i128, i128) -> i128 {
block0(v0: i128,v1: i128):

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@@ -1,5 +1,6 @@
test run
target aarch64
target riscv64
target s390x
function %band_not_i128(i128, i128) -> i128 {

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target s390x
target riscv64
function %bextend_b1_b128(b1) -> b128 {
block0(v0: b1):

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@@ -4,6 +4,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %bint_b1_i128_true() -> i128 {
block0:

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@@ -3,6 +3,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %ctz_i128(i128) -> i128 {
block0(v0: i128):

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@@ -3,6 +3,8 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %bnot_i128(i128) -> i128 {
block0(v0: i128):

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@@ -3,6 +3,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %reverse_bits_zero() -> b1 {
block0:

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@@ -1,6 +1,7 @@
test interpret
test run
target aarch64
target riscv64
target s390x
function %bmask_b128_i128(b128) -> i128 {

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@@ -1,5 +1,6 @@
test run
target aarch64
target riscv64
target s390x
function %bor_not_i128(i128, i128) -> i128 {

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@@ -3,7 +3,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %i128_brz(i128) -> b1 {
block0(v0: i128):

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@@ -1,4 +1,5 @@
test interpret
target riscv64
function %breduce_b128_b1(b128) -> b1 {
block0(v0: b128):

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@@ -1,5 +1,6 @@
test run
target aarch64
target riscv64
target s390x
function %i128_bricmp_eq(i128, i128) -> b1 {

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@@ -1,5 +1,6 @@
test run
target aarch64
target riscv64
target s390x
function %bxor_not_i128(i128, i128) -> i128 {

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@@ -1,5 +1,6 @@
test run
target aarch64
target riscv64
target s390x
function %cls_i128(i128) -> i128 {

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %iconcat_isplit(i64, i64) -> i64, i64 {
block0(v0: i64, v1: i64):
@@ -15,3 +16,4 @@ block0(v0: i64, v1: i64):
; run: %iconcat_isplit(0xFFFFFFFF_FFFFFFFF, 0) == [0xFFFFFFFF_FFFFFFFF, 0]
; run: %iconcat_isplit(0, 0xFFFFFFFF_FFFFFFFF) == [0, 0xFFFFFFFF_FFFFFFFF]
; run: %iconcat_isplit(0x01010101_01010101, 0x02020202_02020202) == [0x01010101_01010101, 0x02020202_02020202]

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@@ -4,6 +4,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %i128_const_0() -> i128 {
block0:

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@@ -4,6 +4,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %i128_uextend_i64(i64) -> i128 {
block0(v0: i64):

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@@ -4,6 +4,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %icmp_eq_i128(i128, i128) -> b1 {
block0(v0: i128, v1: i128):

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@@ -4,6 +4,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %ireduce_128_64(i128) -> i64 {
block0(v0: i128):

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@@ -4,6 +4,7 @@ set enable_llvm_abi_extensions=true
set enable_probestack=false
target x86_64
target aarch64
target riscv64
target s390x
function %i128_stack_store_load(i128) -> b1 {

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@@ -4,6 +4,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %rotl(i128, i8) -> i128 {
block0(v0: i128, v1: i8):

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@@ -3,6 +3,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %i128_select(b1, i128, i128) -> i128 {
block0(v0: b1, v1: i128, v2: i128):

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@@ -4,7 +4,7 @@ set enable_llvm_abi_extensions=true
target aarch64
target s390x
target x86_64
target riscv64
function %ishl_i128_i128(i128, i8) -> i128 {
block0(v0: i128, v1: i8):

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target s390x
target riscv64
; x86_64 only supports vector iabs
function %iabs_i8(i8) -> i8 {

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@@ -3,6 +3,7 @@ test run
target aarch64
target x86_64
target s390x
target riscv64
function %icmp_imm_eq_i8(i8) -> b1 {
block0(v0: i8):

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target x86_64
target riscv64
target s390x
function %icmp_eq_i8(i8, i8) -> b1 {

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target x86_64
target riscv64
target s390x
function %icmp_ne_i8(i8, i8) -> b1 {

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target x86_64
target riscv64
target s390x

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target x86_64
target riscv64
target s390x

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target x86_64
target riscv64
target s390x

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target x86_64
target riscv64
target s390x
function %icmp_slt_i8(i8, i8) -> b1 {

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target x86_64
target riscv64
target s390x
function %icmp_uge_i8(i8, i8) -> b1 {

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %icmp_ugt_i8(i8, i8) -> b1 {
block0(v0: i8, v1: i8):

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@@ -2,6 +2,7 @@ test interpret
test run
target aarch64
target x86_64
target riscv64
target s390x
function %icmp_ule_i8(i8, i8) -> b1 {

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
; This test is also a regression test for aarch64.
; We were not correctly handling the fact that the rhs constant value

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@@ -3,6 +3,8 @@ test run
; target aarch64
; target s390x
target x86_64
target riscv64
; sort three signed i8s with imin and imax only
function %isort3(i8, i8, i8) -> i8, i8, i8 {

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %ireduce_i16_i8(i16) -> i8 {
block0(v0: i16):

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@@ -2,6 +2,8 @@ test run
target x86_64
target s390x
target aarch64
target riscv64
function %load_op_store_iadd_i64(i64 vmctx, i64, i64) -> i64 {
gv0 = vmctx

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@@ -4,6 +4,7 @@ target x86_64
target x86_64 has_sse41=false
target aarch64
target s390x
target riscv64
function %nearest_f32(f32) -> f32 {
block0(v0: f32):

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@@ -22,3 +22,11 @@ block0(v0: i64x2):
}
; run: %popcnt_i64x2([1 0x4000000000000000]) == [1 1]
; run: %popcnt_i64x2([0xffffffffffffffff 0]) == [64 0]
function %popcnt_i8x16(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = popcnt v0
return v1
}
; run: %popcnt_i8x16([1 1 1 1 0x40 0x40 0x40 0x40 0xff 0xff 0xff 0xff 0 0 0 0]) == [1 1 1 1 1 1 1 1 8 8 8 8 0 0 0 0]

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@@ -4,6 +4,7 @@ target aarch64
target s390x
target x86_64
target x86_64 has_popcnt
target riscv64
function %popcnt_i8(i8) -> i8 {
block0(v0: i8):
@@ -93,9 +94,3 @@ block0(v0: i64):
; run: %inv_popcnt_i64(-1) == 0
; run: %inv_popcnt_i64(0) == 64
function %popcnt_i8x16(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = popcnt v0
return v1
}
; run: %popcnt_i8x16([1 1 1 1 0x40 0x40 0x40 0x40 0xff 0xff 0xff 0xff 0 0 0 0]) == [1 1 1 1 1 1 1 1 8 8 8 8 0 0 0 0]

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@@ -3,7 +3,7 @@ test run
target aarch64
target x86_64
target s390x
target riscv64
function %rotl_i64_i64(i64, i64) -> i64 {
block0(v0: i64, v1: i64):

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@@ -3,6 +3,7 @@ test run
target aarch64
target x86_64
target s390x
target riscv64
function %rotr_i64_i64(i64, i64) -> i64 {

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@@ -3,6 +3,7 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
function %select_eq_f32(f32, f32) -> i32 {
block0(v0: f32, v1: f32):

View File

@@ -3,7 +3,7 @@ test run
target aarch64
target x86_64
target s390x
target riscv64
function %ishl_i64_i64(i64, i64) -> i64 {
block0(v0: i64, v1: i64):

View File

@@ -1,6 +1,7 @@
test interpret
test run
target aarch64
target riscv64
target s390x
; x86_64 backend only supports `i16`, `i32`, and `i64` types.

View File

@@ -4,6 +4,8 @@ target aarch64
target s390x
set enable_simd
target x86_64 has_sse3 has_ssse3 has_sse41
target riscv64
function %smulhi_i16(i16, i16) -> i16 {
block0(v0: i16, v1: i16):

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