Files
wasmtime/cranelift/filetests/filetests/runtests/i128-cls.clif
yuyang-ok cdecc858b4 add riscv64 backend for cranelift. (#4271)
Add a RISC-V 64 (`riscv64`, RV64GC) backend.

Co-authored-by: yuyang <756445638@qq.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
2022-09-27 17:30:31 -07:00

21 lines
756 B
Plaintext

test run
target aarch64
target riscv64
target s390x
function %cls_i128(i128) -> i128 {
block0(v0: i128):
v1 = cls v0
return v1
}
; run: %cls_i128(0x00000000_00000000_00000000_00000000) == 127
; run: %cls_i128(0x00000000_00000000_FFFFFFFF_FFFFFFFF) == 63
; run: %cls_i128(0xFFFFFFFF_FFFFFFFF_00000000_00000000) == 63
; run: %cls_i128(0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 127
; run: %cls_i128(0x7FFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 0
; run: %cls_i128(0x3FFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF) == 1
; run: %cls_i128(0xFFFFFFFF_FFFFFFFF_7FFFFFFF_FFFFFFFF) == 63
; run: %cls_i128(0xC0000000_00000000_80000000_00000000) == 1
; run: %cls_i128(0xC0000000_00000000_00000000_00000000) == 1
; run: %cls_i128(0x80000000_00000000_80000000_00000000) == 0