Add register banks for CPU flags to Intel and ARM ISAs.

The arm32 ISA technically has separate floating point and integer flags,
but the only useful thing you can do with the floating point flags is to
copy them ti the integer flags, so there is not need to model them.

The arm64 ISA fixes this and the fcmp instruction writes the integer
nzcv flags directly.

RISC-V does not have CPU flags.

lib/cretonne/meta/isa/arm32/registers.py

@@ -29,9 +29,17 @@ IntRegs = RegBank(
         'General purpose registers',
         units=16, prefix='r')
 
+FlagRegs = RegBank(
+        'FlagRegs', ISA,
+        'Flag registers',
+        units=1,
+        pressure_tracking=False,
+        names=['nzcv'])
+
 GPR = RegClass(IntRegs)
 S = RegClass(FloatRegs, count=32)
 D = RegClass(FloatRegs, width=2)
 Q = RegClass(FloatRegs, width=4)
+FLAG = RegClass(FlagRegs)
 
 RegClass.extract_names(globals())

lib/cretonne/meta/isa/arm64/registers.py

@@ -18,7 +18,15 @@ FloatRegs = RegBank(
         'Floating point registers',
         units=32, prefix='v')
 
+FlagRegs = RegBank(
+        'FlagRegs', ISA,
+        'Flag registers',
+        units=1,
+        pressure_tracking=False,
+        names=['nzcv'])
+
 GPR = RegClass(IntRegs)
 FPR = RegClass(FloatRegs)
+FLAG = RegClass(FlagRegs)
 
 RegClass.extract_names(globals())

lib/cretonne/meta/isa/intel/registers.py

@@ -38,11 +38,19 @@ FloatRegs = RegBank(
         'SSE floating point registers',
         units=16, prefix='xmm')
 
+FlagRegs = RegBank(
+        'FlagRegs', ISA,
+        'Flag registers',
+        units=1,
+        pressure_tracking=False,
+        names=['eflags'])
+
 GPR = RegClass(IntRegs)
 GPR8 = GPR[0:8]
 ABCD = GPR[0:4]
 FPR = RegClass(FloatRegs)
 FPR8 = FPR[0:8]
+FLAG = RegClass(FlagRegs)
 
 # Constraints for stack operands.
 

lib/cretonne/src/isa/arm64/registers.rs

@@ -32,6 +32,7 @@ mod tests {
         assert_eq!(uname(32), "%v0");
         assert_eq!(uname(33), "%v1");
         assert_eq!(uname(63), "%v31");
-        assert_eq!(uname(64), "%INVALID64");
+        assert_eq!(uname(64), "%nzcv");
+        assert_eq!(uname(65), "%INVALID65");
     }
 }