From 0f4f663584f81509f080b70b1fc10276e862da79 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Fri, 13 Oct 2017 13:45:49 -0700
Subject: [PATCH] Add register banks for CPU flags to Intel and ARM ISAs.

The arm32 ISA technically has separate floating point and integer flags,
but the only useful thing you can do with the floating point flags is to
copy them ti the integer flags, so there is not need to model them.

The arm64 ISA fixes this and the fcmp instruction writes the integer
nzcv flags directly.

RISC-V does not have CPU flags.
---
 lib/cretonne/meta/isa/arm32/registers.py | 8 ++++++++
 lib/cretonne/meta/isa/arm64/registers.py | 8 ++++++++
 lib/cretonne/meta/isa/intel/registers.py | 8 ++++++++
 lib/cretonne/src/isa/arm64/registers.rs  | 3 ++-
 4 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/lib/cretonne/meta/isa/arm32/registers.py b/lib/cretonne/meta/isa/arm32/registers.py
index 9522057e34..054e95fa0e 100644
--- a/lib/cretonne/meta/isa/arm32/registers.py
+++ b/lib/cretonne/meta/isa/arm32/registers.py
@@ -29,9 +29,17 @@ IntRegs = RegBank(
         'General purpose registers',
         units=16, prefix='r')
 
+FlagRegs = RegBank(
+        'FlagRegs', ISA,
+        'Flag registers',
+        units=1,
+        pressure_tracking=False,
+        names=['nzcv'])
+
 GPR = RegClass(IntRegs)
 S = RegClass(FloatRegs, count=32)
 D = RegClass(FloatRegs, width=2)
 Q = RegClass(FloatRegs, width=4)
+FLAG = RegClass(FlagRegs)
 
 RegClass.extract_names(globals())
diff --git a/lib/cretonne/meta/isa/arm64/registers.py b/lib/cretonne/meta/isa/arm64/registers.py
index b39bc917a1..df680b1a14 100644
--- a/lib/cretonne/meta/isa/arm64/registers.py
+++ b/lib/cretonne/meta/isa/arm64/registers.py
@@ -18,7 +18,15 @@ FloatRegs = RegBank(
         'Floating point registers',
         units=32, prefix='v')
 
+FlagRegs = RegBank(
+        'FlagRegs', ISA,
+        'Flag registers',
+        units=1,
+        pressure_tracking=False,
+        names=['nzcv'])
+
 GPR = RegClass(IntRegs)
 FPR = RegClass(FloatRegs)
+FLAG = RegClass(FlagRegs)
 
 RegClass.extract_names(globals())
diff --git a/lib/cretonne/meta/isa/intel/registers.py b/lib/cretonne/meta/isa/intel/registers.py
index 886812d6ce..cbb6701660 100644
--- a/lib/cretonne/meta/isa/intel/registers.py
+++ b/lib/cretonne/meta/isa/intel/registers.py
@@ -38,11 +38,19 @@ FloatRegs = RegBank(
         'SSE floating point registers',
         units=16, prefix='xmm')
 
+FlagRegs = RegBank(
+        'FlagRegs', ISA,
+        'Flag registers',
+        units=1,
+        pressure_tracking=False,
+        names=['eflags'])
+
 GPR = RegClass(IntRegs)
 GPR8 = GPR[0:8]
 ABCD = GPR[0:4]
 FPR = RegClass(FloatRegs)
 FPR8 = FPR[0:8]
+FLAG = RegClass(FlagRegs)
 
 # Constraints for stack operands.
 
diff --git a/lib/cretonne/src/isa/arm64/registers.rs b/lib/cretonne/src/isa/arm64/registers.rs
index 0a0e043a20..d4cee48891 100644
--- a/lib/cretonne/src/isa/arm64/registers.rs
+++ b/lib/cretonne/src/isa/arm64/registers.rs
@@ -32,6 +32,7 @@ mod tests {
         assert_eq!(uname(32), "%v0");
         assert_eq!(uname(33), "%v1");
         assert_eq!(uname(63), "%v31");
-        assert_eq!(uname(64), "%INVALID64");
+        assert_eq!(uname(64), "%nzcv");
+        assert_eq!(uname(65), "%INVALID65");
     }
 }