0f4f663584
The arm32 ISA technically has separate floating point and integer flags, but the only useful thing you can do with the floating point flags is to copy them ti the integer flags, so there is not need to model them. The arm64 ISA fixes this and the fcmp instruction writes the integer nzcv flags directly. RISC-V does not have CPU flags.
62 lines
1.7 KiB
Python
62 lines
1.7 KiB
Python
"""
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Intel register banks.
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While the floating-point registers are straight-forward, the general purpose
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register bank has a few quirks on Intel architectures. We have these encodings
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of the 8-bit registers:
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I32 I64 | 16b 32b 64b
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000 AL AL | AX EAX RAX
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001 CL CL | CX ECX RCX
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010 DL DL | DX EDX RDX
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011 BL BL | BX EBX RBX
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100 AH SPL | SP ESP RSP
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101 CH BPL | BP EBP RBP
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110 DH SIL | SI ESI RSI
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111 BH DIL | DI EDI RDI
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Here, the I64 column refers to the registers you get with a REX prefix. Without
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the REX prefix, you get the I32 registers.
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The 8-bit registers are not that useful since WebAssembly only has i32 and i64
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data types, and the H-registers even less so. Rather than trying to model the
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H-registers accurately, we'll avoid using them in both I32 and I64 modes.
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"""
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from __future__ import absolute_import
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from cdsl.registers import RegBank, RegClass, Stack
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from .defs import ISA
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IntRegs = RegBank(
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'IntRegs', ISA,
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'General purpose registers',
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units=16, prefix='r',
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names='rax rcx rdx rbx rsp rbp rsi rdi'.split())
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FloatRegs = RegBank(
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'FloatRegs', ISA,
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'SSE floating point registers',
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units=16, prefix='xmm')
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FlagRegs = RegBank(
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'FlagRegs', ISA,
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'Flag registers',
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units=1,
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pressure_tracking=False,
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names=['eflags'])
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GPR = RegClass(IntRegs)
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GPR8 = GPR[0:8]
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ABCD = GPR[0:4]
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FPR = RegClass(FloatRegs)
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FPR8 = FPR[0:8]
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FLAG = RegClass(FlagRegs)
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# Constraints for stack operands.
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# Stack operand with a 32-bit signed displacement from either RBP or RSP.
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StackGPR32 = Stack(GPR)
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StackFPR32 = Stack(FPR)
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RegClass.extract_names(globals())
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