0f4f663584
The arm32 ISA technically has separate floating point and integer flags, but the only useful thing you can do with the floating point flags is to copy them ti the integer flags, so there is not need to model them. The arm64 ISA fixes this and the fcmp instruction writes the integer nzcv flags directly. RISC-V does not have CPU flags.
33 lines
756 B
Python
33 lines
756 B
Python
"""
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Aarch64 register banks.
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"""
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from __future__ import absolute_import
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from cdsl.registers import RegBank, RegClass
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from .defs import ISA
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# The `x31` regunit serves as the stack pointer / zero register depending on
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# context. We reserve it and don't model the difference.
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IntRegs = RegBank(
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'IntRegs', ISA,
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'General purpose registers',
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units=32, prefix='x')
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FloatRegs = RegBank(
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'FloatRegs', ISA,
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'Floating point registers',
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units=32, prefix='v')
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FlagRegs = RegBank(
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'FlagRegs', ISA,
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'Flag registers',
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units=1,
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pressure_tracking=False,
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names=['nzcv'])
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GPR = RegClass(IntRegs)
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FPR = RegClass(FloatRegs)
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FLAG = RegClass(FlagRegs)
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RegClass.extract_names(globals())
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