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5faa90a292ea70bd03fe64c36d0183279279edfb
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87 Commits

Author SHA1 Message Date
Alexis Engelke
0521ff7d42 decode: Fix VBLENDVP[SD] opcodes 2021-03-23 12:52:37 +01:00
Alexis Engelke
4f2366afd1 instrs: Add VIA PadLock and AMD RDPRU 2021-01-23 16:47:30 +01:00
Alexis Engelke
f7567c89bd instrs: Fix VMOVSS/VMOVSD with memory operand 2021-01-23 16:44:16 +01:00
Alexis Engelke
e8f440c713 instrs: Minor fix with mandatory prefixes 2021-01-23 16:43:52 +01:00
Alexis Engelke
d7b9c97681 instrs: Remove MPX instructions 
These instructions have plenty of corner cases and some instructions
have a different usage of the memory operand. Given that MPX is already
deprecated by Intel, it seems that the better option is to decode these
(rarely occuring) instructions as NOPs.
 2021-01-23 16:18:12 +01:00
Alexis Engelke
0efd44cc28 instrs: Add some missing opcodes and FPU aliases 2021-01-23 16:17:42 +01:00
Alexis Engelke
103fc536b0 instrs: Fix operands of VRCPPS/VSQRTP[SD]/VRSQRTPS 2021-01-23 14:39:48 +01:00
Alexis Engelke
ab63a3c921 instrs: Fix mandatory prefixes of CMPXCHG8B/16B 2021-01-23 14:30:45 +01:00
Alexis Engelke
85fdaa3a9b instrs: Remove incorrect NFx specifiers 
The new trie implementation is more flexible and allows omitting
prefixes even with a ModRM specifier in the opcode. Use this flexibility
to simplify instruction descriptions.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
62018556a1 parseinstrs: Simplify operand kind parsing 2021-01-23 13:25:23 +01:00
Alexis Engelke
bd611902b0 parseinstrs: Add separate ModRM indicator to desc 
Some instructions have no ModRM operand and no extended opcode but still
consume a ModRM byte.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
cb90c2c54d instr: Add weak NOP for PREFETCH register encoding 2021-01-10 18:54:18 +01:00
Alexis Engelke
80df5ff47c instrs: Add reserved NOP/PREFETCH as weak opcodes 2021-01-10 16:53:27 +01:00
Alexis Engelke
f1e18c208c instrs: Add AMD-only MOVTNSS/MOVNTSD 2021-01-10 16:49:53 +01:00
Alexis Engelke
9245a97248 instrs: Add several AMD-only instructions 
- 3DNow! instructions have a trailing immediate byte which indicates the
  opcode. Decoding this with the existing table structure requires more
  effort (in particular, a new lookup table after decoding ModRM would
  be required). Given that AMD even removed 3DNow! over 10 years ago, it
  appears unlikely that this will ever be fully supported. Adding the
  RMI-encoded pseudo-instruction "3DNOW" just to support that opcode.
- FEMMS is a legacy 3DNow! instruction.
- EXTRQ/INSERTQ are instructions with an "unusual" encoding and
  operation mode. This is another instance of 16-bit immediates.
- SVM (AMD's variant of VMX) and SNP instructions are AMD-only.
 2021-01-10 15:18:44 +01:00
Alexis Engelke
c050b34ff9 instrs: Add support for undocumented instructions 
Undocumented instruction are not decoded by default.

- SALC: undocumented in any recent manual and unsupported by newer
  Intel CPUs. Including as listed by [1,2].
- Undocumented FPU instructions: see [2].

[1]: http://www.rcollins.org/secrets/opcodes/SALC.html
[2]: https://github.com/xoreaxeaxeax/sandsifter/issues/33
 2021-01-10 15:04:37 +01:00
Alexis Engelke
b8decc8064 instrs: Add AMD encoding of SHL/6 and TEST/1 
- SHL (SAL) encoding with /6: this is not documented by Intel and
  documented by AMD as present, but unsupported by tools.
- TEST encoding with /1: undocumented by Intel, documented by AMD.
 2021-01-10 15:03:23 +01:00
Alexis Engelke
fcb39f5cbe instrs: Add support for AESKL/AESKLE 2021-01-10 14:15:14 +01:00
Alexis Engelke
862b6d285c instrs: Minor operand size fixes 2021-01-10 14:13:44 +01:00
Alexis Engelke
d40ee6db66 instrs: Add FLD and fix FUCOMIP instructions 2021-01-10 14:08:29 +01:00
Alexis Engelke
c87264ace3 instrs: Add MMX PSHUFW instruction 2021-01-10 14:02:39 +01:00
Alexis Engelke
dd4263b169 instrs: Support far jumps/calls encoded target 2021-01-10 12:31:07 +01:00
Alexis Engelke
2f295e5476 instrs: Exact register size for scalar VEX ops 2021-01-10 12:15:49 +01:00
Alexis Engelke
96e513c8ea breaking! instrs: Decode VMOVS[SD] loads correctly 
These instruction ignore the VEX operand if the source operand is a
memory location.

API compatibility: separate handling for different operand types in the
second and third operand (REG+REG vs. MEM+NONE) is needed.
 2021-01-10 12:12:26 +01:00
Alexis Engelke
e86ea540b5 instrs: Fixup register decoding for PEXTR* 2021-01-10 12:11:27 +01:00
Alexis Engelke
a81582cc3a breaking! instrs: Decode MOVLHPS/MOVHLPS 
Now that we support different /r and /m encodings on the same opcode, we
can easily identify MOVLHPS/MOVHLPS as different instructions.

API compatibility: existing code can point the new MOVLHPS/MOVHLPS
mnemonics to the existing handler for MOVHPS/MOVLPS.
 2021-01-10 12:11:27 +01:00
Alexis Engelke
111769832f format: Properly output VSIB encodings 2021-01-08 10:37:13 +01:00
Alexis Engelke
d8c7ee94b7 instrs: Minor fixes to operand sizes 2021-01-03 20:08:34 +01:00
Alexis Engelke
d2bf961b77 instrs: Properly handle PUSH/POP of SEG registers 2021-01-03 20:08:34 +01:00
Alexis Engelke
aa1a39bd9d instrs: Check SREG validity using modreg table 2020-11-29 11:56:08 +01:00
Alexis Engelke
7ab5a18cb0 instrs: Fix naming of some FMA instructions 2020-11-28 13:54:51 +01:00
Alexis Engelke
8ab9f641b8 instrs: Add TSXLDTRK, AVX_VNNI, HRESET, and UINTR 2020-11-22 17:36:12 +01:00
Alexis Engelke
ad1f1e39c3 decode: Minor non-functional changes 2020-11-22 15:14:57 +01:00
Alexis Engelke
6fe5500444 instrs: Force RIP access to 64-bit and fix XBEGIN 2020-11-22 15:13:52 +01:00
Alexis Engelke
f9bba6289e instrs: Annotate only-mem and only-reg in opcode 2020-11-22 11:34:55 +01:00
Alexis Engelke
62b0420147 parseinstr: Simplify opcode naming scheme 2020-11-09 09:47:36 +01:00
Alexis Engelke
2e7e396325 decode: Remove TABLE_PREFIX_REP and use NFx prefix 2020-11-09 09:47:36 +01:00
Alexis Engelke
69ce124354 encode: Add library for x86-64 encoding 2020-11-09 09:46:38 +01:00
Alexis Engelke
4e95c8d152 instrs: Several operand size and AVX-related fixes 2020-07-05 14:59:24 +02:00
Alexis Engelke
9d7aeb2b61 instrs: Replace LIG attribute with LIG specifier 2020-07-05 14:57:22 +02:00
Alexis Engelke
dc668691d8 instrs: Specify segment register size 2020-07-04 14:25:22 +02:00
Alexis Engelke
0da46cba98 instrs: Add missing VEXLIG for compares 2020-07-04 14:25:20 +02:00
Alexis Engelke
c9333ac2c9 instrs: Enforce memory for VSIB encodings 2020-07-04 14:24:59 +02:00
Alexis Engelke
141680e77c instrs: Remove MUSTMEM, encode in operands 2020-07-04 14:24:56 +02:00
Alexis Engelke
da4ad137d8 instrs: Remove redundant IMM_8 2020-07-04 08:55:51 +02:00
Alexis Engelke
854082a156 instrs: Remove invalid SIZE_8 markers 2020-07-02 08:39:51 +02:00
Alexis Engelke
7333453a19 instrs: Update several operand types and sizes 2020-06-27 19:01:26 +02:00
Alexis Engelke
3221a319d3 instrs: Don't use O-encoding hack for FSTSW 2020-06-27 17:33:58 +02:00
Alexis Engelke
618d90ed42 instrs: Encode memory size for FPU instructions 2020-06-27 17:33:58 +02:00
Alexis Engelke
bb4b195dbe instrs/sse,avx: Fix several operand sizes 2020-06-25 21:04:10 +02:00