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363698db3bd24edee0c15e8ba3ee8772c65cca87
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Author SHA1 Message Date
Alexis Engelke
363698db3b parseinstrs: Move decode table gen to new function 2021-01-23 13:59:59 +01:00
Alexis Engelke
85fdaa3a9b instrs: Remove incorrect NFx specifiers 
The new trie implementation is more flexible and allows omitting
prefixes even with a ModRM specifier in the opcode. Use this flexibility
to simplify instruction descriptions.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
dc399390a4 parseinstrs: Refactor mapping of opcode to Trie 2021-01-23 13:25:23 +01:00
Alexis Engelke
13a2456458 parseinstrs: Simplify trie implementation 2021-01-23 13:25:23 +01:00
Alexis Engelke
43910a6227 parseinstrs: Avoid redundant encoding of InstrDesc 2021-01-23 13:25:23 +01:00
Alexis Engelke
09d3886577 parseinstrs: Move regtype encoding to InstrDesc 2021-01-23 13:25:23 +01:00
Alexis Engelke
d6278de812 parseinstrs: Use tuples/ints for indexing in trie 
This avoids useless internal string formatting.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
1390bae341 parseinstr: Create optype string in descriptor 
The raw encoding representation is now only used in InstrDesc.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
801fe4bc43 parseinstrs: Generalize immediate size computation 2021-01-23 13:25:23 +01:00
Alexis Engelke
62018556a1 parseinstrs: Simplify operand kind parsing 2021-01-23 13:25:23 +01:00
Alexis Engelke
bd611902b0 parseinstrs: Add separate ModRM indicator to desc 
Some instructions have no ModRM operand and no extended opcode but still
consume a ModRM byte.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
8561d77c91 format: Minor non-functional changes 2021-01-10 18:55:05 +01:00
Alexis Engelke
cb90c2c54d instr: Add weak NOP for PREFETCH register encoding 2021-01-10 18:54:18 +01:00
Alexis Engelke
9d7b584121 decode: Verify 3DNow! opcode validity 2021-01-10 18:53:32 +01:00
Alexis Engelke
80df5ff47c instrs: Add reserved NOP/PREFETCH as weak opcodes 2021-01-10 16:53:27 +01:00
Alexis Engelke
f1e18c208c instrs: Add AMD-only MOVTNSS/MOVNTSD 2021-01-10 16:49:53 +01:00
Alexis Engelke
1458bf9673 encode: Support VEX-encoded instructions 2021-01-10 16:03:40 +01:00
Alexis Engelke
9245a97248 instrs: Add several AMD-only instructions 
- 3DNow! instructions have a trailing immediate byte which indicates the
  opcode. Decoding this with the existing table structure requires more
  effort (in particular, a new lookup table after decoding ModRM would
  be required). Given that AMD even removed 3DNow! over 10 years ago, it
  appears unlikely that this will ever be fully supported. Adding the
  RMI-encoded pseudo-instruction "3DNOW" just to support that opcode.
- FEMMS is a legacy 3DNow! instruction.
- EXTRQ/INSERTQ are instructions with an "unusual" encoding and
  operation mode. This is another instance of 16-bit immediates.
- SVM (AMD's variant of VMX) and SNP instructions are AMD-only.
 2021-01-10 15:18:44 +01:00
Alexis Engelke
51072cac9c format: Generalize ENTER/JMPF/CALLF op. formatting 2021-01-10 15:15:30 +01:00
Alexis Engelke
c050b34ff9 instrs: Add support for undocumented instructions 
Undocumented instruction are not decoded by default.

- SALC: undocumented in any recent manual and unsupported by newer
  Intel CPUs. Including as listed by [1,2].
- Undocumented FPU instructions: see [2].

[1]: http://www.rcollins.org/secrets/opcodes/SALC.html
[2]: https://github.com/xoreaxeaxeax/sandsifter/issues/33
 2021-01-10 15:04:37 +01:00
Alexis Engelke
b8decc8064 instrs: Add AMD encoding of SHL/6 and TEST/1 
- SHL (SAL) encoding with /6: this is not documented by Intel and
  documented by AMD as present, but unsupported by tools.
- TEST encoding with /1: undocumented by Intel, documented by AMD.
 2021-01-10 15:03:23 +01:00
Alexis Engelke
fcb39f5cbe instrs: Add support for AESKL/AESKLE 2021-01-10 14:15:14 +01:00
Alexis Engelke
862b6d285c instrs: Minor operand size fixes 2021-01-10 14:13:44 +01:00
Alexis Engelke
d40ee6db66 instrs: Add FLD and fix FUCOMIP instructions 2021-01-10 14:08:29 +01:00
Alexis Engelke
c87264ace3 instrs: Add MMX PSHUFW instruction 2021-01-10 14:02:39 +01:00
Alexis Engelke
dd4263b169 instrs: Support far jumps/calls encoded target 2021-01-10 12:31:07 +01:00
Alexis Engelke
2f295e5476 instrs: Exact register size for scalar VEX ops 2021-01-10 12:15:49 +01:00
Alexis Engelke
96e513c8ea breaking! instrs: Decode VMOVS[SD] loads correctly 
These instruction ignore the VEX operand if the source operand is a
memory location.

API compatibility: separate handling for different operand types in the
second and third operand (REG+REG vs. MEM+NONE) is needed.
 2021-01-10 12:12:26 +01:00
Alexis Engelke
e86ea540b5 instrs: Fixup register decoding for PEXTR* 2021-01-10 12:11:27 +01:00
Alexis Engelke
a81582cc3a breaking! instrs: Decode MOVLHPS/MOVHLPS 
Now that we support different /r and /m encodings on the same opcode, we
can easily identify MOVLHPS/MOVHLPS as different instructions.

API compatibility: existing code can point the new MOVLHPS/MOVHLPS
mnemonics to the existing handler for MOVHPS/MOVLPS.
 2021-01-10 12:11:27 +01:00
Alexis Engelke
af9188e267 parseinstrs: Respect mem-only/reg-only encodings 2021-01-10 12:02:58 +01:00
Alexis Engelke
111769832f format: Properly output VSIB encodings 2021-01-08 10:37:13 +01:00
Alexis Engelke
018a954b4c encode: Use macro for OPC_SEG mask 2021-01-07 10:20:00 +01:00
Alexis Engelke
dfb28c923d encode: Make internal escape encoding more compact 2021-01-07 10:03:58 +01:00
Alexis Engelke
3fdbd70153 encode: Fix erroneous encoding of high registers 2021-01-07 10:03:17 +01:00
Alexis Engelke
db183ee6f9 meson: Check compiler options and Python version 
Thanks to William Woodruff for pointing out that -Wcast-align=strict is
a GCC-only option, which causes build errors (instead of just
complaining about an unsupported warning option).
 2021-01-05 20:21:44 +01:00
Alexis Engelke
84645afaac README: Add API for encoder 2021-01-03 21:23:24 +01:00
Alexis Engelke
aefab34927 README: Update and include encoder 2021-01-03 21:19:36 +01:00
Alexis Engelke
44808e7b1a format: Format instructions with Intel syntax 2021-01-03 21:18:57 +01:00
Alexis Engelke
d8c7ee94b7 instrs: Minor fixes to operand sizes 2021-01-03 20:08:34 +01:00
Alexis Engelke
d2bf961b77 instrs: Properly handle PUSH/POP of SEG registers 2021-01-03 20:08:34 +01:00
Alexis Engelke
3a3a284f6f parseinstrs: Improve performance 2021-01-03 20:08:34 +01:00
Alexis Engelke
5a77c0e6eb parseinstrs: Use suffix tree to reduce mnem size 
This brings slight size improvements, although due to SSE/MMX
instruction name prefixes, benefits are rather small (~50 bytes).
 2021-01-03 20:08:30 +01:00
Alexis Engelke
e82c9e20db build: Simplify 2021-01-02 16:27:28 +01:00
Alexis Engelke
90cce987f0 decode: Remove use of ARCH_* macros 2021-01-02 16:25:25 +01:00
Alexis Engelke
64a9984fa0 format: Add function fdi_name 2020-12-12 16:24:17 +01:00
Alexis Engelke
305eb9d568 decode: Inline ModRM decoding 
This is a preparation for further changes to that routine.
 2020-11-29 13:34:16 +01:00
Alexis Engelke
aa1a39bd9d instrs: Check SREG validity using modreg table 2020-11-29 11:56:08 +01:00
Alexis Engelke
13e7e27640 decode: Minor non-functional changes 2020-11-29 10:03:11 +01:00
Alexis Engelke
7ab5a18cb0 instrs: Fix naming of some FMA instructions 2020-11-28 13:54:51 +01:00