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Author SHA1 Message Date
T0b1
9263c3d6b2 wasm support 2023-04-28 20:41:17 +02:00
Alexis Engelke
e2480e9f85 instrs: Fix VMOVD_G2X with W1 in 32-bit mode 2023-04-24 22:21:00 +02:00
Alexis Engelke
6abc971576 decode: Move instr-width to legacy path 
Very few instructions set use instrwidth, so move this check as well to
the legacy path. The only affected common instructions are RET and
LEAVE.
 2023-04-24 08:55:56 +02:00
Alexis Engelke
48f886e130 decode: Group all VSIB handling in single branch 
Most instructions don't use VSIB encoding, so move all VSIB-related
handling to a single block behind a single branch.
 2023-04-23 11:55:45 +02:00
Alexis Engelke
1290e9f094 decode: Group all EVEX-handling for ModRM operands 
Most instructions aren't EVEX-encoded, so hide all uncommon paths behind
a single branch.
 2023-04-23 11:29:34 +02:00
Alexis Engelke
bbc1b0b648 decode: Use macros for all desc accesses [NFC] 2023-04-23 08:57:08 +02:00
Alexis Engelke
8dad665751 encode: Fix unhelpful warning [NFC] 2023-04-23 08:57:08 +02:00
Alexis Engelke
247acd6221 decode: Unify VEX opcode escape extraction 2023-04-23 08:57:08 +02:00
Alexis Engelke
239be46d4a format: Fix out-of-bounds reads for strings 2023-04-23 08:57:08 +02:00
Alexis Engelke
0297f66de6 decode-test: Add VPEXTRB sil case 2023-04-23 08:57:08 +02:00
Alexis Engelke
0a36604c81 decode: Change REP flag values 
The new values allow for a more optimizable computation of the required
flags from the decoded prefix.
 2023-04-23 08:57:08 +02:00
Alexis Engelke
538708cd21 decode: Change encoding of T16 index 
This encoding change saves a shift for the "is register" part.
 2023-04-23 08:57:08 +02:00
Alexis Engelke
c5f5fa1f75 decode: Simplify ModRM reg vs. mem distiction 2023-04-23 08:57:08 +02:00
Alexis Engelke
513cc709a4 decode: Handle GPH, NOP and 3DNow in legacy block 2023-04-23 08:57:08 +02:00
Alexis Engelke
dac2ff1987 decode: Encode trie node kind in 2 bits 2023-04-23 08:57:08 +02:00
Alexis Engelke
e1084be859 decode: Encode prefixes in trie 
This allows to handle unescaped opcodes with a single table lookup.
 2023-04-23 08:57:08 +02:00
Alexis Engelke
a34cd9d2aa parseinstrs: Verify more x86 constraints 2023-04-23 08:57:08 +02:00
Alexis Engelke
e247ead397 parseinstrs: Minor refactoring of trie entries 2023-04-23 08:57:08 +02:00
Alexis Engelke
262370046c decode: Optimize handling of immediates 2023-04-23 08:57:08 +02:00
Alexis Engelke
957537651e decode: Optimize decoding of shift operands 2023-04-23 08:57:08 +02:00
Alexis Engelke
3de8490e0c decode-test: Add more partial test cases 2023-04-23 08:57:08 +02:00
Alexis Engelke
d679578b60 encode-test: Fix ADD mnemonic 2023-03-12 18:59:49 +01:00
Alexis Engelke
0b881e21dc format: Fix 64-bit immediate on 32-bit platforms 2023-03-12 17:10:01 +01:00
Alexis Engelke
49f5b7b338 decode: Implement 16-bit ModRM decoding 2023-02-16 09:14:34 +01:00
Alexis Engelke
2c21073379 decode: Faster prefix decoder 
This improves decoding performance by ~5%.
 2023-01-21 12:30:00 +01:00
Alexis Engelke
b48495805e decode: Minor tweaks for performance 2023-01-15 13:47:11 +01:00
Alexis Engelke
955f139025 instrs: Add AVX512-FP16 instructions 2023-01-15 13:47:11 +01:00
Alexis Engelke
8550e2cac9 parseinstrs: Add support for BCST16 
2-byte broadcasts cannot be inferred from the encoding and need to be
indicated in the descriptor.
 2023-01-15 13:47:11 +01:00
Alexis Engelke
06832825ec fadec: Store broadcast size in segment 
This is a preparation for AVX512-FP16, where the broadcast size is not
just 32/64 bit depending solely on EVEX.W, but can also be 16 bit (with
EVEX.W=0). The broadcast size therefore needs two bits, but the evex
field only had one free bit left. Store broadcast size with the segment
for now. (This is not a good fit and is likely to change at some point.)
 2023-01-15 13:47:11 +01:00
Alexis Engelke
a3c8848005 instrs: Remove unused WIG specifier 
If REX.W/VEX.W/EVEX.W is not used as opcode extension or as operand
size, it is ignored automatically. No need to encode this.
 2023-01-15 13:47:11 +01:00
Alexis Engelke
b1f7a5fe19 decode: Add UD for EVEX.z without EVEX.aaa 
This was tested on hardware, where EVEX.z without EVEX.aaa reliably
causes #UD. The SDM is not too precise about this.
 2023-01-15 13:47:11 +01:00
Alexis Engelke
e04aff73dc decode: Add AVX-512 support 2023-01-15 13:47:11 +01:00
Alexis Engelke
ec5a430b5c decode: Decode EVEX prefix 2023-01-15 13:40:51 +01:00
Alexis Engelke
4a552feabf decode-test: Increase coverage 2023-01-15 13:38:40 +01:00
Alexis Engelke
36c37186dd encode-test: Test all REX/VEX.RXB combinations 2023-01-15 13:38:28 +01:00
Alexis Engelke
7b2a586449 parseinstrs: Fix erroneous 16-bit operand size 2023-01-15 11:24:35 +01:00
Alexis Engelke
d7aff5de28 format: Fix clz for 32-bit targets 2023-01-15 11:09:40 +01:00
Alexis Engelke
2f7e8dd0de encode: Remove descriptor table 
All relevant information is now encoded directly in the numeric value of
the mnemonic, significantly shrinking the size of the encoder.
 2023-01-15 11:09:40 +01:00
Alexis Engelke
9f0ddeb44a encode: Fix [LMS]FENCE encoding 2023-01-13 14:25:55 +01:00
Alexis Engelke
cbbfd9da0e instrs: Fix minor (currently ignored) annotations 2022-12-28 12:28:22 +01:00
Alexis Engelke
36019517cf parseinstrs: Print stats only if not subproject 
Statistics are only interesting for development.
 2022-12-28 12:28:22 +01:00
Alexis Engelke
6bf96d6963 parseinstrs: Improve performance of superstring 
This algorithm yields slightly worse results, but is substantially
faster for larger string counts.
 2022-12-28 12:28:22 +01:00
Alexis Engelke
771d968165 instrs: Fix wrong operand sizes caused by byte imm 2022-12-27 19:46:58 +01:00
Alexis Engelke
377e362a0e decode: Handle imm_byte size differently 
For byte-sized immediates, there are only two options for the operand
size: byte and the instruction's operand size. This knowledge allows to
remove the byte constraint from the set of fixed operand sizes.
 2022-12-27 19:46:04 +01:00
Alexis Engelke
1aec30cd0f instrs: Various small fixes 2022-12-26 22:01:11 +01:00
Alexis Engelke
94fc7a3671 instrs: Fix CLRSSBSY operand size 2022-12-26 19:30:14 +01:00
Alexis Engelke
6a0db935f5 instrs: Remove non-existent VEX-encoded VPSRAVQ 2022-12-26 18:42:15 +01:00
Alexis Engelke
4efe60ffa8 instrs: Fix VMWRITE operand order 2022-12-26 18:42:15 +01:00
Alexis Engelke
e70118a0d7 instrs: Fix VPSRA/VPSRL/VPSLL r/m operand size 2022-12-03 15:06:54 +01:00
Alexis Engelke
003a11ff12 instrs: Fix VMASKMOVDQU encoding 2022-12-03 14:58:06 +01:00