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Author SHA1 Message Date
Alexis Engelke
e5cdc57743 parseinstrs: Minor simplification 2021-09-13 17:43:12 +02:00
Alexis Engelke
bf0425f057 decode: Expose immediate in RVMR encodings 
The AMD64 instructions VPERMIL2PS and VPERMIL2PD (currently not
supported) encode a fifth immediate operand in the lower bits of the
re-purposed immediate. Expose this value in any case so that no
information gets lost during decoding.
 2021-09-13 17:38:24 +02:00
Alexis Engelke
7229f13742 parseinstrs: Don't generate 16-bit version for I66 2021-09-13 17:28:49 +02:00
Alexis Engelke
effc0c7e49 parseinstrs: Fold trie layers with only one child 2021-09-13 17:27:47 +02:00
Alexis Engelke
71c0daf581 instrs: Change operand format 
This changes the instruction description format:

- Use Intel/AMD terminology for describing operands (where applicable)
- Group instructions by ISA extension
- Indicate read/written status flags
 2021-09-13 17:26:43 +02:00
Alexis Engelke
e41d6c26f8 parseinstrs: Make superstring function generic 2021-09-11 13:19:17 +02:00
Alexis Engelke
1fcacdeda7 parseinstrs: Optimize mnemonic compression 
As the formatter no longer demands a null-terminated string, mnemonics
can arbitarily overlap and therefore save space.

This is the shortest superstring problem, which is NP-hard. This is
currently approximated with a greedy heuristic.
 2021-09-11 13:05:34 +02:00
Alexis Engelke
e164803037 instrs: Support FRED instructions 2021-06-13 16:01:03 +02:00
Alexis Engelke
7df4c9542f format: Reduce size of register name table 2021-06-13 15:59:44 +02:00
Alexis Engelke
99a1fbeee1 format: Major refactoring for performance 2021-05-30 14:25:38 +02:00
Alexis Engelke
50f052488d decode: More precise register types 2021-04-02 17:20:23 +02:00
Alexis Engelke
d67eb93148 general: Improve documentation 2021-04-02 11:31:28 +02:00
Alexis Engelke
c99e860a5e tests: Add few more encode/decode cases 2021-04-02 11:28:13 +02:00
Alexis Engelke
4185d7b2d6 encode: Support FD/TD encodings 2021-04-02 11:26:12 +02:00
Alexis Engelke
fa52782e76 encode: Enforce 15-byte limit 2021-04-02 11:00:24 +02:00
Alexis Engelke
d9183228d0 encode: Actually encode LOCK prefix 2021-04-02 10:59:06 +02:00
Alexis Engelke
2d9587bc16 encode: Fix encoding of memory operand 
When a modrm_idx is used without a ModRM being present, the encoder
attempted to encode memory operands using O/OA/AO encodings.
 2021-04-02 10:54:04 +02:00
Alexis Engelke
51ffe2598e ci: Fix GitHub CI 2021-03-28 15:17:35 +02:00
Alexis Engelke
cf8d1be15f encode: Fix erroneous encoding of SREG push/pop 2021-03-23 13:25:30 +01:00
Alexis Engelke
5faa90a292 encode: Support RVMR encoding 2021-03-23 12:55:43 +01:00
Alexis Engelke
0521ff7d42 decode: Fix VBLENDVP[SD] opcodes 2021-03-23 12:52:37 +01:00
Alexis Engelke
b5994b2f2d ci: Add build description for builds.sr.ht 2021-02-06 12:44:24 +01:00
Alexis Engelke
4f2366afd1 instrs: Add VIA PadLock and AMD RDPRU 2021-01-23 16:47:30 +01:00
Alexis Engelke
f7567c89bd instrs: Fix VMOVSS/VMOVSD with memory operand 2021-01-23 16:44:16 +01:00
Alexis Engelke
e8f440c713 instrs: Minor fix with mandatory prefixes 2021-01-23 16:43:52 +01:00
Alexis Engelke
d7b9c97681 instrs: Remove MPX instructions 
These instructions have plenty of corner cases and some instructions
have a different usage of the memory operand. Given that MPX is already
deprecated by Intel, it seems that the better option is to decode these
(rarely occuring) instructions as NOPs.
 2021-01-23 16:18:12 +01:00
Alexis Engelke
0efd44cc28 instrs: Add some missing opcodes and FPU aliases 2021-01-23 16:17:42 +01:00
Alexis Engelke
103fc536b0 instrs: Fix operands of VRCPPS/VSQRTP[SD]/VRSQRTPS 2021-01-23 14:39:48 +01:00
Alexis Engelke
f17d84cee6 format: Emit XACQUIRE/XRELEASE 
As CMPXCHGD has a mandatory prefix table, it is absolutely necessary
that the presence of any tables does not modify any decoding state.
 2021-01-23 14:35:08 +01:00
Alexis Engelke
ab63a3c921 instrs: Fix mandatory prefixes of CMPXCHG8B/16B 2021-01-23 14:30:45 +01:00
Alexis Engelke
7919b8115a format: Emit REP/REPNZ only for string instruction 2021-01-23 14:29:29 +01:00
Alexis Engelke
fe68dbb743 decode: Fix LOCK handling for MOV CR/DR 2021-01-23 14:28:27 +01:00
Alexis Engelke
95371637ea format: Add names for bound registers 2021-01-23 14:05:42 +01:00
Alexis Engelke
363698db3b parseinstrs: Move decode table gen to new function 2021-01-23 13:59:59 +01:00
Alexis Engelke
85fdaa3a9b instrs: Remove incorrect NFx specifiers 
The new trie implementation is more flexible and allows omitting
prefixes even with a ModRM specifier in the opcode. Use this flexibility
to simplify instruction descriptions.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
dc399390a4 parseinstrs: Refactor mapping of opcode to Trie 2021-01-23 13:25:23 +01:00
Alexis Engelke
13a2456458 parseinstrs: Simplify trie implementation 2021-01-23 13:25:23 +01:00
Alexis Engelke
43910a6227 parseinstrs: Avoid redundant encoding of InstrDesc 2021-01-23 13:25:23 +01:00
Alexis Engelke
09d3886577 parseinstrs: Move regtype encoding to InstrDesc 2021-01-23 13:25:23 +01:00
Alexis Engelke
d6278de812 parseinstrs: Use tuples/ints for indexing in trie 
This avoids useless internal string formatting.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
1390bae341 parseinstr: Create optype string in descriptor 
The raw encoding representation is now only used in InstrDesc.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
801fe4bc43 parseinstrs: Generalize immediate size computation 2021-01-23 13:25:23 +01:00
Alexis Engelke
62018556a1 parseinstrs: Simplify operand kind parsing 2021-01-23 13:25:23 +01:00
Alexis Engelke
bd611902b0 parseinstrs: Add separate ModRM indicator to desc 
Some instructions have no ModRM operand and no extended opcode but still
consume a ModRM byte.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
8561d77c91 format: Minor non-functional changes 2021-01-10 18:55:05 +01:00
Alexis Engelke
cb90c2c54d instr: Add weak NOP for PREFETCH register encoding 2021-01-10 18:54:18 +01:00
Alexis Engelke
9d7b584121 decode: Verify 3DNow! opcode validity 2021-01-10 18:53:32 +01:00
Alexis Engelke
80df5ff47c instrs: Add reserved NOP/PREFETCH as weak opcodes 2021-01-10 16:53:27 +01:00
Alexis Engelke
f1e18c208c instrs: Add AMD-only MOVTNSS/MOVNTSD 2021-01-10 16:49:53 +01:00
Alexis Engelke
1458bf9673 encode: Support VEX-encoded instructions 2021-01-10 16:03:40 +01:00