T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
2,919 Commits 2 Branches 0 Tags
0eb2dfc4a39f4441ca1b6e12a58c53425f95e6cb
Commit Graph

2919 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Benjamin Bouvier
0eb2dfc4a3 [meta] Rename OperandKind::default_member to format_field_name; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
4f5b0689f3 [meta] Remove OperandKind::imm_name method; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
ae3ea47dbd [meta] Delegate finding the default value to OperandKind instead of its builder. 
This applies both to the default_member value (which is now determined at
runtime, instead of pre-computed) and the rust_type value (which is
determined in the Operand's ctor, instead of the builder).
 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
4632d35196 [meta] Remove the OperandBuilder, replace it with Operand ctors; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
2bebc40c16 [meta] Move the doc() default values in the Operand/OperandKind; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
0b8a579943 Fixes #851: Document instructions' input operands in InstBuilder; 2019-10-30 18:39:20 +01:00
Josh Triplett
fcf0ad1d5d Log function definition unconditionally 
Don't log inside the `.map_err` call, which resulted in only logging
function definitions on codegen errors.
 2019-10-30 15:55:26 +01:00
bjorn3
689771caf3 Don't force enable basic-blocks feature 
Fixes #1179
 2019-10-30 11:22:05 +01:00
lzutao
7e5c33a29e Use array::iter 2019-10-30 09:47:25 +01:00
Benjamin Bouvier
e8c03fbd09 [meta] Remove unused bit-vector functionalty; 
It can be resurrected if needed in the future. It was used only for the
semantics descriptions, which went away with the transition of the
meta-language to Rust.
 2019-10-29 14:23:10 +01:00
Benjamin Bouvier
5889dd2c64 [meta] Add more pub(crate) definitions. 2019-10-29 14:23:10 +01:00
Benjamin Bouvier
06b1817d89 [meta] Rename Operand::is_pure_immediate into is_immediate; 2019-10-29 14:23:10 +01:00
Benjamin Bouvier
b657aa57f6 [meta] Rename Operand::is_immediate to is_immediate_or_entityref 2019-10-29 14:23:10 +01:00
Andrew Brown
f37d1c7ecc Simplify binding of IntCC::Equals to SIMD icmp; fixes #1150 2019-10-28 11:09:37 -07:00
Joshua Nelson
e045a6df27 implement Debug for Linkage 
this would have been useful while debugging something in my own project
 2019-10-28 11:43:15 +01:00
Peter Huene
9f506692c2 Fix clippy warnings. 
This commit fixes the current set of (stable) clippy warnings in the repo.
 2019-10-24 17:20:12 -07:00
yjh
1176e4f178 Fix clippy warnings (#1168) 2019-10-24 09:54:31 -06:00
Benjamin Bouvier
2b6ea31621 [wasm] Include more large tests; 2019-10-23 10:15:49 +02:00
Andrew Brown
77035b44a6 Translate WASM all_true to CLIF 2019-10-22 11:01:05 -07:00
Andrew Brown
879ccf871a Add x86 SIMD vall_true 
In order to implement SIMD's all_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#all-lanes-true), we must legalize some instruction (I chose `vall_true`) to a comparison against 0 and a similar reduction as vany_true using `PTEST` and `SETNZ`. Since `icmp` only allows integers but `vall_true` could allow more vector types, `raw_bitcast` is used to convert the lane types into integers, e.g. b32x4 to i32x4. To do so without runtime type-checking, the `raw_bitcast` instruction (which emits no instruction) can now bitcast from any vector type to the same type, e.g. i32x4 to i32x4.
 2019-10-22 11:01:05 -07:00
Andrew Brown
65e18df12f Translate WASM any_true to CLIF 2019-10-22 11:01:05 -07:00
Andrew Brown
186effc420 Add x86 SIMD vany_true and x86_ptest 
In order to implement SIMD's any_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#any-lane-true), we must legalize some instruction (I chose `vany_true`) to a sequence of `PTEST` and `SETNZ`. To emit `PTEST` I added the new CLIF instruction `x86_ptest` and used CLIF's `trueif ne` for `SETNZ`.
 2019-10-22 11:01:05 -07:00
Benjamin Bouvier
873465e7a9 [contribution] Update contribution guidelines. 2019-10-22 15:33:09 +02:00
Benjamin Bouvier
499413dbc4 [contribution] Add a pull request template. 2019-10-22 15:33:09 +02:00
Benjamin Bouvier
f721821bec [contribution] Add Github issue templates; 2019-10-22 15:33:09 +02:00
Benjamin Bouvier
0243b642e3 [meta] Remove name lookups in formats; 
This does a lot at once, since there was no clear way to split the three
commits:

- Instruction need to be passed an explicit InstructionFormat,
- InstructionFormat deduplication is checked once all entities have been
defined;
 2019-10-22 14:05:12 +02:00
Benjamin Bouvier
9e9a7626d7 [meta] Use a ref-counted pointer to an InstructionFormat in instructions; 
This avoids a lot of dereferences, and InstructionFormat are immutable
once they're created. It removes a lot of code that was keeping the
FormatRegistry around, just in case we needed the format. This is more
in line with the way we create Instructions, and make it easy to
reference InstructionFormats in general.
 2019-10-22 14:05:12 +02:00
Benjamin Bouvier
d3e694fbe7 [meta] Remove unused InstructionGroup::{name, doc}; 2019-10-22 14:05:12 +02:00
Benjamin Bouvier
8fece43aa1 [meta] Use a type alias for Instruction; 
... instead of embedding a Rc<InstructionContent>, just make it a type
alias.
 2019-10-22 14:05:12 +02:00
Benjamin Bouvier
d102bf9b61 Add allow(dead_code) for Immediate until it's used in legalization patterns; (#1157) 2019-10-18 08:05:01 -06:00
Andrew Brown
135f9eb4a6 Translate WASM bitselect to CLIF 2019-10-17 15:49:29 -07:00
Andrew Brown
b927c55511 Add SIMD bitselect instruction and x86 legalization 
This new instructions matches the `bitselect` behavior described in the WASM SIMD spec (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-select)
 2019-10-17 15:49:29 -07:00
Andrew Brown
8f74333662 Add x86 SIMD band_not 2019-10-17 15:49:29 -07:00
Sean Stangl
fad6bb1a5c Fix build by marking tests as incompatible with basic-blocks. Closes #1152 2019-10-17 12:00:22 -07:00
Sean Stangl
46b44ad82d Increase legibility of the SSABuilder (#1142) 2019-10-17 11:30:38 -06:00
Benjamin Bouvier
a3f55cdf1f Regalloc solver: check that a variable doesn't exist to test if it can be added (fixes #1123); 
This situation could be triggered that can_add_var would return true
while a variable was already added for the given register.

For instance, when we have a reassignment (because of a fixed register
input requirement) and a fixed input conflict on the same fixed
register, this register will not be available in the regs_in set after
inputs_done (because of the fixed input conflict diversion) but will
have its own variable.
 2019-10-17 08:42:08 -07:00
Benjamin Bouvier
beca77c2f8 Regalloc: rename "constraint" to "rc" and "op" to "constraint"; 2019-10-17 08:42:08 -07:00
dependabot-preview[bot]
05cc8823c2 Update raw-cpuid requirement from 6.0.0 to 7.0.3 
Updates the requirements on [raw-cpuid](https://github.com/gz/rust-cpuid) to permit the latest version.
- [Release notes](https://github.com/gz/rust-cpuid/releases)
- [Commits](https://github.com/gz/rust-cpuid/compare/6.0...7.0.3)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
 2019-10-17 17:15:21 +02:00
Nicolas B. Pierron
69d2f40c10 Fix #796: Enable basic-blocks by default. 2019-10-17 14:00:40 +02:00
Nicolas B. Pierron
7c31ce40c4 i128-isplit-forward-jump.clif: BB conditional branches can only be followed by a jump statement. 2019-10-17 13:59:04 +02:00
dependabot-preview[bot]
e15b720d56 Update indicatif requirement from 0.11.0 to 0.12.0 
Updates the requirements on [indicatif](https://github.com/mitsuhiko/indicatif) to permit the latest version.
- [Release notes](https://github.com/mitsuhiko/indicatif/releases)
- [Commits](https://github.com/mitsuhiko/indicatif/compare/0.11.0...0.12.0)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
 2019-10-16 12:29:14 +02:00
Andrew Brown
19a980363e Translate WASM shr to CLIF sshr and ushr 
As with shift left, the spec requires that the shift count is computed modulo the lane width (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#left-shift-by-scalar).
 2019-10-15 15:51:50 -07:00
Andrew Brown
f1904bffea Add x86 SIMD sshr and ushr 
Only the shifts with applicable SSE2 instructions are implemented here: PSRL* (for ushr) only has 16-64 bit instructions and PSRA* (for sshr) only has 16-32 bit instructions.
 2019-10-15 15:51:50 -07:00
Andrew Brown
808885ce56 Translate WASM shl to CLIF ishl 
Note how, according to the spec (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#left-shift-by-scalar), the shift count is computed modulo the lane width. E.g., a shift count of 17 on an i16x8 should not result in all zeroes as it does with Cranelift's `ishl` and x86's `PSSLW`--it should shift once to the left.
 2019-10-15 15:51:50 -07:00
Andrew Brown
6460fe705f Add x86 SIMD ishl 
Only the shifts with applicable SSE2 instructions (i.e. 16-64 bit width) are implemented here.
 2019-10-15 15:51:50 -07:00
Andrew Brown
67733bd2fc Use ConstantData exclusively for inserting data into the constant pool 
Previously we allowed anything that could be converted into ConstantData (e.g. a Vec).
 2019-10-15 15:19:00 -07:00
Andrew Brown
a69b0fc221 Change match_literals_to_uimm128 to match_literals_to_constant_data 2019-10-15 15:19:00 -07:00
Andrew Brown
ff93564c55 Update predicate documentation to match new ConstantData parameter 2019-10-15 15:19:00 -07:00
Andrew Brown
a03f905d08 Replace V128Imm functionality with ConstantData 
This moves most original uses of V128Imm (e.g. in parsing) to ConstantData and shifts the unit tests from V128Imm to ConstantData.
 2019-10-15 15:19:00 -07:00
Andrew Brown
1600dba634 Make ConstantData a container for any-size constant values 
Previously, ConstantData was a type alias for `Vec<u8>` which prevented it from having an implementation; this meant that `V128Imm` and `&[u8; 16]` were used in places that otherwise could have accepted types of different byte lengths.
 2019-10-15 15:19:00 -07:00