Andrew Brown f1904bffea Add x86 SIMD sshr and ushr ...

Only the shifts with applicable SSE2 instructions are implemented here: PSRL* (for ushr) only has 16-64 bit instructions and PSRA* (for sshr) only has 16-32 bit instructions.

2019-10-15 15:51:50 -07:00

cranelift

Add x86 SIMD sshr and ushr

2019-10-15 15:51:50 -07:00

.azure-pipelines.yml

[ci] Disable cargo fuzz on macos nightly;

2019-10-15 14:33:50 +02:00

Description

No description provided

125 MiB

Languages

Rust 77.8%

WebAssembly 20.6%

C 1.3%