Add adjust_sp_imm instruction. Note: This enables using rsp and rbp as normal registers. Which is... wrong.

lib/cretonne/meta/base/formats.py

@@ -69,6 +69,7 @@ RegSpill = InstructionFormat(
         VALUE, ('src', regunit), ('dst', entities.stack_slot))
 RegFill = InstructionFormat(
         VALUE, ('src', entities.stack_slot), ('dst', regunit))
+AdjustSpImm = InstructionFormat(offset32)
 
 Trap = InstructionFormat(trapcode)
 CondTrap = InstructionFormat(VALUE, trapcode)

lib/cretonne/meta/base/instructions.py

@@ -544,6 +544,14 @@ copy_special = Instruction(
         ins=(src, dst),
         other_side_effects=True)
 
+Offset = Operand('Offset', offset32, 'Offset from current stack pointer')
+adjust_sp_imm = Instruction(
+    'adjust_sp_imm', r"""
+    Adds an immediate offset value to the stack pointer register.
+    """,
+    ins=(Offset,),
+    other_side_effects=True)
+
 regspill = Instruction(
         'regspill', r"""
         Temporarily divert ``x`` from ``src`` to ``SS``.

lib/cretonne/meta/isa/intel/encodings.py

@@ -234,7 +234,10 @@ I64.enc(x86.pop.i64, *r.popq.rex(0x58))
 I64.enc(x86.pop.i64, *r.popq(0x58))
 
 # Copy Special
-I64.enc(base.copy_special, *r.copysp.rex(0x89))
+I64.enc(base.copy_special, *r.copysp.rex(0x89, w=1))
+
+# Adjust SP Imm
+I64.enc(base.adjust_sp_imm, *r.adjustsp.rex(0x81, w=1))
 
 #
 # Float loads and stores.

lib/cretonne/meta/isa/intel/recipes.py

@@ -10,7 +10,7 @@ from base.formats import Trap, Call, IndirectCall, Store, Load
 from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
 from base.formats import Jump, Branch, BranchInt, BranchFloat
 from base.formats import Ternary, FuncAddr, UnaryGlobalVar
-from base.formats import RegMove, RegSpill, RegFill, CopySpecial
+from base.formats import RegMove, RegSpill, RegFill, CopySpecial, AdjustSpImm
 from .registers import GPR, ABCD, FPR, GPR8, FPR8, FLAG, StackGPR32, StackFPR32
 from .defs import supported_floatccs
 
@@ -493,6 +493,15 @@ copysp = TailRecipe(
         modrm_rr(dst, src, sink);
         ''')
 
+adjustsp = TailRecipe(
+    'adjustsp', AdjustSpImm, size=5, ins=(), outs=(),
+    emit='''
+    PUT_OP(bits, rex1(4), sink);
+    modrm_r_bits(4, bits, sink);
+    let offset: i32 = offset.into();
+    sink.put4(offset as u32);
+    ''')
+
 
 # XX+rd id with Abs4 function relocation.
 fnaddr4 = TailRecipe(

lib/cretonne/src/ir/instructions.rs

@@ -241,6 +241,7 @@ pub enum InstructionData {
         src: RegUnit,
         dst: RegUnit,
     },
+    AdjustSpImm { opcode: Opcode, offset: Offset32 },
     RegSpill {
         opcode: Opcode,
         arg: Value,

lib/cretonne/src/isa/intel/abi.rs

@@ -140,8 +140,8 @@ pub fn allocatable_registers(
     flags: &shared_settings::Flags,
 ) -> AllocatableSet {
     let mut regs = AllocatableSet::new();
-    regs.take(GPR, RU::rsp as RegUnit);
+    //regs.take(GPR, RU::rsp as RegUnit);
-    regs.take(GPR, RU::rbp as RegUnit);
+    //regs.take(GPR, RU::rbp as RegUnit);
 
     // 32-bit arch only has 8 registers.
     if !flags.is_64bit() {

lib/cretonne/src/verifier/mod.rs

@@ -359,6 +359,7 @@ impl<'a> Verifier<'a> {
             Store { .. } |
             RegMove { .. } |
             CopySpecial { .. } |
+            AdjustSpImm { .. } |
             Trap { .. } |
             CondTrap { .. } |
             NullAry { .. } => {}

lib/cretonne/src/write.rs

@@ -407,6 +407,7 @@ pub fn write_operands(
                 write!(w, " %{} -> %{}", src, dst)
             }
         }
+        AdjustSpImm { offset, .. } => write!(w, " {}", offset),
         RegSpill { arg, src, dst, .. } => {
             if let Some(isa) = isa {
                 let regs = isa.register_info();

lib/reader/src/parser.rs

@@ -2279,6 +2279,10 @@ impl<'a> Parser<'a> {
                 let dst = self.match_regunit(ctx.unique_isa)?;
                 InstructionData::CopySpecial { opcode, src, dst }
             }
+            InstructionFormat::AdjustSpImm => {
+                let offset = self.optional_offset32()?;
+                InstructionData::AdjustSpImm { opcode, offset }
+            }
             InstructionFormat::RegSpill => {
                 let arg = self.match_value("expected SSA value operand")?;
                 self.match_token(