Fix push/pop encoding for extended registers. Add copy_special encoding.

lib/cretonne/meta/isa/intel/encodings.py

@@ -228,9 +228,14 @@ enc_both(base.fill.b1, r.fiSib32, 0x8b)
 enc_both(base.regfill.b1, r.rfi32, 0x8b)
 
 # Push and Pop
+I64.enc(x86.push.i64, *r.pushq.rex(0x50))
 I64.enc(x86.push.i64, *r.pushq(0x50))
+I64.enc(x86.pop.i64, *r.popq.rex(0x58))
 I64.enc(x86.pop.i64, *r.popq(0x58))
 
+# Copy Special
+I64.enc(base.copy_special, *r.copysp.rex(0x89))
+
 #
 # Float loads and stores.
 #

lib/cretonne/meta/isa/intel/recipes.py

@@ -10,7 +10,7 @@ from base.formats import Trap, Call, IndirectCall, Store, Load
 from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
 from base.formats import Jump, Branch, BranchInt, BranchFloat
 from base.formats import Ternary, FuncAddr, UnaryGlobalVar
-from base.formats import RegMove, RegSpill, RegFill
+from base.formats import RegMove, RegSpill, RegFill, CopySpecial
 from .registers import GPR, ABCD, FPR, GPR8, FPR8, FLAG, StackGPR32, StackFPR32
 from .defs import supported_floatccs
 
@@ -484,6 +484,16 @@ popq = TailRecipe(
     PUT_OP(bits | (out_reg0 & 7), rex1(out_reg0), sink);
     ''')
 
+# XX /r, for regmove instructions.
+copysp = TailRecipe(
+        'copysp', CopySpecial, size=1, ins=(), outs=(),
+        clobbers_flags=False,
+        emit='''
+        PUT_OP(bits, rex2(dst, src), sink);
+        modrm_rr(dst, src, sink);
+        ''')
+
+
 # XX+rd id with Abs4 function relocation.
 fnaddr4 = TailRecipe(
         'fnaddr4', FuncAddr, size=4, ins=(), outs=GPR,