From ffab87318ecbad9085d7c7184be9b5038b15e62b Mon Sep 17 00:00:00 2001 From: Tyler McMullen Date: Mon, 27 Nov 2017 15:32:28 -0800 Subject: [PATCH] Add adjust_sp_imm instruction. Note: This enables using rsp and rbp as normal registers. Which is... wrong. --- lib/cretonne/meta/base/formats.py | 1 + lib/cretonne/meta/base/instructions.py | 8 ++++++++ lib/cretonne/meta/isa/intel/encodings.py | 5 ++++- lib/cretonne/meta/isa/intel/recipes.py | 11 ++++++++++- lib/cretonne/src/ir/instructions.rs | 1 + lib/cretonne/src/isa/intel/abi.rs | 4 ++-- lib/cretonne/src/verifier/mod.rs | 1 + lib/cretonne/src/write.rs | 1 + lib/reader/src/parser.rs | 4 ++++ 9 files changed, 32 insertions(+), 4 deletions(-) diff --git a/lib/cretonne/meta/base/formats.py b/lib/cretonne/meta/base/formats.py index 539d87561b..df8539656b 100644 --- a/lib/cretonne/meta/base/formats.py +++ b/lib/cretonne/meta/base/formats.py @@ -69,6 +69,7 @@ RegSpill = InstructionFormat( VALUE, ('src', regunit), ('dst', entities.stack_slot)) RegFill = InstructionFormat( VALUE, ('src', entities.stack_slot), ('dst', regunit)) +AdjustSpImm = InstructionFormat(offset32) Trap = InstructionFormat(trapcode) CondTrap = InstructionFormat(VALUE, trapcode) diff --git a/lib/cretonne/meta/base/instructions.py b/lib/cretonne/meta/base/instructions.py index 195f255046..4eef992e99 100644 --- a/lib/cretonne/meta/base/instructions.py +++ b/lib/cretonne/meta/base/instructions.py @@ -544,6 +544,14 @@ copy_special = Instruction( ins=(src, dst), other_side_effects=True) +Offset = Operand('Offset', offset32, 'Offset from current stack pointer') +adjust_sp_imm = Instruction( + 'adjust_sp_imm', r""" + Adds an immediate offset value to the stack pointer register. + """, + ins=(Offset,), + other_side_effects=True) + regspill = Instruction( 'regspill', r""" Temporarily divert ``x`` from ``src`` to ``SS``. diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py index 0b1f33524f..c4b4a730e6 100644 --- a/lib/cretonne/meta/isa/intel/encodings.py +++ b/lib/cretonne/meta/isa/intel/encodings.py @@ -234,7 +234,10 @@ I64.enc(x86.pop.i64, *r.popq.rex(0x58)) I64.enc(x86.pop.i64, *r.popq(0x58)) # Copy Special -I64.enc(base.copy_special, *r.copysp.rex(0x89)) +I64.enc(base.copy_special, *r.copysp.rex(0x89, w=1)) + +# Adjust SP Imm +I64.enc(base.adjust_sp_imm, *r.adjustsp.rex(0x81, w=1)) # # Float loads and stores. diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py index 71c280ff2a..a478b1b54e 100644 --- a/lib/cretonne/meta/isa/intel/recipes.py +++ b/lib/cretonne/meta/isa/intel/recipes.py @@ -10,7 +10,7 @@ from base.formats import Trap, Call, IndirectCall, Store, Load from base.formats import IntCompare, FloatCompare, IntCond, FloatCond from base.formats import Jump, Branch, BranchInt, BranchFloat from base.formats import Ternary, FuncAddr, UnaryGlobalVar -from base.formats import RegMove, RegSpill, RegFill, CopySpecial +from base.formats import RegMove, RegSpill, RegFill, CopySpecial, AdjustSpImm from .registers import GPR, ABCD, FPR, GPR8, FPR8, FLAG, StackGPR32, StackFPR32 from .defs import supported_floatccs @@ -493,6 +493,15 @@ copysp = TailRecipe( modrm_rr(dst, src, sink); ''') +adjustsp = TailRecipe( + 'adjustsp', AdjustSpImm, size=5, ins=(), outs=(), + emit=''' + PUT_OP(bits, rex1(4), sink); + modrm_r_bits(4, bits, sink); + let offset: i32 = offset.into(); + sink.put4(offset as u32); + ''') + # XX+rd id with Abs4 function relocation. fnaddr4 = TailRecipe( diff --git a/lib/cretonne/src/ir/instructions.rs b/lib/cretonne/src/ir/instructions.rs index 37ca23150c..040d6cb98e 100644 --- a/lib/cretonne/src/ir/instructions.rs +++ b/lib/cretonne/src/ir/instructions.rs @@ -241,6 +241,7 @@ pub enum InstructionData { src: RegUnit, dst: RegUnit, }, + AdjustSpImm { opcode: Opcode, offset: Offset32 }, RegSpill { opcode: Opcode, arg: Value, diff --git a/lib/cretonne/src/isa/intel/abi.rs b/lib/cretonne/src/isa/intel/abi.rs index e8be53e848..0c45a0e223 100644 --- a/lib/cretonne/src/isa/intel/abi.rs +++ b/lib/cretonne/src/isa/intel/abi.rs @@ -140,8 +140,8 @@ pub fn allocatable_registers( flags: &shared_settings::Flags, ) -> AllocatableSet { let mut regs = AllocatableSet::new(); - regs.take(GPR, RU::rsp as RegUnit); - regs.take(GPR, RU::rbp as RegUnit); + //regs.take(GPR, RU::rsp as RegUnit); + //regs.take(GPR, RU::rbp as RegUnit); // 32-bit arch only has 8 registers. if !flags.is_64bit() { diff --git a/lib/cretonne/src/verifier/mod.rs b/lib/cretonne/src/verifier/mod.rs index 259cf48a5e..57a94b6d0d 100644 --- a/lib/cretonne/src/verifier/mod.rs +++ b/lib/cretonne/src/verifier/mod.rs @@ -359,6 +359,7 @@ impl<'a> Verifier<'a> { Store { .. } | RegMove { .. } | CopySpecial { .. } | + AdjustSpImm { .. } | Trap { .. } | CondTrap { .. } | NullAry { .. } => {} diff --git a/lib/cretonne/src/write.rs b/lib/cretonne/src/write.rs index 8c8c280ca9..ba951c4c84 100644 --- a/lib/cretonne/src/write.rs +++ b/lib/cretonne/src/write.rs @@ -407,6 +407,7 @@ pub fn write_operands( write!(w, " %{} -> %{}", src, dst) } } + AdjustSpImm { offset, .. } => write!(w, " {}", offset), RegSpill { arg, src, dst, .. } => { if let Some(isa) = isa { let regs = isa.register_info(); diff --git a/lib/reader/src/parser.rs b/lib/reader/src/parser.rs index b3827de62c..d567da7741 100644 --- a/lib/reader/src/parser.rs +++ b/lib/reader/src/parser.rs @@ -2279,6 +2279,10 @@ impl<'a> Parser<'a> { let dst = self.match_regunit(ctx.unique_isa)?; InstructionData::CopySpecial { opcode, src, dst } } + InstructionFormat::AdjustSpImm => { + let offset = self.optional_offset32()?; + InstructionData::AdjustSpImm { opcode, offset } + } InstructionFormat::RegSpill => { let arg = self.match_value("expected SSA value operand")?; self.match_token(