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Add adjust_sp_imm instruction. Note: This enables using rsp and rbp as normal registers. Which is... wrong.

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Tyler McMullen
2017-11-27 15:32:28 -08:00
committed by Jakob Stoklund Olesen
parent 32509ebacd
commit ffab87318e
9 changed files with 32 additions and 4 deletions
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4
lib/cretonne/src/isa/intel/abi.rs
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@@ -140,8 +140,8 @@ pub fn allocatable_registers(
flags: &shared_settings::Flags,
) -> AllocatableSet {
let mut regs = AllocatableSet::new();
regs.take(GPR, RU::rsp as RegUnit);
regs.take(GPR, RU::rbp as RegUnit);
//regs.take(GPR, RU::rsp as RegUnit);
//regs.take(GPR, RU::rbp as RegUnit);
// 32-bit arch only has 8 registers.
if !flags.is_64bit() {