Add adjust_sp_imm instruction. Note: This enables using rsp and rbp as normal registers. Which is... wrong.

lib/cretonne/src/ir/instructions.rs

@@ -241,6 +241,7 @@ pub enum InstructionData {
         src: RegUnit,
         dst: RegUnit,
     },
+    AdjustSpImm { opcode: Opcode, offset: Offset32 },
     RegSpill {
         opcode: Opcode,
         arg: Value,

lib/cretonne/src/isa/intel/abi.rs

@@ -140,8 +140,8 @@ pub fn allocatable_registers(
     flags: &shared_settings::Flags,
 ) -> AllocatableSet {
     let mut regs = AllocatableSet::new();
-    regs.take(GPR, RU::rsp as RegUnit);
-    regs.take(GPR, RU::rbp as RegUnit);
+    //regs.take(GPR, RU::rsp as RegUnit);
+    //regs.take(GPR, RU::rbp as RegUnit);
 
     // 32-bit arch only has 8 registers.
     if !flags.is_64bit() {

lib/cretonne/src/verifier/mod.rs

@@ -359,6 +359,7 @@ impl<'a> Verifier<'a> {
             Store { .. } |
             RegMove { .. } |
             CopySpecial { .. } |
+            AdjustSpImm { .. } |
             Trap { .. } |
             CondTrap { .. } |
             NullAry { .. } => {}

lib/cretonne/src/write.rs

@@ -407,6 +407,7 @@ pub fn write_operands(
                 write!(w, " %{} -> %{}", src, dst)
             }
         }
+        AdjustSpImm { offset, .. } => write!(w, " {}", offset),
         RegSpill { arg, src, dst, .. } => {
             if let Some(isa) = isa {
                 let regs = isa.register_info();