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Add adjust_sp_imm instruction. Note: This enables using rsp and rbp as normal registers. Which is... wrong.

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Tyler McMullen
2017-11-27 15:32:28 -08:00
committed by Jakob Stoklund Olesen
parent 32509ebacd
commit ffab87318e
9 changed files with 32 additions and 4 deletions
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5
lib/cretonne/meta/isa/intel/encodings.py
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@@ -234,7 +234,10 @@ I64.enc(x86.pop.i64, *r.popq.rex(0x58))
I64.enc(x86.pop.i64, *r.popq(0x58))
# Copy Special
I64.enc(base.copy_special, *r.copysp.rex(0x89))
I64.enc(base.copy_special, *r.copysp.rex(0x89, w=1))
# Adjust SP Imm
I64.enc(base.adjust_sp_imm, *r.adjustsp.rex(0x81, w=1))
#
# Float loads and stores.