Add adjust_sp_imm instruction. Note: This enables using rsp and rbp as normal registers. Which is... wrong.

lib/cretonne/meta/isa/intel/encodings.py

@@ -234,7 +234,10 @@ I64.enc(x86.pop.i64, *r.popq.rex(0x58))
 I64.enc(x86.pop.i64, *r.popq(0x58))
 
 # Copy Special
-I64.enc(base.copy_special, *r.copysp.rex(0x89))
+I64.enc(base.copy_special, *r.copysp.rex(0x89, w=1))
+
+# Adjust SP Imm
+I64.enc(base.adjust_sp_imm, *r.adjustsp.rex(0x81, w=1))
 
 #
 # Float loads and stores.

lib/cretonne/meta/isa/intel/recipes.py

@@ -10,7 +10,7 @@ from base.formats import Trap, Call, IndirectCall, Store, Load
 from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
 from base.formats import Jump, Branch, BranchInt, BranchFloat
 from base.formats import Ternary, FuncAddr, UnaryGlobalVar
-from base.formats import RegMove, RegSpill, RegFill, CopySpecial
+from base.formats import RegMove, RegSpill, RegFill, CopySpecial, AdjustSpImm
 from .registers import GPR, ABCD, FPR, GPR8, FPR8, FLAG, StackGPR32, StackFPR32
 from .defs import supported_floatccs
 
@@ -493,6 +493,15 @@ copysp = TailRecipe(
         modrm_rr(dst, src, sink);
         ''')
 
+adjustsp = TailRecipe(
+    'adjustsp', AdjustSpImm, size=5, ins=(), outs=(),
+    emit='''
+    PUT_OP(bits, rex1(4), sink);
+    modrm_r_bits(4, bits, sink);
+    let offset: i32 = offset.into();
+    sink.put4(offset as u32);
+    ''')
+
 
 # XX+rd id with Abs4 function relocation.
 fnaddr4 = TailRecipe(