Add a register bank index to RegClassData.

This makes it possible to find the register bank that contains a
register class.
This commit is contained in:
Jakob Stoklund Olesen
2017-05-15 13:01:41 -07:00
parent a2fd9cf0cc
commit ca6eddaf88
4 changed files with 13 additions and 6 deletions

View File

@@ -87,6 +87,7 @@ class RegBank(object):
align = next_power_of_two(align)
self.first_unit = (u + align - 1) & -align
self.index = len(isa.regbanks)
isa.regbanks.append(self)
def __repr__(self):

View File

@@ -34,13 +34,14 @@ def gen_regclass(rc, fmt):
Emit a static data definition for a register class.
"""
with fmt.indented('RegClassData {', '},'):
fmt.line('name: "{}",'.format(rc.name))
fmt.line('index: {},'.format(rc.index))
fmt.line('width: {},'.format(rc.width))
fmt.line('first: {},'.format(rc.bank.first_unit + rc.start))
fmt.line('subclasses: 0x{:x},'.format(rc.subclass_mask()))
fmt.format('name: "{}",', rc.name)
fmt.format('index: {},', rc.index)
fmt.format('width: {},', rc.width)
fmt.format('bank: {},', rc.bank.index)
fmt.format('first: {},', rc.bank.first_unit + rc.start)
fmt.format('subclasses: 0x{:x},', rc.subclass_mask())
mask = ', '.join('0x{:08x}'.format(x) for x in rc.mask())
fmt.line('mask: [{}],'.format(mask))
fmt.format('mask: [{}],', mask)
def gen_isa(isa, fmt):

View File

@@ -108,6 +108,9 @@ pub struct RegClassData {
/// How many register units to allocate per register.
pub width: u8,
/// Index of the register bank this class belongs to.
pub bank: u8,
/// The first register unit in this class.
pub first: RegUnit,

View File

@@ -140,6 +140,7 @@ mod tests {
name: "GPR",
index: 0,
width: 1,
bank: 0,
first: 28,
subclasses: 0,
mask: [0xf0000000, 0x0000000f, 0],
@@ -148,6 +149,7 @@ mod tests {
name: "DPR",
index: 0,
width: 2,
bank: 0,
first: 28,
subclasses: 0,
mask: [0x50000000, 0x0000000a, 0],