Add a register bank index to RegClassData.
This makes it possible to find the register bank that contains a register class.
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@@ -87,6 +87,7 @@ class RegBank(object):
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align = next_power_of_two(align)
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self.first_unit = (u + align - 1) & -align
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self.index = len(isa.regbanks)
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isa.regbanks.append(self)
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def __repr__(self):
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@@ -34,13 +34,14 @@ def gen_regclass(rc, fmt):
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Emit a static data definition for a register class.
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"""
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with fmt.indented('RegClassData {', '},'):
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fmt.line('name: "{}",'.format(rc.name))
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fmt.line('index: {},'.format(rc.index))
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fmt.line('width: {},'.format(rc.width))
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fmt.line('first: {},'.format(rc.bank.first_unit + rc.start))
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fmt.line('subclasses: 0x{:x},'.format(rc.subclass_mask()))
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fmt.format('name: "{}",', rc.name)
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fmt.format('index: {},', rc.index)
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fmt.format('width: {},', rc.width)
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fmt.format('bank: {},', rc.bank.index)
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fmt.format('first: {},', rc.bank.first_unit + rc.start)
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fmt.format('subclasses: 0x{:x},', rc.subclass_mask())
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mask = ', '.join('0x{:08x}'.format(x) for x in rc.mask())
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fmt.line('mask: [{}],'.format(mask))
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fmt.format('mask: [{}],', mask)
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def gen_isa(isa, fmt):
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@@ -108,6 +108,9 @@ pub struct RegClassData {
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/// How many register units to allocate per register.
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pub width: u8,
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/// Index of the register bank this class belongs to.
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pub bank: u8,
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/// The first register unit in this class.
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pub first: RegUnit,
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@@ -140,6 +140,7 @@ mod tests {
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name: "GPR",
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index: 0,
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width: 1,
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bank: 0,
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first: 28,
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subclasses: 0,
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mask: [0xf0000000, 0x0000000f, 0],
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@@ -148,6 +149,7 @@ mod tests {
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name: "DPR",
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index: 0,
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width: 2,
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bank: 0,
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first: 28,
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subclasses: 0,
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mask: [0x50000000, 0x0000000a, 0],
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