From ca6eddaf88cabdb2a2993d1392df25ece7b49155 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Mon, 15 May 2017 13:01:41 -0700
Subject: [PATCH] Add a register bank index to RegClassData.

This makes it possible to find the register bank that contains a
register class.
---
 lib/cretonne/meta/cdsl/registers.py          |  1 +
 lib/cretonne/meta/gen_registers.py           | 13 +++++++------
 lib/cretonne/src/isa/registers.rs            |  3 +++
 lib/cretonne/src/regalloc/allocatable_set.rs |  2 ++
 4 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/lib/cretonne/meta/cdsl/registers.py b/lib/cretonne/meta/cdsl/registers.py
index 1f6bfa682f..c16e760a5c 100644
--- a/lib/cretonne/meta/cdsl/registers.py
+++ b/lib/cretonne/meta/cdsl/registers.py
@@ -87,6 +87,7 @@ class RegBank(object):
                 align = next_power_of_two(align)
             self.first_unit = (u + align - 1) & -align
 
+        self.index = len(isa.regbanks)
         isa.regbanks.append(self)
 
     def __repr__(self):
diff --git a/lib/cretonne/meta/gen_registers.py b/lib/cretonne/meta/gen_registers.py
index b1532761a6..4199dce268 100644
--- a/lib/cretonne/meta/gen_registers.py
+++ b/lib/cretonne/meta/gen_registers.py
@@ -34,13 +34,14 @@ def gen_regclass(rc, fmt):
     Emit a static data definition for a register class.
     """
     with fmt.indented('RegClassData {', '},'):
-        fmt.line('name: "{}",'.format(rc.name))
-        fmt.line('index: {},'.format(rc.index))
-        fmt.line('width: {},'.format(rc.width))
-        fmt.line('first: {},'.format(rc.bank.first_unit + rc.start))
-        fmt.line('subclasses: 0x{:x},'.format(rc.subclass_mask()))
+        fmt.format('name: "{}",', rc.name)
+        fmt.format('index: {},', rc.index)
+        fmt.format('width: {},', rc.width)
+        fmt.format('bank: {},', rc.bank.index)
+        fmt.format('first: {},', rc.bank.first_unit + rc.start)
+        fmt.format('subclasses: 0x{:x},', rc.subclass_mask())
         mask = ', '.join('0x{:08x}'.format(x) for x in rc.mask())
-        fmt.line('mask: [{}],'.format(mask))
+        fmt.format('mask: [{}],', mask)
 
 
 def gen_isa(isa, fmt):
diff --git a/lib/cretonne/src/isa/registers.rs b/lib/cretonne/src/isa/registers.rs
index 91a25595f1..461309a9e9 100644
--- a/lib/cretonne/src/isa/registers.rs
+++ b/lib/cretonne/src/isa/registers.rs
@@ -108,6 +108,9 @@ pub struct RegClassData {
     /// How many register units to allocate per register.
     pub width: u8,
 
+    /// Index of the register bank this class belongs to.
+    pub bank: u8,
+
     /// The first register unit in this class.
     pub first: RegUnit,
 
diff --git a/lib/cretonne/src/regalloc/allocatable_set.rs b/lib/cretonne/src/regalloc/allocatable_set.rs
index db5a593901..fa3e7a9153 100644
--- a/lib/cretonne/src/regalloc/allocatable_set.rs
+++ b/lib/cretonne/src/regalloc/allocatable_set.rs
@@ -140,6 +140,7 @@ mod tests {
         name: "GPR",
         index: 0,
         width: 1,
+        bank: 0,
         first: 28,
         subclasses: 0,
         mask: [0xf0000000, 0x0000000f, 0],
@@ -148,6 +149,7 @@ mod tests {
         name: "DPR",
         index: 0,
         width: 2,
+        bank: 0,
         first: 28,
         subclasses: 0,
         mask: [0x50000000, 0x0000000a, 0],