Generate SSA code from returns (#5172)

Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.

cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif

@@ -9,8 +9,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   movz x3, #127
-;   adds w0, w0, w3
+;   movz x2, #127
+;   adds w0, w0, w2
 ;   b.lo 8 ; udf
 ;   ret
 
@@ -22,8 +22,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   movz x3, #127
-;   adds w0, w3, w0
+;   movz x2, #127
+;   adds w0, w2, w0
 ;   b.lo 8 ; udf
 ;   ret
 
@@ -46,8 +46,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz x3, #127
-;   adds x0, x0, x3
+;   movz x2, #127
+;   adds x0, x0, x2
 ;   b.lo 8 ; udf
 ;   ret
 
@@ -59,8 +59,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz x3, #127
-;   adds x0, x3, x0
+;   movz x2, #127
+;   adds x0, x2, x0
 ;   b.lo 8 ; udf
 ;   ret