Generate SSA code from returns (#5172)

Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.

cranelift/filetests/filetests/isa/aarch64/amodes.clif

@@ -36,8 +36,8 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   mov w4, w0
-;   ldr w0, [x4, w1, UXTW]
+;   mov w3, w0
+;   ldr w0, [x3, w1, UXTW]
 ;   ret
 
 function %f8(i64, i32) -> i32 {
@@ -52,10 +52,10 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   add x4, x0, #68
-;   add x4, x4, x0
-;   add x4, x4, x1, SXTW
-;   ldr w0, [x4, w1, SXTW]
+;   add x3, x0, #68
+;   add x3, x3, x0
+;   add x3, x3, x1, SXTW
+;   ldr w0, [x3, w1, SXTW]
 ;   ret
 
 function %f9(i64, i64, i64) -> i32 {
@@ -69,10 +69,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   mov x6, x0
-;   add x6, x6, x2
-;   add x6, x6, x1
-;   ldr w0, [x6, #48]
+;   mov x5, x0
+;   add x5, x5, x2
+;   add x5, x5, x1
+;   ldr w0, [x5, #48]
 ;   ret
 
 function %f10(i64, i64, i64) -> i32 {
@@ -86,10 +86,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x5, #4100
-;   add x5, x5, x1
-;   add x5, x5, x2
-;   ldr w0, [x5, x0]
+;   movz x4, #4100
+;   add x4, x4, x1
+;   add x4, x4, x2
+;   ldr w0, [x4, x0]
 ;   ret
 
 function %f10() -> i32 {
@@ -100,8 +100,8 @@ block0:
 }
 
 ; block0:
-;   movz x1, #1234
-;   ldr w0, [x1]
+;   movz x0, #1234
+;   ldr w0, [x0]
 ;   ret
 
 function %f11(i64) -> i32 {
@@ -113,8 +113,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   add x3, x0, #8388608
-;   ldr w0, [x3]
+;   add x2, x0, #8388608
+;   ldr w0, [x2]
 ;   ret
 
 function %f12(i64) -> i32 {
@@ -126,8 +126,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   sub x3, x0, #4
-;   ldr w0, [x3]
+;   sub x2, x0, #4
+;   ldr w0, [x2]
 ;   ret
 
 function %f13(i64) -> i32 {
@@ -139,10 +139,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz w3, #51712
-;   movk w3, w3, #15258, LSL #16
-;   add x3, x3, x0
-;   ldr w0, [x3]
+;   movz w2, #51712
+;   movk w2, w2, #15258, LSL #16
+;   add x2, x2, x0
+;   ldr w0, [x2]
 ;   ret
 
 function %f14(i32) -> i32 {
@@ -153,8 +153,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sxtw x3, w0
-;   ldr w0, [x3]
+;   sxtw x2, w0
+;   ldr w0, [x2]
 ;   ret
 
 function %f15(i32, i32) -> i32 {
@@ -167,8 +167,8 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sxtw x4, w0
-;   ldr w0, [x4, w1, SXTW]
+;   sxtw x3, w0
+;   ldr w0, [x3, w1, SXTW]
 ;   ret
 
 function %f18(i64, i64, i64) -> i32 {
@@ -180,8 +180,8 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movn w5, #4097
-;   ldrsh x0, [x5]
+;   movn w4, #4097
+;   ldrsh x0, [x4]
 ;   ret
 
 function %f19(i64, i64, i64) -> i32 {
@@ -193,8 +193,8 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x5, #4098
-;   ldrsh x0, [x5]
+;   movz x4, #4098
+;   ldrsh x0, [x4]
 ;   ret
 
 function %f20(i64, i64, i64) -> i32 {
@@ -206,9 +206,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movn w5, #4097
-;   sxtw x7, w5
-;   ldrsh x0, [x7]
+;   movn w4, #4097
+;   sxtw x6, w4
+;   ldrsh x0, [x6]
 ;   ret
 
 function %f21(i64, i64, i64) -> i32 {
@@ -220,9 +220,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x5, #4098
-;   sxtw x7, w5
-;   ldrsh x0, [x7]
+;   movz x4, #4098
+;   sxtw x6, w4
+;   ldrsh x0, [x6]
 ;   ret
 
 function %i128(i64) -> i128 {
@@ -233,11 +233,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
-;   mov x6, x8
-;   ldp x0, x1, [x6]
-;   mov x7, x8
-;   stp x0, x1, [x7]
+;   mov x6, x0
+;   mov x4, x6
+;   ldp x0, x1, [x4]
+;   mov x5, x6
+;   stp x0, x1, [x5]
 ;   ret
 
 function %i128_imm_offset(i64) -> i128 {
@@ -248,11 +248,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
-;   mov x6, x8
-;   ldp x0, x1, [x6, #16]
-;   mov x7, x8
-;   stp x0, x1, [x7, #16]
+;   mov x6, x0
+;   mov x4, x6
+;   ldp x0, x1, [x4, #16]
+;   mov x5, x6
+;   stp x0, x1, [x5, #16]
 ;   ret
 
 function %i128_imm_offset_large(i64) -> i128 {
@@ -263,11 +263,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
-;   mov x6, x8
-;   ldp x0, x1, [x6, #504]
-;   mov x7, x8
-;   stp x0, x1, [x7, #504]
+;   mov x6, x0
+;   mov x4, x6
+;   ldp x0, x1, [x4, #504]
+;   mov x5, x6
+;   stp x0, x1, [x5, #504]
 ;   ret
 
 function %i128_imm_offset_negative_large(i64) -> i128 {
@@ -278,11 +278,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
-;   mov x6, x8
-;   ldp x0, x1, [x6, #-512]
-;   mov x7, x8
-;   stp x0, x1, [x7, #-512]
+;   mov x6, x0
+;   mov x4, x6
+;   ldp x0, x1, [x4, #-512]
+;   mov x5, x6
+;   stp x0, x1, [x5, #-512]
 ;   ret
 
 function %i128_add_offset(i64) -> i128 {
@@ -294,11 +294,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
-;   mov x6, x8
-;   ldp x0, x1, [x6, #32]
-;   mov x7, x8
-;   stp x0, x1, [x7, #32]
+;   mov x6, x0
+;   mov x4, x6
+;   ldp x0, x1, [x4, #32]
+;   mov x5, x6
+;   stp x0, x1, [x5, #32]
 ;   ret
 
 function %i128_32bit_sextend_simple(i32) -> i128 {
@@ -310,11 +310,11 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sxtw x6, w0
-;   ldp x10, x1, [x6]
-;   sxtw x7, w0
-;   mov x0, x10
-;   stp x0, x1, [x7]
+;   sxtw x4, w0
+;   mov x11, x0
+;   ldp x0, x1, [x4]
+;   sxtw x5, w11
+;   stp x0, x1, [x5]
 ;   ret
 
 function %i128_32bit_sextend(i64, i32) -> i128 {
@@ -328,13 +328,13 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   mov x11, x0
-;   mov x7, x11
-;   add x7, x7, x1, SXTW
-;   ldp x0, x10, [x7, #24]
-;   mov x9, x11
-;   add x9, x9, x1, SXTW
-;   mov x1, x10
-;   stp x0, x1, [x9, #24]
+;   mov x9, x0
+;   mov x5, x9
+;   add x5, x5, x1, SXTW
+;   mov x11, x1
+;   ldp x0, x1, [x5, #24]
+;   mov x7, x9
+;   add x7, x7, x11, SXTW
+;   stp x0, x1, [x7, #24]
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/arithmetic.clif

@@ -74,8 +74,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz w3, #2
-;   sdiv x0, x0, x3
+;   movz w2, #2
+;   sdiv x0, x0, x2
 ;   ret
 
 function %f8(i64, i64) -> i64 {
@@ -97,8 +97,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   orr x3, xzr, #2
-;   udiv x0, x0, x3
+;   orr x2, xzr, #2
+;   udiv x0, x0, x2
 ;   ret
 
 function %f10(i64, i64) -> i64 {
@@ -109,8 +109,8 @@ block0(v0: i64, v1: i64):
 
 ; block0:
 ;   cbnz x1, 8 ; udf
-;   sdiv x5, x0, x1
-;   msub x0, x5, x1, x0
+;   sdiv x4, x0, x1
+;   msub x0, x4, x1, x0
 ;   ret
 
 function %f11(i64, i64) -> i64 {
@@ -121,8 +121,8 @@ block0(v0: i64, v1: i64):
 
 ; block0:
 ;   cbnz x1, 8 ; udf
-;   udiv x5, x0, x1
-;   msub x0, x5, x1, x0
+;   udiv x4, x0, x1
+;   msub x0, x4, x1, x0
 ;   ret
 
 function %f12(i32, i32) -> i32 {
@@ -132,13 +132,13 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sxtw x4, w0
-;   sxtw x6, w1
-;   cbnz x6, 8 ; udf
-;   adds wzr, w6, #1
-;   ccmp w4, #1, #nzcv, eq
+;   sxtw x3, w0
+;   sxtw x5, w1
+;   cbnz x5, 8 ; udf
+;   adds wzr, w5, #1
+;   ccmp w3, #1, #nzcv, eq
 ;   b.vc 8 ; udf
-;   sdiv x0, x4, x6
+;   sdiv x0, x3, x5
 ;   ret
 
 function %f13(i32) -> i32 {
@@ -149,9 +149,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sxtw x3, w0
-;   movz w5, #2
-;   sdiv x0, x3, x5
+;   sxtw x2, w0
+;   movz w4, #2
+;   sdiv x0, x2, x4
 ;   ret
 
 function %f14(i32, i32) -> i32 {
@@ -161,10 +161,10 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   mov w4, w0
-;   mov w6, w1
-;   cbnz x6, 8 ; udf
-;   udiv x0, x4, x6
+;   mov w3, w0
+;   mov w5, w1
+;   cbnz x5, 8 ; udf
+;   udiv x0, x3, x5
 ;   ret
 
 function %f15(i32) -> i32 {
@@ -175,9 +175,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   mov w3, w0
-;   orr w5, wzr, #2
-;   udiv x0, x3, x5
+;   mov w2, w0
+;   orr w4, wzr, #2
+;   udiv x0, x2, x4
 ;   ret
 
 function %f16(i32, i32) -> i32 {
@@ -187,11 +187,11 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sxtw x4, w0
-;   sxtw x6, w1
-;   cbnz x6, 8 ; udf
-;   sdiv x9, x4, x6
-;   msub x0, x9, x6, x4
+;   sxtw x3, w0
+;   sxtw x5, w1
+;   cbnz x5, 8 ; udf
+;   sdiv x8, x3, x5
+;   msub x0, x8, x5, x3
 ;   ret
 
 function %f17(i32, i32) -> i32 {
@@ -201,11 +201,11 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   mov w4, w0
-;   mov w6, w1
-;   cbnz x6, 8 ; udf
-;   udiv x9, x4, x6
-;   msub x0, x9, x6, x4
+;   mov w3, w0
+;   mov w5, w1
+;   cbnz x5, 8 ; udf
+;   udiv x8, x3, x5
+;   msub x0, x8, x5, x3
 ;   ret
 
 function %f18(i64, i64) -> i64 {
@@ -331,8 +331,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz x3, #1
-;   sub x0, xzr, x3
+;   movz x2, #1
+;   sub x0, xzr, x2
 ;   ret
 
 function %f30(i8x16) -> i8x16 {
@@ -343,11 +343,11 @@ block0(v0: i8x16):
 }
 
 ; block0:
-;   movz x3, #1
-;   and w5, w3, #7
-;   sub x7, xzr, x5
-;   dup v17.16b, w7
-;   ushl v0.16b, v0.16b, v17.16b
+;   movz x2, #1
+;   and w4, w2, #7
+;   sub x6, xzr, x4
+;   dup v16.16b, w6
+;   ushl v0.16b, v0.16b, v16.16b
 ;   ret
 
 function %add_i128(i128, i128) -> i128 {
@@ -379,9 +379,9 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   umulh x7, x0, x2
-;   madd x9, x0, x3, x7
-;   madd x1, x1, x2, x9
+;   umulh x5, x0, x2
+;   madd x7, x0, x3, x5
+;   madd x1, x1, x2, x7
 ;   madd x0, x0, x2, xzr
 ;   ret
 
@@ -437,8 +437,8 @@ block0(v0: i32, v1: i32, v2: i32):
 }
 
 ; block0:
-;   madd w6, w1, w2, wzr
-;   sub w0, w6, w0
+;   madd w5, w1, w2, wzr
+;   sub w0, w5, w0
 ;   ret
 
 function %imul_sub_i64(i64, i64, i64) -> i64 {
@@ -449,8 +449,8 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   madd x6, x1, x2, xzr
-;   sub x0, x6, x0
+;   madd x5, x1, x2, xzr
+;   sub x0, x5, x0
 ;   ret
 
 function %srem_const (i64) -> i64 {
@@ -461,9 +461,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz w3, #2
-;   sdiv x5, x0, x3
-;   msub x0, x5, x3, x0
+;   movz w2, #2
+;   sdiv x4, x0, x2
+;   msub x0, x4, x2, x0
 ;   ret
 
 function %urem_const (i64) -> i64 {
@@ -474,9 +474,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   orr x3, xzr, #2
-;   udiv x5, x0, x3
-;   msub x0, x5, x3, x0
+;   orr x2, xzr, #2
+;   udiv x4, x0, x2
+;   msub x0, x4, x2, x0
 ;   ret
 
 function %sdiv_minus_one(i64) -> i64 {
@@ -487,9 +487,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movn x3, #0
-;   adds xzr, x3, #1
+;   movn x2, #0
+;   adds xzr, x2, #1
 ;   ccmp x0, #1, #nzcv, eq
 ;   b.vc 8 ; udf
-;   sdiv x0, x0, x3
+;   sdiv x0, x0, x2
 ;   ret
+

cranelift/filetests/filetests/isa/aarch64/bitops.clif

@@ -9,8 +9,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   rbit w3, w0
-;   lsr w0, w3, #24
+;   rbit w2, w0
+;   lsr w0, w2, #24
 ;   ret
 
 function %a(i16) -> i16 {
@@ -20,8 +20,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   rbit w3, w0
-;   lsr w0, w3, #16
+;   rbit w2, w0
+;   lsr w0, w2, #16
 ;   ret
 
 function %a(i32) -> i32 {
@@ -51,9 +51,9 @@ block0(v0: i128):
 }
 
 ; block0:
-;   rbit x5, x0
-;   rbit x0, x1
-;   mov x1, x5
+;   mov x6, x1
+;   rbit x1, x0
+;   rbit x0, x6
 ;   ret
 
 function %b(i8) -> i8 {
@@ -63,9 +63,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w3, w0
-;   clz w5, w3
-;   sub w0, w5, #24
+;   uxtb w2, w0
+;   clz w4, w2
+;   sub w0, w4, #24
 ;   ret
 
 function %b(i16) -> i16 {
@@ -75,9 +75,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   uxth w3, w0
-;   clz w5, w3
-;   sub w0, w5, #16
+;   uxth w2, w0
+;   clz w4, w2
+;   sub w0, w4, #16
 ;   ret
 
 function %b(i32) -> i32 {
@@ -107,10 +107,10 @@ block0(v0: i128):
 }
 
 ; block0:
-;   clz x5, x1
-;   clz x7, x0
-;   lsr x9, x5, #6
-;   madd x0, x7, x9, x5
+;   clz x3, x1
+;   clz x5, x0
+;   lsr x7, x3, #6
+;   madd x0, x5, x7, x3
 ;   movz w1, #0
 ;   ret
 
@@ -121,9 +121,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sxtb w3, w0
-;   cls w5, w3
-;   sub w0, w5, #24
+;   sxtb w2, w0
+;   cls w4, w2
+;   sub w0, w4, #24
 ;   ret
 
 function %c(i16) -> i16 {
@@ -133,9 +133,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sxth w3, w0
-;   cls w5, w3
-;   sub w0, w5, #16
+;   sxth w2, w0
+;   cls w4, w2
+;   sub w0, w4, #16
 ;   ret
 
 function %c(i32) -> i32 {
@@ -165,14 +165,14 @@ block0(v0: i128):
 }
 
 ; block0:
-;   cls x5, x0
-;   cls x7, x1
-;   eon x9, x1, x0
-;   lsr x11, x9, #63
-;   madd x13, x5, x11, x11
-;   subs xzr, x7, #63
-;   csel x0, x13, xzr, eq
-;   add x0, x0, x7
+;   cls x3, x0
+;   cls x5, x1
+;   eon x7, x1, x0
+;   lsr x9, x7, #63
+;   madd x11, x3, x9, x9
+;   subs xzr, x5, #63
+;   csel x14, x11, xzr, eq
+;   add x0, x14, x5
 ;   movz w1, #0
 ;   ret
 
@@ -183,9 +183,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   rbit w3, w0
-;   orr w5, w3, #8388608
-;   clz w0, w5
+;   rbit w2, w0
+;   orr w4, w2, #8388608
+;   clz w0, w4
 ;   ret
 
 function %d(i16) -> i16 {
@@ -195,9 +195,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   rbit w3, w0
-;   orr w5, w3, #32768
-;   clz w0, w5
+;   rbit w2, w0
+;   orr w4, w2, #32768
+;   clz w0, w4
 ;   ret
 
 function %d(i32) -> i32 {
@@ -207,8 +207,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   rbit w3, w0
-;   clz w0, w3
+;   rbit w2, w0
+;   clz w0, w2
 ;   ret
 
 function %d(i64) -> i64 {
@@ -217,24 +217,24 @@ block0(v0: i64):
     return v1
 }
 
+; block0:
+;   rbit x2, x0
+;   clz x0, x2
+;   ret
+
+function %d(i128) -> i128 {
+block0(v0: i128):
+    v1 = ctz v0
+    return v1
+}
+
 ; block0:
 ;   rbit x3, x0
-;   clz x0, x3
-;   ret
-
-function %d(i128) -> i128 {
-block0(v0: i128):
-    v1 = ctz v0
-    return v1
-}
-
-; block0:
-;   rbit x5, x0
-;   rbit x7, x1
+;   rbit x5, x1
+;   clz x7, x3
 ;   clz x9, x5
-;   clz x11, x7
-;   lsr x13, x9, #6
-;   madd x0, x11, x13, x9
+;   lsr x11, x7, #6
+;   madd x0, x9, x11, x7
 ;   movz w1, #0
 ;   ret
 
@@ -245,11 +245,11 @@ block0(v0: i128):
 }
 
 ; block0:
-;   fmov d6, x0
-;   mov v6.d[1], v6.d[1], x1
-;   cnt v17.16b, v6.16b
-;   addv b19, v17.16b
-;   umov w0, v19.b[0]
+;   fmov d4, x0
+;   mov v4.d[1], v4.d[1], x1
+;   cnt v7.16b, v4.16b
+;   addv b17, v7.16b
+;   umov w0, v17.b[0]
 ;   movz w1, #0
 ;   ret
 
@@ -260,10 +260,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   fmov d3, x0
-;   cnt v5.8b, v3.8b
-;   addv b7, v5.8b
-;   umov w0, v7.b[0]
+;   fmov d2, x0
+;   cnt v4.8b, v2.8b
+;   addv b6, v4.8b
+;   umov w0, v6.b[0]
 ;   ret
 
 function %d(i32) -> i32 {
@@ -273,10 +273,10 @@ block0(v0: i32):
 }
 
 ; block0:
-;   fmov s3, w0
-;   cnt v5.8b, v3.8b
-;   addv b7, v5.8b
-;   umov w0, v7.b[0]
+;   fmov s2, w0
+;   cnt v4.8b, v2.8b
+;   addv b6, v4.8b
+;   umov w0, v6.b[0]
 ;   ret
 
 function %d(i16) -> i16 {
@@ -286,10 +286,10 @@ block0(v0: i16):
 }
 
 ; block0:
-;   fmov s3, w0
-;   cnt v5.8b, v3.8b
-;   addp v7.8b, v5.8b, v5.8b
-;   umov w0, v7.b[0]
+;   fmov s2, w0
+;   cnt v4.8b, v2.8b
+;   addp v6.8b, v4.8b, v4.8b
+;   umov w0, v6.b[0]
 ;   ret
 
 function %d(i8) -> i8 {
@@ -299,9 +299,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   fmov s3, w0
-;   cnt v5.8b, v3.8b
-;   umov w0, v5.b[0]
+;   fmov s2, w0
+;   cnt v4.8b, v2.8b
+;   umov w0, v4.b[0]
 ;   ret
 
 function %sextend_i8() -> i32 {
@@ -312,8 +312,8 @@ block0:
 }
 
 ; block0:
-;   movn x1, #0
-;   sxtb w0, w1
+;   movn x0, #0
+;   sxtb w0, w0
 ;   ret
 
 function %sextend_i8() -> i32 {
@@ -324,8 +324,8 @@ block0:
 }
 
 ; block0:
-;   movn x1, #0
-;   sxtb w0, w1
+;   movn x0, #0
+;   sxtb w0, w0
 ;   ret
 
 function %bnot_i32(i32) -> i32 {
@@ -821,15 +821,15 @@ block0(v0: i128, v1: i8):
 }
 
 ; block0:
-;   lsl x6, x0, x2
-;   lsl x8, x1, x2
-;   orn w10, wzr, w2
-;   lsr x12, x0, #1
-;   lsr x14, x12, x10
-;   orr x1, x8, x14
+;   lsl x4, x0, x2
+;   lsl x6, x1, x2
+;   orn w8, wzr, w2
+;   lsr x10, x0, #1
+;   lsr x12, x10, x8
+;   orr x14, x6, x12
 ;   ands xzr, x2, #64
-;   csel x0, xzr, x6, ne
-;   csel x1, x6, x1, ne
+;   csel x0, xzr, x4, ne
+;   csel x1, x4, x14, ne
 ;   ret
 
 function %ishl_i128_i128(i128, i128) -> i128 {
@@ -839,15 +839,15 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   lsl x7, x0, x2
-;   lsl x9, x1, x2
-;   orn w11, wzr, w2
-;   lsr x13, x0, #1
-;   lsr x15, x13, x11
-;   orr x1, x9, x15
+;   lsl x5, x0, x2
+;   lsl x7, x1, x2
+;   orn w9, wzr, w2
+;   lsr x11, x0, #1
+;   lsr x13, x11, x9
+;   orr x15, x7, x13
 ;   ands xzr, x2, #64
-;   csel x0, xzr, x7, ne
-;   csel x1, x7, x1, ne
+;   csel x0, xzr, x5, ne
+;   csel x1, x5, x15, ne
 ;   ret
 
 function %ushr_i128_i8(i128, i8) -> i128 {
@@ -857,15 +857,15 @@ block0(v0: i128, v1: i8):
 }
 
 ; block0:
-;   lsr x6, x0, x2
-;   lsr x8, x1, x2
-;   orn w10, wzr, w2
-;   lsl x12, x1, #1
-;   lsl x14, x12, x10
-;   orr x0, x6, x14
+;   lsr x4, x0, x2
+;   lsr x6, x1, x2
+;   orn w8, wzr, w2
+;   lsl x10, x1, #1
+;   lsl x12, x10, x8
+;   orr x14, x4, x12
 ;   ands xzr, x2, #64
-;   csel x0, x8, x0, ne
-;   csel x1, xzr, x8, ne
+;   csel x0, x6, x14, ne
+;   csel x1, xzr, x6, ne
 ;   ret
 
 function %ushr_i128_i128(i128, i128) -> i128 {
@@ -875,15 +875,15 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   lsr x7, x0, x2
-;   lsr x9, x1, x2
-;   orn w11, wzr, w2
-;   lsl x13, x1, #1
-;   lsl x15, x13, x11
-;   orr x1, x7, x15
+;   lsr x5, x0, x2
+;   lsr x7, x1, x2
+;   orn w9, wzr, w2
+;   lsl x11, x1, #1
+;   lsl x13, x11, x9
+;   orr x15, x5, x13
 ;   ands xzr, x2, #64
-;   csel x0, x9, x1, ne
-;   csel x1, xzr, x9, ne
+;   csel x0, x7, x15, ne
+;   csel x1, xzr, x7, ne
 ;   ret
 
 function %sshr_i128_i8(i128, i8) -> i128 {
@@ -893,16 +893,16 @@ block0(v0: i128, v1: i8):
 }
 
 ; block0:
-;   lsr x6, x0, x2
-;   asr x8, x1, x2
-;   orn w10, wzr, w2
-;   lsl x12, x1, #1
-;   lsl x14, x12, x10
-;   asr x1, x1, #63
-;   orr x3, x6, x14
+;   lsr x4, x0, x2
+;   asr x6, x1, x2
+;   orn w8, wzr, w2
+;   lsl x10, x1, #1
+;   lsl x12, x10, x8
+;   asr x14, x1, #63
+;   orr x0, x4, x12
 ;   ands xzr, x2, #64
-;   csel x0, x8, x3, ne
-;   csel x1, x1, x8, ne
+;   csel x0, x6, x0, ne
+;   csel x1, x14, x6, ne
 ;   ret
 
 function %sshr_i128_i128(i128, i128) -> i128 {
@@ -912,15 +912,15 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   lsr x7, x0, x2
-;   asr x9, x1, x2
-;   orn w11, wzr, w2
-;   lsl x13, x1, #1
-;   lsl x15, x13, x11
-;   asr x1, x1, #63
-;   orr x3, x7, x15
+;   lsr x5, x0, x2
+;   asr x7, x1, x2
+;   orn w9, wzr, w2
+;   lsl x11, x1, #1
+;   lsl x13, x11, x9
+;   asr x15, x1, #63
+;   orr x1, x5, x13
 ;   ands xzr, x2, #64
-;   csel x0, x9, x3, ne
-;   csel x1, x1, x9, ne
+;   csel x0, x7, x1, ne
+;   csel x1, x15, x7, ne
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/bti.clif

@@ -33,7 +33,7 @@ block5(v5: i32):
 ; block0:
 ;   emit_island 44
 ;   subs wzr, w0, #3
-;   b.hs label1 ; csel x1, xzr, x0, hs ; csdb ; adr x15, pc+16 ; ldrsw x1, [x15, x1, uxtw #2] ; add x15, x15, x1 ; br x15 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))]
+;   b.hs label1 ; csel x15, xzr, x0, hs ; csdb ; adr x14, pc+16 ; ldrsw x15, [x14, x15, uxtw #2] ; add x14, x14, x15 ; br x14 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))]
 ; block1:
 ;   movz x5, #4
 ;   b label2
@@ -80,16 +80,17 @@ block2:
 
 ;   bti c
 ; block0:
-;   ldr x6, [x0]
+;   ldr x5, [x0]
+;   mov x8, x5
 ;   emit_island 36
 ;   subs wzr, w0, #1
-;   b.hs label1 ; csel x8, xzr, x0, hs ; csdb ; adr x7, pc+16 ; ldrsw x8, [x7, x8, uxtw #2] ; add x7, x7, x8 ; br x7 ; jt_entries [Label(MachLabel(2))]
+;   b.hs label1 ; csel x7, xzr, x0, hs ; csdb ; adr x6, pc+16 ; ldrsw x7, [x6, x7, uxtw #2] ; add x6, x6, x7 ; br x6 ; jt_entries [Label(MachLabel(2))]
 ; block1:
-;   mov x0, x6
+;   mov x0, x8
 ;   ret
 ; block2:
 ;   bti j
-;   mov x0, x6
+;   mov x0, x8
 ;   add x0, x0, #42
 ;   ret
 
@@ -105,8 +106,8 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/call-pauth.clif

@@ -14,8 +14,8 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   autiasp ; ret
 

cranelift/filetests/filetests/isa/aarch64/call.clif

@@ -14,8 +14,8 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -30,8 +30,8 @@ block0(v0: i32):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -54,8 +54,8 @@ block0(v0: i32):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -105,8 +105,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   mov x8, x0
-;   mov x13, x1
+;   mov x9, x0
+;   mov x8, x1
 ;   movz x0, #42
 ;   movz x1, #42
 ;   movz x2, #42
@@ -115,8 +115,7 @@ block0(v0: i8):
 ;   movz x5, #42
 ;   movz x6, #42
 ;   movz x7, #42
-;   mov x11, x8
-;   strb w11, [x13]
+;   strb w9, [x8]
 ;   ret
 
 function %f8() {
@@ -283,8 +282,8 @@ block0(v0: i64):
 ;   mov x1, x0
 ;   movz x0, #42
 ;   movz x2, #42
-;   ldr x7, 8 ; b 12 ; data TestCase(%f11) + 0
-;   blr x7
+;   ldr x6, 8 ; b 12 ; data TestCase(%f11) + 0
+;   blr x6
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -314,8 +313,8 @@ block0(v0: i64):
 ;   mov x2, x0
 ;   movz x3, #42
 ;   movz x0, #42
-;   ldr x7, 8 ; b 12 ; data TestCase(%f12) + 0
-;   blr x7
+;   ldr x6, 8 ; b 12 ; data TestCase(%f12) + 0
+;   blr x6
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -345,8 +344,8 @@ block0(v0: i64):
 ;   mov x1, x0
 ;   movz x2, #42
 ;   movz x0, #42
-;   ldr x7, 8 ; b 12 ; data TestCase(%f13) + 0
-;   blr x7
+;   ldr x6, 8 ; b 12 ; data TestCase(%f13) + 0
+;   blr x6
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -381,12 +380,12 @@ block0(v0: i128, v1: i64):
 ;   mov x4, x0
 ;   str x1, [sp, #8]
 ;   mov x5, x1
-;   ldr x12, 8 ; b 12 ; data TestCase(%f14) + 0
+;   ldr x10, 8 ; b 12 ; data TestCase(%f14) + 0
 ;   mov x0, x4
 ;   mov x2, x4
 ;   mov x1, x5
 ;   mov x3, x5
-;   blr x12
+;   blr x10
 ;   add sp, sp, #16
 ;   virtual_sp_offset_adjust -16
 ;   ldp fp, lr, [sp], #16
@@ -423,12 +422,12 @@ block0(v0: i128, v1: i64):
 ;   mov x4, x0
 ;   str x1, [sp, #8]
 ;   mov x5, x1
-;   ldr x12, 8 ; b 12 ; data TestCase(%f15) + 0
+;   ldr x10, 8 ; b 12 ; data TestCase(%f15) + 0
 ;   mov x0, x4
 ;   mov x2, x4
 ;   mov x1, x5
 ;   mov x3, x5
-;   blr x12
+;   blr x10
 ;   add sp, sp, #16
 ;   virtual_sp_offset_adjust -16
 ;   ldp fp, lr, [sp], #16
@@ -442,10 +441,10 @@ block0:
 }
 
 ; block0:
-;   mov x11, x0
+;   mov x6, x0
 ;   movz x0, #0
-;   movz x7, #1
-;   str w7, [x11]
+;   movz x4, #1
+;   str w4, [x6]
 ;   ret
 
 function %f17(i64 sret) {
@@ -473,8 +472,8 @@ block0(v0: i64):
 ;   mov fp, sp
 ; block0:
 ;   mov x8, x0
-;   ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
-;   blr x4
+;   ldr x3, 8 ; b 12 ; data TestCase(%g) + 0
+;   blr x3
 ;   ldp fp, lr, [sp], #16
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/compare_zero.clif

@@ -57,8 +57,8 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   cmeq v3.4s, v0.4s, #0
-;   mvn v0.16b, v3.16b
+;   cmeq v2.4s, v0.4s, #0
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f2_vconst(i32x4) -> i32x4 {
@@ -69,8 +69,8 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   cmeq v3.4s, v0.4s, #0
-;   mvn v0.16b, v3.16b
+;   cmeq v2.4s, v0.4s, #0
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f3(i64x2) -> i64x2 {
@@ -82,8 +82,8 @@ block0(v0: i64x2):
 }
 
 ; block0:
-;   cmeq v3.2d, v0.2d, #0
-;   mvn v0.16b, v3.16b
+;   cmeq v2.2d, v0.2d, #0
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f3_vconst(i64x2) -> i64x2 {
@@ -94,8 +94,8 @@ block0(v0: i64x2):
 }
 
 ; block0:
-;   cmeq v3.2d, v0.2d, #0
-;   mvn v0.16b, v3.16b
+;   cmeq v2.2d, v0.2d, #0
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f4(i8x16) -> i8x16 {
@@ -337,8 +337,8 @@ block0(v0: f64x2):
 }
 
 ; block0:
-;   fcmeq v3.2d, v0.2d, #0.0
-;   mvn v0.16b, v3.16b
+;   fcmeq v2.2d, v0.2d, #0.0
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f14_vconst(f64x2) -> i64x2 {
@@ -349,8 +349,8 @@ block0(v0: f64x2):
 }
 
 ; block0:
-;   fcmeq v3.2d, v0.2d, #0.0
-;   mvn v0.16b, v3.16b
+;   fcmeq v2.2d, v0.2d, #0.0
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f15(f32x4) -> i32x4 {
@@ -362,8 +362,8 @@ block0(v0: f32x4):
 }
 
 ; block0:
-;   fcmeq v3.4s, v0.4s, #0.0
-;   mvn v0.16b, v3.16b
+;   fcmeq v2.4s, v0.4s, #0.0
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f15_vconst(f32x4) -> i32x4 {
@@ -374,8 +374,8 @@ block0(v0: f32x4):
 }
 
 ; block0:
-;   fcmeq v3.4s, v0.4s, #0.0
-;   mvn v0.16b, v3.16b
+;   fcmeq v2.4s, v0.4s, #0.0
+;   mvn v0.16b, v2.16b
 ;   ret
 
 function %f16(f32x4) -> i32x4 {

cranelift/filetests/filetests/isa/aarch64/condbr.clif

@@ -45,10 +45,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, lo
+;   cset x6, lo
 ;   subs xzr, x1, x3
-;   cset x10, lt
-;   csel x0, x7, x10, eq
+;   cset x9, lt
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_ult_i128(i128, i128) -> i8 {
@@ -59,10 +59,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, lo
+;   cset x6, lo
 ;   subs xzr, x1, x3
-;   cset x10, lo
-;   csel x0, x7, x10, eq
+;   cset x9, lo
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_sle_i128(i128, i128) -> i8 {
@@ -73,10 +73,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, ls
+;   cset x6, ls
 ;   subs xzr, x1, x3
-;   cset x10, le
-;   csel x0, x7, x10, eq
+;   cset x9, le
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_ule_i128(i128, i128) -> i8 {
@@ -87,10 +87,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, ls
+;   cset x6, ls
 ;   subs xzr, x1, x3
-;   cset x10, ls
-;   csel x0, x7, x10, eq
+;   cset x9, ls
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_sgt_i128(i128, i128) -> i8 {
@@ -101,10 +101,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, hi
+;   cset x6, hi
 ;   subs xzr, x1, x3
-;   cset x10, gt
-;   csel x0, x7, x10, eq
+;   cset x9, gt
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_ugt_i128(i128, i128) -> i8 {
@@ -115,10 +115,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, hi
+;   cset x6, hi
 ;   subs xzr, x1, x3
-;   cset x10, hi
-;   csel x0, x7, x10, eq
+;   cset x9, hi
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_sge_i128(i128, i128) -> i8 {
@@ -129,10 +129,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, hs
+;   cset x6, hs
 ;   subs xzr, x1, x3
-;   cset x10, ge
-;   csel x0, x7, x10, eq
+;   cset x9, ge
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %icmp_uge_i128(i128, i128) -> i8 {
@@ -143,10 +143,10 @@ block0(v0: i128, v1: i128):
 
 ; block0:
 ;   subs xzr, x0, x2
-;   cset x7, hs
+;   cset x6, hs
 ;   subs xzr, x1, x3
-;   cset x10, hs
-;   csel x0, x7, x10, eq
+;   cset x9, hs
+;   csel x0, x6, x9, eq
 ;   ret
 
 function %f(i64, i64) -> i64 {

cranelift/filetests/filetests/isa/aarch64/condops.clif

@@ -11,8 +11,8 @@ block0(v0: i8, v1: i8, v2: i8):
 }
 
 ; block0:
-;   uxtb w5, w0
-;   subs wzr, w5, #42
+;   uxtb w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -25,8 +25,8 @@ block0(v0: i8, v1: i16, v2: i16):
 }
 
 ; block0:
-;   uxtb w5, w0
-;   subs wzr, w5, #42
+;   uxtb w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -39,8 +39,8 @@ block0(v0: i8, v1: i32, v2: i32):
 }
 
 ; block0:
-;   uxtb w5, w0
-;   subs wzr, w5, #42
+;   uxtb w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -53,8 +53,8 @@ block0(v0: i8, v1: i64, v2: i64):
 }
 
 ; block0:
-;   uxtb w5, w0
-;   subs wzr, w5, #42
+;   uxtb w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -67,8 +67,8 @@ block0(v0: i8, v1: i128, v2: i128):
 }
 
 ; block0:
-;   uxtb w8, w0
-;   subs wzr, w8, #42
+;   uxtb w6, w0
+;   subs wzr, w6, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
@@ -82,8 +82,8 @@ block0(v0: i16, v1: i8, v2: i8):
 }
 
 ; block0:
-;   uxth w5, w0
-;   subs wzr, w5, #42
+;   uxth w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -96,8 +96,8 @@ block0(v0: i16, v1: i16, v2: i16):
 }
 
 ; block0:
-;   uxth w5, w0
-;   subs wzr, w5, #42
+;   uxth w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -110,8 +110,8 @@ block0(v0: i16, v1: i32, v2: i32):
 }
 
 ; block0:
-;   uxth w5, w0
-;   subs wzr, w5, #42
+;   uxth w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -124,8 +124,8 @@ block0(v0: i16, v1: i64, v2: i64):
 }
 
 ; block0:
-;   uxth w5, w0
-;   subs wzr, w5, #42
+;   uxth w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
@@ -138,8 +138,8 @@ block0(v0: i16, v1: i128, v2: i128):
 }
 
 ; block0:
-;   uxth w8, w0
-;   subs wzr, w8, #42
+;   uxth w6, w0
+;   subs wzr, w6, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
@@ -286,10 +286,10 @@ block0(v0: i128, v1: i8, v2: i8):
 }
 
 ; block0:
-;   movz x7, #42
-;   movz w9, #0
-;   subs xzr, x0, x7
-;   ccmp x1, x9, #nzcv, eq
+;   movz x6, #42
+;   movz w8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 
@@ -303,10 +303,10 @@ block0(v0: i128, v1: i16, v2: i16):
 }
 
 ; block0:
-;   movz x7, #42
-;   movz w9, #0
-;   subs xzr, x0, x7
-;   ccmp x1, x9, #nzcv, eq
+;   movz x6, #42
+;   movz w8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 
@@ -320,10 +320,10 @@ block0(v0: i128, v1: i32, v2: i32):
 }
 
 ; block0:
-;   movz x7, #42
-;   movz w9, #0
-;   subs xzr, x0, x7
-;   ccmp x1, x9, #nzcv, eq
+;   movz x6, #42
+;   movz w8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 
@@ -337,10 +337,10 @@ block0(v0: i128, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x7, #42
-;   movz w9, #0
-;   subs xzr, x0, x7
-;   ccmp x1, x9, #nzcv, eq
+;   movz x6, #42
+;   movz w8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 
@@ -354,10 +354,10 @@ block0(v0: i128, v1: i128, v2: i128):
 }
 
 ; block0:
-;   movz x11, #42
-;   movz w13, #0
-;   subs xzr, x0, x11
-;   ccmp x1, x13, #nzcv, eq
+;   movz x9, #42
+;   movz w11, #0
+;   subs xzr, x0, x9
+;   ccmp x1, x11, #nzcv, eq
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   ret
@@ -371,8 +371,8 @@ block0(v0: i8, v1: i8, v2: i8):
 }
 
 ; block0:
-;   uxtb w5, w0
-;   subs wzr, w5, #42
+;   uxtb w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -386,8 +386,8 @@ block0(v0: i8, v1: i16, v2: i16):
 }
 
 ; block0:
-;   uxtb w5, w0
-;   subs wzr, w5, #42
+;   uxtb w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -401,8 +401,8 @@ block0(v0: i8, v1: i32, v2: i32):
 }
 
 ; block0:
-;   uxtb w5, w0
-;   subs wzr, w5, #42
+;   uxtb w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -416,8 +416,8 @@ block0(v0: i8, v1: i64, v2: i64):
 }
 
 ; block0:
-;   uxtb w5, w0
-;   subs wzr, w5, #42
+;   uxtb w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -431,8 +431,8 @@ block0(v0: i8, v1: i128, v2: i128):
 }
 
 ; block0:
-;   uxtb w8, w0
-;   subs wzr, w8, #42
+;   uxtb w6, w0
+;   subs wzr, w6, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   csdb
@@ -447,8 +447,8 @@ block0(v0: i16, v1: i8, v2: i8):
 }
 
 ; block0:
-;   uxth w5, w0
-;   subs wzr, w5, #42
+;   uxth w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -462,8 +462,8 @@ block0(v0: i16, v1: i16, v2: i16):
 }
 
 ; block0:
-;   uxth w5, w0
-;   subs wzr, w5, #42
+;   uxth w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -477,8 +477,8 @@ block0(v0: i16, v1: i32, v2: i32):
 }
 
 ; block0:
-;   uxth w5, w0
-;   subs wzr, w5, #42
+;   uxth w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -492,8 +492,8 @@ block0(v0: i16, v1: i64, v2: i64):
 }
 
 ; block0:
-;   uxth w5, w0
-;   subs wzr, w5, #42
+;   uxth w4, w0
+;   subs wzr, w4, #42
 ;   csel x0, x1, x2, eq
 ;   csdb
 ;   ret
@@ -507,8 +507,8 @@ block0(v0: i16, v1: i128, v2: i128):
 }
 
 ; block0:
-;   uxth w8, w0
-;   subs wzr, w8, #42
+;   uxth w6, w0
+;   subs wzr, w6, #42
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   csdb
@@ -666,10 +666,10 @@ block0(v0: i128, v1: i8, v2: i8):
 }
 
 ; block0:
-;   movz x7, #42
-;   movz w9, #0
-;   subs xzr, x0, x7
-;   ccmp x1, x9, #nzcv, eq
+;   movz x6, #42
+;   movz w8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
@@ -684,10 +684,10 @@ block0(v0: i128, v1: i16, v2: i16):
 }
 
 ; block0:
-;   movz x7, #42
-;   movz w9, #0
-;   subs xzr, x0, x7
-;   ccmp x1, x9, #nzcv, eq
+;   movz x6, #42
+;   movz w8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
@@ -702,10 +702,10 @@ block0(v0: i128, v1: i32, v2: i32):
 }
 
 ; block0:
-;   movz x7, #42
-;   movz w9, #0
-;   subs xzr, x0, x7
-;   ccmp x1, x9, #nzcv, eq
+;   movz x6, #42
+;   movz w8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
@@ -720,10 +720,10 @@ block0(v0: i128, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x7, #42
-;   movz w9, #0
-;   subs xzr, x0, x7
-;   ccmp x1, x9, #nzcv, eq
+;   movz x6, #42
+;   movz w8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
 ;   ret
@@ -738,10 +738,10 @@ block0(v0: i128, v1: i128, v2: i128):
 }
 
 ; block0:
-;   movz x11, #42
-;   movz w13, #0
-;   subs xzr, x0, x11
-;   ccmp x1, x13, #nzcv, eq
+;   movz x9, #42
+;   movz w11, #0
+;   subs xzr, x0, x9
+;   ccmp x1, x11, #nzcv, eq
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
 ;   csdb
@@ -755,8 +755,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w3, w0
-;   subs wzr, w3, #42
+;   uxtb w2, w0
+;   subs wzr, w2, #42
 ;   cset x0, eq
 ;   ret
 
@@ -767,9 +767,9 @@ block0(v0: i8, v1: i8, v2: i8):
 }
 
 ; block0:
-;   and w5, w1, w0
-;   bic w7, w2, w0
-;   orr w0, w5, w7
+;   and w4, w1, w0
+;   bic w6, w2, w0
+;   orr w0, w4, w6
 ;   ret
 
 function %i(i8, i8, i8) -> i8 {

cranelift/filetests/filetests/isa/aarch64/constants.clif

@@ -224,8 +224,8 @@ block0:
 }
 
 ; block0:
-;   movz x2, #16457, LSL #48
-;   fmov d0, x2
+;   movz x1, #16457, LSL #48
+;   fmov d0, x1
 ;   ret
 
 function %f() -> f32 {
@@ -235,8 +235,8 @@ block0:
 }
 
 ; block0:
-;   movz x2, #16968, LSL #16
-;   fmov s0, w2
+;   movz x1, #16968, LSL #16
+;   fmov s0, w1
 ;   ret
 
 function %f() -> f64 {

cranelift/filetests/filetests/isa/aarch64/dynamic-simd-narrow.clif

@@ -15,9 +15,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v4.4h, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
-;   sqxtn v0.8b, v4.8h
+;   dup v3.4h, w0
+;   mov v3.d[1], v3.d[1], v3.d[0]
+;   sqxtn v0.8b, v3.8h
 ;   ret
 
 function %snarrow_i16x8(i16) -> i8x16 {
@@ -34,9 +34,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v6.8h, w0
-;   sqxtn v0.8b, v6.8h
-;   sqxtn2 v0.16b, v0.16b, v6.8h
+;   dup v5.8h, w0
+;   sqxtn v0.8b, v5.8h
+;   sqxtn2 v0.16b, v0.16b, v5.8h
 ;   ret
 
 function %snarrow_i32x2(i32) -> i16x4 {
@@ -53,9 +53,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v4.2s, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
-;   sqxtn v0.4h, v4.4s
+;   dup v3.2s, w0
+;   mov v3.d[1], v3.d[1], v3.d[0]
+;   sqxtn v0.4h, v3.4s
 ;   ret
 
 function %snarrow_i32x4(i32) -> i16x8 {
@@ -72,9 +72,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v6.4s, w0
-;   sqxtn v0.4h, v6.4s
-;   sqxtn2 v0.8h, v0.8h, v6.4s
+;   dup v5.4s, w0
+;   sqxtn v0.4h, v5.4s
+;   sqxtn2 v0.8h, v0.8h, v5.4s
 ;   ret
 
 function %snarrow_i64x2(i64) -> i32x4 {
@@ -91,9 +91,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   dup v6.2d, x0
-;   sqxtn v0.2s, v6.2d
-;   sqxtn2 v0.4s, v0.4s, v6.2d
+;   dup v5.2d, x0
+;   sqxtn v0.2s, v5.2d
+;   sqxtn2 v0.4s, v0.4s, v5.2d
 ;   ret
 
 function %unarrow_i16x4(i16) -> i8x8 {
@@ -110,9 +110,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v4.4h, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
-;   sqxtun v0.8b, v4.8h
+;   dup v3.4h, w0
+;   mov v3.d[1], v3.d[1], v3.d[0]
+;   sqxtun v0.8b, v3.8h
 ;   ret
 
 function %unarrow_i16x8(i16) -> i8x16 {
@@ -129,9 +129,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v6.8h, w0
-;   sqxtun v0.8b, v6.8h
-;   sqxtun2 v0.16b, v0.16b, v6.8h
+;   dup v5.8h, w0
+;   sqxtun v0.8b, v5.8h
+;   sqxtun2 v0.16b, v0.16b, v5.8h
 ;   ret
 
 function %unarrow_i32x2(i32) -> i16x4 {
@@ -148,9 +148,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v4.2s, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
-;   sqxtun v0.4h, v4.4s
+;   dup v3.2s, w0
+;   mov v3.d[1], v3.d[1], v3.d[0]
+;   sqxtun v0.4h, v3.4s
 ;   ret
 
 function %unarrow_i32x4(i32) -> i16x8 {
@@ -167,9 +167,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v6.4s, w0
-;   sqxtun v0.4h, v6.4s
-;   sqxtun2 v0.8h, v0.8h, v6.4s
+;   dup v5.4s, w0
+;   sqxtun v0.4h, v5.4s
+;   sqxtun2 v0.8h, v0.8h, v5.4s
 ;   ret
 
 function %unarrow_i64x2(i64) -> i32x4 {
@@ -186,9 +186,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   dup v6.2d, x0
-;   sqxtun v0.2s, v6.2d
-;   sqxtun2 v0.4s, v0.4s, v6.2d
+;   dup v5.2d, x0
+;   sqxtun v0.2s, v5.2d
+;   sqxtun2 v0.4s, v0.4s, v5.2d
 ;   ret
 
 function %uunarrow_i16x4(i16) -> i8x8 {
@@ -205,9 +205,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v4.4h, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
-;   uqxtn v0.8b, v4.8h
+;   dup v3.4h, w0
+;   mov v3.d[1], v3.d[1], v3.d[0]
+;   uqxtn v0.8b, v3.8h
 ;   ret
 
 function %uunarrow_i16x8(i16) -> i8x16 {
@@ -224,9 +224,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v6.8h, w0
-;   uqxtn v0.8b, v6.8h
-;   uqxtn2 v0.16b, v0.16b, v6.8h
+;   dup v5.8h, w0
+;   uqxtn v0.8b, v5.8h
+;   uqxtn2 v0.16b, v0.16b, v5.8h
 ;   ret
 
 function %uunarrow_i32x2(i32) -> i16x4 {
@@ -243,9 +243,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v4.2s, w0
-;   mov v4.d[1], v4.d[1], v4.d[0]
-;   uqxtn v0.4h, v4.4s
+;   dup v3.2s, w0
+;   mov v3.d[1], v3.d[1], v3.d[0]
+;   uqxtn v0.4h, v3.4s
 ;   ret
 
 function %uunarrow_i32x4(i32) -> i16x8 {
@@ -262,9 +262,9 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v6.4s, w0
-;   uqxtn v0.4h, v6.4s
-;   uqxtn2 v0.8h, v0.8h, v6.4s
+;   dup v5.4s, w0
+;   uqxtn v0.4h, v5.4s
+;   uqxtn2 v0.8h, v0.8h, v5.4s
 ;   ret
 
 function %uunarrow_i64x2(i64) -> i32x4 {
@@ -281,8 +281,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   dup v6.2d, x0
-;   uqxtn v0.2s, v6.2d
-;   uqxtn2 v0.4s, v0.4s, v6.2d
+;   dup v5.2d, x0
+;   uqxtn v0.2s, v5.2d
+;   uqxtn2 v0.4s, v0.4s, v5.2d
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/dynamic-simd-neon.clif

@@ -14,9 +14,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   dup v7.16b, w0
-;   dup v16.16b, w1
-;   add v0.16b, v7.16b, v16.16b
+;   dup v6.16b, w0
+;   dup v7.16b, w1
+;   add v0.16b, v6.16b, v7.16b
 ;   ret
 
 function %i16x8_splat_add(i16, i16) -> i16x8 {
@@ -32,9 +32,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   dup v7.8h, w0
-;   dup v16.8h, w1
-;   add v0.8h, v7.8h, v16.8h
+;   dup v6.8h, w0
+;   dup v7.8h, w1
+;   add v0.8h, v6.8h, v7.8h
 ;   ret
 
 function %i32x4_splat_mul(i32, i32) -> i32x4 {
@@ -50,9 +50,9 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   dup v7.4s, w0
-;   dup v16.4s, w1
-;   mul v0.4s, v7.4s, v16.4s
+;   dup v6.4s, w0
+;   dup v7.4s, w1
+;   mul v0.4s, v6.4s, v7.4s
 ;   ret
 
 function %i64x2_splat_sub(i64, i64) -> i64x2 {
@@ -68,9 +68,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   dup v7.2d, x0
-;   dup v16.2d, x1
-;   sub v0.2d, v7.2d, v16.2d
+;   dup v6.2d, x0
+;   dup v7.2d, x1
+;   sub v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f32x4_splat_add(f32, f32) -> f32x4 {
@@ -86,9 +86,9 @@ block0(v0: f32, v1: f32):
 }
 
 ; block0:
-;   dup v7.4s, v0.s[0]
-;   dup v16.4s, v1.s[0]
-;   fadd v0.4s, v7.4s, v16.4s
+;   dup v6.4s, v0.s[0]
+;   dup v7.4s, v1.s[0]
+;   fadd v0.4s, v6.4s, v7.4s
 ;   ret
 
 function %f64x2_splat_sub(f64, f64) -> f64x2 {
@@ -104,9 +104,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v7.2d, v0.d[0]
-;   dup v16.2d, v1.d[0]
-;   fsub v0.2d, v7.2d, v16.2d
+;   dup v6.2d, v0.d[0]
+;   dup v7.2d, v1.d[0]
+;   fsub v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f64x2_splat_mul(f64, f64) -> f64x2 {
@@ -122,9 +122,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v7.2d, v0.d[0]
-;   dup v16.2d, v1.d[0]
-;   fmul v0.2d, v7.2d, v16.2d
+;   dup v6.2d, v0.d[0]
+;   dup v7.2d, v1.d[0]
+;   fmul v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f64x2_splat_div(f64, f64) -> f64x2 {
@@ -140,9 +140,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v7.2d, v0.d[0]
-;   dup v16.2d, v1.d[0]
-;   fdiv v0.2d, v7.2d, v16.2d
+;   dup v6.2d, v0.d[0]
+;   dup v7.2d, v1.d[0]
+;   fdiv v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f64x2_splat_min(f64, f64) -> f64x2 {
@@ -158,9 +158,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v7.2d, v0.d[0]
-;   dup v16.2d, v1.d[0]
-;   fmin v0.2d, v7.2d, v16.2d
+;   dup v6.2d, v0.d[0]
+;   dup v7.2d, v1.d[0]
+;   fmin v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f64x2_splat_max(f64, f64) -> f64x2 {
@@ -176,9 +176,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v7.2d, v0.d[0]
-;   dup v16.2d, v1.d[0]
-;   fmax v0.2d, v7.2d, v16.2d
+;   dup v6.2d, v0.d[0]
+;   dup v7.2d, v1.d[0]
+;   fmax v0.2d, v6.2d, v7.2d
 ;   ret
 
 function %f64x2_splat_min_pseudo(f64, f64) -> f64x2 {
@@ -194,10 +194,10 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v16.2d, v0.d[0]
-;   dup v17.2d, v1.d[0]
-;   fcmgt v0.2d, v16.2d, v17.2d
-;   bsl v0.16b, v0.16b, v17.16b, v16.16b
+;   dup v7.2d, v0.d[0]
+;   dup v16.2d, v1.d[0]
+;   fcmgt v0.2d, v7.2d, v16.2d
+;   bsl v0.16b, v0.16b, v16.16b, v7.16b
 ;   ret
 
 function %f64x2_splat_max_pseudo(f64, f64) -> f64x2 {
@@ -213,9 +213,9 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   dup v16.2d, v0.d[0]
-;   dup v17.2d, v1.d[0]
-;   fcmgt v0.2d, v17.2d, v16.2d
-;   bsl v0.16b, v0.16b, v17.16b, v16.16b
+;   dup v7.2d, v0.d[0]
+;   dup v16.2d, v1.d[0]
+;   fcmgt v0.2d, v16.2d, v7.2d
+;   bsl v0.16b, v0.16b, v16.16b, v7.16b
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/dynamic-simd-widen.clif

@@ -15,8 +15,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   dup v5.16b, w0
-;   sxtl2 v0.8h, v5.16b
+;   dup v4.16b, w0
+;   sxtl2 v0.8h, v4.16b
 ;   ret
 
 function %swidenhigh_i16x8(i16) -> i32x4 {
@@ -33,8 +33,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v5.8h, w0
-;   sxtl2 v0.4s, v5.8h
+;   dup v4.8h, w0
+;   sxtl2 v0.4s, v4.8h
 ;   ret
 
 function %swidenhigh_i32x4(i32) -> i64x2 {
@@ -51,8 +51,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v5.4s, w0
-;   sxtl2 v0.2d, v5.4s
+;   dup v4.4s, w0
+;   sxtl2 v0.2d, v4.4s
 ;   ret
 
 function %swidenlow_i8x16(i8) -> i16x8 {
@@ -69,8 +69,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   dup v5.16b, w0
-;   sxtl v0.8h, v5.8b
+;   dup v4.16b, w0
+;   sxtl v0.8h, v4.8b
 ;   ret
 
 function %swidenlow_i16x8(i16) -> i32x4 {
@@ -87,8 +87,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   dup v5.8h, w0
-;   sxtl v0.4s, v5.4h
+;   dup v4.8h, w0
+;   sxtl v0.4s, v4.4h
 ;   ret
 
 function %swidenlow_i32x4(i32) -> i64x2 {
@@ -105,6 +105,7 @@ block0(v0: i32):
 }
 
 ; block0:
-;   dup v5.4s, w0
-;   sxtl v0.2d, v5.2s
+;   dup v4.4s, w0
+;   sxtl v0.2d, v4.2s
 ;   ret
+

cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif

@@ -80,8 +80,8 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #16
 ; block0:
-;   mov x3, sp
-;   ldr q0, [x3]
+;   mov x2, sp
+;   ldr q0, [x2]
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret

cranelift/filetests/filetests/isa/aarch64/extend-op.clif

@@ -11,8 +11,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sxtb x4, w0
-;   add x0, x4, #42
+;   sxtb x3, w0
+;   add x0, x3, #42
 ;   ret
 
 function %f2(i8, i64) -> i64 {

cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif

@@ -9,8 +9,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w3, w0
-;   ucvtf s0, w3
+;   uxtb w2, w0
+;   ucvtf s0, w2
 ;   ret
 
 function u0:0(i8) -> f64 {
@@ -20,8 +20,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w3, w0
-;   ucvtf d0, w3
+;   uxtb w2, w0
+;   ucvtf d0, w2
 ;   ret
 
 function u0:0(i16) -> f32 {
@@ -31,8 +31,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   uxth w3, w0
-;   ucvtf s0, w3
+;   uxth w2, w0
+;   ucvtf s0, w2
 ;   ret
 
 function u0:0(i16) -> f64 {
@@ -42,8 +42,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   uxth w3, w0
-;   ucvtf d0, w3
+;   uxth w2, w0
+;   ucvtf d0, w2
 ;   ret
 
 function u0:0(f32) -> i8 {
@@ -55,12 +55,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
-;   fcmp s0, s5
+;   fmov s4, #-1
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #17280, LSL #16
-;   fmov s18, w10
-;   fcmp s0, s18
+;   movz x9, #17280, LSL #16
+;   fmov s17, w9
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
@@ -74,12 +74,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
-;   fcmp d0, d5
+;   fmov d4, #-1
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16496, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #16496, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
@@ -93,12 +93,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
-;   fcmp s0, s5
+;   fmov s4, #-1
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #18304, LSL #16
-;   fmov s18, w10
-;   fcmp s0, s18
+;   movz x9, #18304, LSL #16
+;   fmov s17, w9
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
@@ -112,12 +112,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
-;   fcmp d0, d5
+;   fmov d4, #-1
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16624, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #16624, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret

cranelift/filetests/filetests/isa/aarch64/fcvt.clif

@@ -8,8 +8,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sxtb w3, w0
-;   scvtf s0, w3
+;   sxtb w2, w0
+;   scvtf s0, w2
 ;   ret
 
 function %f2(i16) -> f32 {
@@ -19,8 +19,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sxth w3, w0
-;   scvtf s0, w3
+;   sxth w2, w0
+;   scvtf s0, w2
 ;   ret
 
 function %f3(i32) -> f32 {
@@ -50,8 +50,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sxtb w3, w0
-;   scvtf d0, w3
+;   sxtb w2, w0
+;   scvtf d0, w2
 ;   ret
 
 function %f6(i16) -> f64 {
@@ -61,8 +61,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sxth w3, w0
-;   scvtf d0, w3
+;   sxth w2, w0
+;   scvtf d0, w2
 ;   ret
 
 function %f7(i32) -> f64 {
@@ -92,8 +92,8 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   sxtl v3.2d, v0.2s
-;   scvtf v0.2d, v3.2d
+;   sxtl v2.2d, v0.2s
+;   scvtf v0.2d, v2.2d
 ;   ret
 
 function %f10(i8, i16, i32, i64) -> f32 {
@@ -109,15 +109,15 @@ block0(v0: i8, v1: i16, v2: i32, v3: i64):
 }
 
 ; block0:
-;   uxtb w13, w0
-;   ucvtf s23, w13
-;   uxth w13, w1
-;   ucvtf s24, w13
-;   ucvtf s22, w2
-;   ucvtf s25, x3
-;   fadd s23, s23, s24
-;   fadd s22, s23, s22
-;   fadd s0, s22, s25
+;   uxtb w12, w0
+;   ucvtf s22, w12
+;   uxth w12, w1
+;   ucvtf s23, w12
+;   ucvtf s21, w2
+;   ucvtf s24, x3
+;   fadd s22, s22, s23
+;   fadd s21, s22, s21
+;   fadd s0, s21, s24
 ;   ret
 
 function %f11(i32x4) -> f64x2 {
@@ -128,8 +128,8 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   uxtl v4.2d, v0.2s
-;   ucvtf v0.2d, v4.2d
+;   uxtl v3.2d, v0.2s
+;   ucvtf v0.2d, v3.2d
 ;   ret
 
 function %f12(i32x4) -> f32x4 {
@@ -151,12 +151,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
-;   fcmp s0, s5
+;   fmov s4, #-1
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #20352, LSL #16
-;   fmov s18, w10
-;   fcmp s0, s18
+;   movz x9, #20352, LSL #16
+;   fmov s17, w9
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
@@ -170,12 +170,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
-;   fcmp s0, s5
+;   fmov s4, #-1
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #24448, LSL #16
-;   fmov s18, w10
-;   fcmp s0, s18
+;   movz x9, #24448, LSL #16
+;   fmov s17, w9
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, s0
 ;   ret
@@ -189,12 +189,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
-;   fcmp d0, d5
+;   fmov d4, #-1
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16880, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #16880, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
@@ -208,12 +208,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
-;   fcmp d0, d5
+;   fmov d4, #-1
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #17392, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #17392, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, d0
 ;   ret
@@ -267,13 +267,13 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   movz x6, #52992, LSL #16
-;   fmov s6, w6
-;   fcmp s0, s6
+;   movz x5, #52992, LSL #16
+;   fmov s5, w5
+;   fcmp s0, s5
 ;   b.ge 8 ; udf
-;   movz x12, #20224, LSL #16
-;   fmov s20, w12
-;   fcmp s0, s20
+;   movz x11, #20224, LSL #16
+;   fmov s19, w11
+;   fcmp s0, s19
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, s0
 ;   ret
@@ -287,13 +287,13 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   movz x6, #57088, LSL #16
-;   fmov s6, w6
-;   fcmp s0, s6
+;   movz x5, #57088, LSL #16
+;   fmov s5, w5
+;   fcmp s0, s5
 ;   b.ge 8 ; udf
-;   movz x12, #24320, LSL #16
-;   fmov s20, w12
-;   fcmp s0, s20
+;   movz x11, #24320, LSL #16
+;   fmov s19, w11
+;   fcmp s0, s19
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, s0
 ;   ret
@@ -307,12 +307,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   ldr d5, pc+8 ; b 12 ; data.f64 -2147483649
-;   fcmp d0, d5
+;   ldr d4, pc+8 ; b 12 ; data.f64 -2147483649
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16864, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #16864, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, d0
 ;   ret
@@ -326,13 +326,13 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   movz x6, #50144, LSL #48
-;   fmov d6, x6
-;   fcmp d0, d6
+;   movz x5, #50144, LSL #48
+;   fmov d5, x5
+;   fcmp d0, d5
 ;   b.ge 8 ; udf
-;   movz x12, #17376, LSL #48
-;   fmov d20, x12
-;   fcmp d0, d20
+;   movz x11, #17376, LSL #48
+;   fmov d19, x11
+;   fcmp d0, d19
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, d0
 ;   ret
@@ -404,10 +404,10 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvtzu w3, s0
-;   movz w5, #255
-;   subs wzr, w3, w5
-;   csel x0, x5, x3, hi
+;   fcvtzu w2, s0
+;   movz w4, #255
+;   subs wzr, w2, w4
+;   csel x0, x4, x2, hi
 ;   ret
 
 function %f32(f32) -> i8 {
@@ -417,13 +417,13 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvtzs w3, s0
-;   movz w5, #127
-;   movn x7, #127
-;   subs wzr, w3, w5
-;   csel x10, x5, x3, gt
-;   subs wzr, w10, w7
-;   csel x0, x7, x10, lt
+;   fcvtzs w2, s0
+;   movz w4, #127
+;   movn x6, #127
+;   subs wzr, w2, w4
+;   csel x9, x4, x2, gt
+;   subs wzr, w9, w6
+;   csel x0, x6, x9, lt
 ;   ret
 
 function %f33(f32) -> i16 {
@@ -433,10 +433,10 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvtzu w3, s0
-;   movz w5, #65535
-;   subs wzr, w3, w5
-;   csel x0, x5, x3, hi
+;   fcvtzu w2, s0
+;   movz w4, #65535
+;   subs wzr, w2, w4
+;   csel x0, x4, x2, hi
 ;   ret
 
 function %f34(f32) -> i16 {
@@ -446,13 +446,13 @@ block0(v0: f32):
 }
 
 ; block0:
-;   fcvtzs w3, s0
-;   movz w5, #32767
-;   movn x7, #32767
-;   subs wzr, w3, w5
-;   csel x10, x5, x3, gt
-;   subs wzr, w10, w7
-;   csel x0, x7, x10, lt
+;   fcvtzs w2, s0
+;   movz w4, #32767
+;   movn x6, #32767
+;   subs wzr, w2, w4
+;   csel x9, x4, x2, gt
+;   subs wzr, w9, w6
+;   csel x0, x6, x9, lt
 ;   ret
 
 function %f35(f64) -> i8 {
@@ -462,10 +462,10 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvtzu w3, d0
-;   movz w5, #255
-;   subs wzr, w3, w5
-;   csel x0, x5, x3, hi
+;   fcvtzu w2, d0
+;   movz w4, #255
+;   subs wzr, w2, w4
+;   csel x0, x4, x2, hi
 ;   ret
 
 function %f36(f64) -> i8 {
@@ -475,13 +475,13 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvtzs w3, d0
-;   movz w5, #127
-;   movn x7, #127
-;   subs wzr, w3, w5
-;   csel x10, x5, x3, gt
-;   subs wzr, w10, w7
-;   csel x0, x7, x10, lt
+;   fcvtzs w2, d0
+;   movz w4, #127
+;   movn x6, #127
+;   subs wzr, w2, w4
+;   csel x9, x4, x2, gt
+;   subs wzr, w9, w6
+;   csel x0, x6, x9, lt
 ;   ret
 
 function %f37(f64) -> i16 {
@@ -491,10 +491,10 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvtzu w3, d0
-;   movz w5, #65535
-;   subs wzr, w3, w5
-;   csel x0, x5, x3, hi
+;   fcvtzu w2, d0
+;   movz w4, #65535
+;   subs wzr, w2, w4
+;   csel x0, x4, x2, hi
 ;   ret
 
 function %f38(f64) -> i16 {
@@ -504,12 +504,12 @@ block0(v0: f64):
 }
 
 ; block0:
-;   fcvtzs w3, d0
-;   movz w5, #32767
-;   movn x7, #32767
-;   subs wzr, w3, w5
-;   csel x10, x5, x3, gt
-;   subs wzr, w10, w7
-;   csel x0, x7, x10, lt
+;   fcvtzs w2, d0
+;   movz w4, #32767
+;   movn x6, #32767
+;   subs wzr, w2, w4
+;   csel x9, x4, x2, gt
+;   subs wzr, w9, w6
+;   csel x0, x6, x9, lt
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/floating-point.clif

@@ -309,8 +309,8 @@ block0(v0: f32, v1: f32):
 }
 
 ; block0:
-;   ushr v5.2s, v1.2s, #31
-;   sli v0.2s, v0.2s, v5.2s, #31
+;   ushr v4.2s, v1.2s, #31
+;   sli v0.2s, v0.2s, v4.2s, #31
 ;   ret
 
 function %f32(f64, f64) -> f64 {
@@ -320,8 +320,8 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   ushr d5, d1, #63
-;   sli d0, d0, d5, #63
+;   ushr d4, d1, #63
+;   sli d0, d0, d4, #63
 ;   ret
 
 function %f33(f32) -> i32 {
@@ -333,12 +333,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
-;   fcmp s0, s5
+;   fmov s4, #-1
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #20352, LSL #16
-;   fmov s18, w10
-;   fcmp s0, s18
+;   movz x9, #20352, LSL #16
+;   fmov s17, w9
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
@@ -352,13 +352,13 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   movz x6, #52992, LSL #16
-;   fmov s6, w6
-;   fcmp s0, s6
+;   movz x5, #52992, LSL #16
+;   fmov s5, w5
+;   fcmp s0, s5
 ;   b.ge 8 ; udf
-;   movz x12, #20224, LSL #16
-;   fmov s20, w12
-;   fcmp s0, s20
+;   movz x11, #20224, LSL #16
+;   fmov s19, w11
+;   fcmp s0, s19
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, s0
 ;   ret
@@ -372,12 +372,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
-;   fcmp s0, s5
+;   fmov s4, #-1
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #24448, LSL #16
-;   fmov s18, w10
-;   fcmp s0, s18
+;   movz x9, #24448, LSL #16
+;   fmov s17, w9
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, s0
 ;   ret
@@ -391,13 +391,13 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   movz x6, #57088, LSL #16
-;   fmov s6, w6
-;   fcmp s0, s6
+;   movz x5, #57088, LSL #16
+;   fmov s5, w5
+;   fcmp s0, s5
 ;   b.ge 8 ; udf
-;   movz x12, #24320, LSL #16
-;   fmov s20, w12
-;   fcmp s0, s20
+;   movz x11, #24320, LSL #16
+;   fmov s19, w11
+;   fcmp s0, s19
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, s0
 ;   ret
@@ -411,12 +411,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
-;   fcmp d0, d5
+;   fmov d4, #-1
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16880, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #16880, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
@@ -430,12 +430,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   ldr d5, pc+8 ; b 12 ; data.f64 -2147483649
-;   fcmp d0, d5
+;   ldr d4, pc+8 ; b 12 ; data.f64 -2147483649
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16864, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #16864, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, d0
 ;   ret
@@ -449,12 +449,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
-;   fcmp d0, d5
+;   fmov d4, #-1
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #17392, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #17392, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, d0
 ;   ret
@@ -468,13 +468,13 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   movz x6, #50144, LSL #48
-;   fmov d6, x6
-;   fcmp d0, d6
+;   movz x5, #50144, LSL #48
+;   fmov d5, x5
+;   fcmp d0, d5
 ;   b.ge 8 ; udf
-;   movz x12, #17376, LSL #48
-;   fmov d20, x12
-;   fcmp d0, d20
+;   movz x11, #17376, LSL #48
+;   fmov d19, x11
+;   fcmp d0, d19
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, d0
 ;   ret
@@ -776,9 +776,9 @@ block0(v0: f32x4, v1: f32x4, v2: f32x4):
 }
 
 ; block0:
-;   mov v5.16b, v2.16b
-;   fmla v5.4s, v5.4s, v0.4s, v1.4s
-;   mov v0.16b, v5.16b
+;   mov v5.16b, v0.16b
+;   mov v0.16b, v2.16b
+;   fmla v0.4s, v0.4s, v5.4s, v1.4s
 ;   ret
 
 function %f71(f32x2, f32x2, f32x2) -> f32x2 {
@@ -788,9 +788,9 @@ block0(v0: f32x2, v1: f32x2, v2: f32x2):
 }
 
 ; block0:
-;   mov v5.16b, v2.16b
-;   fmla v5.2s, v5.2s, v0.2s, v1.2s
-;   mov v0.16b, v5.16b
+;   mov v5.16b, v0.16b
+;   mov v0.16b, v2.16b
+;   fmla v0.2s, v0.2s, v5.2s, v1.2s
 ;   ret
 
 function %f72(f64x2, f64x2, f64x2) -> f64x2 {
@@ -800,9 +800,9 @@ block0(v0: f64x2, v1: f64x2, v2: f64x2):
 }
 
 ; block0:
-;   mov v5.16b, v2.16b
-;   fmla v5.2d, v5.2d, v0.2d, v1.2d
-;   mov v0.16b, v5.16b
+;   mov v5.16b, v0.16b
+;   mov v0.16b, v2.16b
+;   fmla v0.2d, v0.2d, v5.2d, v1.2d
 ;   ret
 
 function %f73(f32x2, f32x2) -> f32x2 {
@@ -812,8 +812,8 @@ block0(v0: f32x2, v1: f32x2):
 }
 
 ; block0:
-;   ushr v5.2s, v1.2s, #31
-;   sli v0.2s, v0.2s, v5.2s, #31
+;   ushr v4.2s, v1.2s, #31
+;   sli v0.2s, v0.2s, v4.2s, #31
 ;   ret
 
 function %f74(f32x4, f32x4) -> f32x4 {
@@ -823,8 +823,8 @@ block0(v0: f32x4, v1: f32x4):
 }
 
 ; block0:
-;   ushr v5.4s, v1.4s, #31
-;   sli v0.4s, v0.4s, v5.4s, #31
+;   ushr v4.4s, v1.4s, #31
+;   sli v0.4s, v0.4s, v4.4s, #31
 ;   ret
 
 function %f75(f64x2, f64x2) -> f64x2 {
@@ -834,6 +834,7 @@ block0(v0: f64x2, v1: f64x2):
 }
 
 ; block0:
-;   ushr v5.2d, v1.2d, #63
-;   sli v0.2d, v0.2d, v5.2d, #63
+;   ushr v4.2d, v1.2d, #63
+;   sli v0.2d, v0.2d, v4.2d, #63
 ;   ret
+

cranelift/filetests/filetests/isa/aarch64/heap_addr.clif

@@ -14,16 +14,16 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   mov w9, w1
-;   ldr x10, [x0]
-;   mov x10, x10
-;   subs xzr, x9, x10
+;   mov w8, w1
+;   ldr x9, [x0]
+;   mov x9, x9
+;   subs xzr, x8, x9
 ;   b.ls label1 ; b label2
 ; block1:
-;   add x11, x0, x1, UXTW
-;   movz x12, #0
-;   subs xzr, x9, x10
-;   csel x0, x12, x11, hi
+;   add x10, x0, x1, UXTW
+;   movz x11, #0
+;   subs xzr, x8, x9
+;   csel x0, x11, x10, hi
 ;   csdb
 ;   ret
 ; block2:
@@ -39,14 +39,14 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   mov w7, w1
-;   subs xzr, x7, #65536
+;   mov w6, w1
+;   subs xzr, x6, #65536
 ;   b.ls label1 ; b label2
 ; block1:
-;   add x9, x0, x1, UXTW
-;   movz x8, #0
-;   subs xzr, x7, #65536
-;   csel x0, x8, x9, hi
+;   add x8, x0, x1, UXTW
+;   movz x7, #0
+;   subs xzr, x6, #65536
+;   csel x0, x7, x8, hi
 ;   csdb
 ;   ret
 ; block2:

cranelift/filetests/filetests/isa/aarch64/i128-bmask.clif

@@ -8,8 +8,8 @@ block0(v0: i128):
 }
 
 ; block0:
-;   orr x5, x0, x1
-;   subs xzr, x5, #0
+;   orr x3, x0, x1
+;   subs xzr, x3, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret
@@ -21,8 +21,8 @@ block0(v0: i128):
 }
 
 ; block0:
-;   orr x4, x0, x1
-;   subs xzr, x4, #0
+;   orr x3, x0, x1
+;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
 
@@ -33,8 +33,8 @@ block0(v0: i128):
 }
 
 ; block0:
-;   orr x4, x0, x1
-;   subs xzr, x4, #0
+;   orr x3, x0, x1
+;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
 
@@ -45,8 +45,8 @@ block0(v0: i128):
 }
 
 ; block0:
-;   orr x4, x0, x1
-;   subs xzr, x4, #0
+;   orr x3, x0, x1
+;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
 
@@ -57,8 +57,8 @@ block0(v0: i128):
 }
 
 ; block0:
-;   orr x4, x0, x1
-;   subs xzr, x4, #0
+;   orr x3, x0, x1
+;   subs xzr, x3, #0
 ;   csetm x0, ne
 ;   ret
 
@@ -93,8 +93,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   and w4, w0, #65535
-;   subs wzr, w4, #0
+;   and w2, w0, #65535
+;   subs wzr, w2, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret
@@ -106,8 +106,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   and w4, w0, #255
-;   subs wzr, w4, #0
+;   and w2, w0, #255
+;   subs wzr, w2, #0
 ;   csetm x1, ne
 ;   mov x0, x1
 ;   ret

cranelift/filetests/filetests/isa/aarch64/iabs.clif

@@ -79,9 +79,9 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sxtb w3, w0
-;   subs wzr, w3, #0
-;   csneg x0, x3, x3, gt
+;   sxtb w2, w0
+;   subs wzr, w2, #0
+;   csneg x0, x2, x2, gt
 ;   ret
 
 function %f9(i16) -> i16 {
@@ -91,9 +91,9 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sxth w3, w0
-;   subs wzr, w3, #0
-;   csneg x0, x3, x3, gt
+;   sxth w2, w0
+;   subs wzr, w2, #0
+;   csneg x0, x2, x2, gt
 ;   ret
 
 function %f10(i32) -> i32 {

cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif

@@ -14,10 +14,10 @@ block0:
 }
 
 ; block0:
-;   movz x1, #56780
-;   uxth w3, w1
-;   movz x5, #56780
-;   subs wzr, w3, w5, UXTH
+;   movz x0, #56780
+;   uxth w2, w0
+;   movz x4, #56780
+;   subs wzr, w2, w4, UXTH
 ;   cset x0, ne
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/jumptable.clif

@@ -32,7 +32,7 @@ block5(v5: i32):
 ; block0:
 ;   emit_island 44
 ;   subs wzr, w0, #3
-;   b.hs label1 ; csel x1, xzr, x0, hs ; csdb ; adr x15, pc+16 ; ldrsw x1, [x15, x1, uxtw #2] ; add x15, x15, x1 ; br x15 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))]
+;   b.hs label1 ; csel x15, xzr, x0, hs ; csdb ; adr x14, pc+16 ; ldrsw x15, [x14, x15, uxtw #2] ; add x14, x14, x15 ; br x14 ; jt_entries [Label(MachLabel(3)), Label(MachLabel(5)), Label(MachLabel(7))]
 ; block1:
 ;   movz x5, #4
 ;   b label2
@@ -56,3 +56,4 @@ block5(v5: i32):
 ; block9:
 ;   add w0, w0, w5
 ;   ret
+

cranelift/filetests/filetests/isa/aarch64/prologue.clif

@@ -82,6 +82,7 @@ block0(v0: f64):
 ;   stp d10, d11, [sp, #-16]!
 ;   stp d8, d9, [sp, #-16]!
 ; block0:
+;   fadd d23, d0, d0
 ;   fadd d24, d0, d0
 ;   fadd d25, d0, d0
 ;   fadd d26, d0, d0
@@ -104,7 +105,7 @@ block0(v0: f64):
 ;   fadd d20, d0, d0
 ;   fadd d21, d0, d0
 ;   fadd d22, d0, d0
-;   fadd d23, d0, d0
+;   fadd d15, d0, d0
 ;   fadd d8, d0, d0
 ;   fadd d9, d0, d0
 ;   fadd d10, d0, d0
@@ -112,38 +113,37 @@ block0(v0: f64):
 ;   fadd d12, d0, d0
 ;   fadd d13, d0, d0
 ;   fadd d14, d0, d0
-;   fadd d15, d0, d0
-;   fadd d24, d0, d24
-;   fadd d25, d25, d26
-;   fadd d26, d27, d28
-;   fadd d27, d29, d30
-;   fadd d28, d31, d1
-;   fadd d29, d2, d3
-;   fadd d30, d4, d5
-;   fadd d31, d6, d7
-;   fadd d0, d16, d17
-;   fadd d1, d18, d19
-;   fadd d2, d20, d21
-;   fadd d3, d22, d23
-;   fadd d4, d8, d9
-;   fadd d5, d10, d11
-;   fadd d6, d12, d13
-;   fadd d7, d14, d15
+;   fadd d23, d0, d23
 ;   fadd d24, d24, d25
 ;   fadd d25, d26, d27
 ;   fadd d26, d28, d29
 ;   fadd d27, d30, d31
-;   fadd d28, d0, d1
-;   fadd d29, d2, d3
-;   fadd d30, d4, d5
-;   fadd d31, d6, d7
-;   fadd d24, d24, d25
-;   fadd d25, d26, d27
-;   fadd d26, d28, d29
-;   fadd d27, d30, d31
-;   fadd d24, d24, d25
-;   fadd d25, d26, d27
-;   fadd d0, d24, d25
+;   fadd d28, d1, d2
+;   fadd d29, d3, d4
+;   fadd d30, d5, d6
+;   fadd d31, d7, d16
+;   fadd d0, d17, d18
+;   fadd d1, d19, d20
+;   fadd d2, d21, d22
+;   fadd d3, d15, d8
+;   fadd d4, d9, d10
+;   fadd d5, d11, d12
+;   fadd d6, d13, d14
+;   fadd d23, d23, d24
+;   fadd d24, d25, d26
+;   fadd d25, d27, d28
+;   fadd d26, d29, d30
+;   fadd d27, d31, d0
+;   fadd d28, d1, d2
+;   fadd d29, d3, d4
+;   fadd d30, d5, d6
+;   fadd d23, d23, d24
+;   fadd d24, d25, d26
+;   fadd d25, d27, d28
+;   fadd d26, d29, d30
+;   fadd d23, d23, d24
+;   fadd d24, d25, d26
+;   fadd d0, d23, d24
 ;   ldp d8, d9, [sp], #16
 ;   ldp d10, d11, [sp], #16
 ;   ldp d12, d13, [sp], #16
@@ -200,9 +200,10 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ;   str x28, [sp, #-16]!
-;   stp x19, x21, [sp, #-16]!
+;   stp x21, x27, [sp, #-16]!
 ; block0:
-;   add x6, x0, x0
+;   add x5, x0, x0
+;   add x6, x0, x5
 ;   add x7, x0, x6
 ;   add x8, x0, x7
 ;   add x9, x0, x8
@@ -216,29 +217,29 @@ block0(v0: i64):
 ;   add x2, x0, x1
 ;   add x3, x0, x2
 ;   add x4, x0, x3
-;   add x5, x0, x4
-;   add x28, x0, x5
+;   add x27, x0, x4
+;   add x28, x0, x27
 ;   add x21, x0, x28
-;   add x19, x0, x21
-;   add x6, x0, x6
-;   add x7, x7, x8
-;   add x8, x9, x10
-;   add x9, x11, x12
-;   add x10, x13, x14
-;   add x11, x15, x1
-;   add x12, x2, x3
-;   add x13, x4, x5
-;   add x14, x28, x21
-;   add x6, x19, x6
-;   add x7, x7, x8
-;   add x8, x9, x10
-;   add x9, x11, x12
-;   add x10, x13, x14
+;   add x5, x0, x5
 ;   add x6, x6, x7
 ;   add x7, x8, x9
-;   add x6, x10, x6
-;   add x0, x7, x6
-;   ldp x19, x21, [sp], #16
+;   add x8, x10, x11
+;   add x9, x12, x13
+;   add x10, x14, x15
+;   add x11, x1, x2
+;   add x12, x3, x4
+;   add x13, x27, x28
+;   add x5, x21, x5
+;   add x6, x6, x7
+;   add x7, x8, x9
+;   add x8, x10, x11
+;   add x9, x12, x13
+;   add x5, x5, x6
+;   add x6, x7, x8
+;   add x5, x9, x5
+;   add x0, x6, x5
+;   ldp x21, x27, [sp], #16
 ;   ldr x28, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
+

cranelift/filetests/filetests/isa/aarch64/reftypes.clif

@@ -69,28 +69,28 @@ block3(v7: r64, v8: r64):
 ; block0:
 ;   str x0, [sp, #8]
 ;   str x1, [sp, #16]
-;   ldr x3, 8 ; b 12 ; data TestCase(%f) + 0
-;   blr x3
-;   mov x2, sp
-;   ldr x9, [sp, #8]
-;   str x9, [x2]
-;   uxtb w3, w0
-;   cbz x3, label1 ; b label3
+;   ldr x1, 8 ; b 12 ; data TestCase(%f) + 0
+;   blr x1
+;   mov x15, sp
+;   ldr x6, [sp, #8]
+;   str x6, [x15]
+;   uxtb w0, w0
+;   cbz x0, label1 ; b label3
 ; block1:
 ;   b label2
 ; block2:
-;   mov x1, x9
+;   mov x1, x6
 ;   ldr x0, [sp, #16]
 ;   b label5
 ; block3:
 ;   b label4
 ; block4:
-;   mov x0, x9
+;   mov x0, x6
 ;   ldr x1, [sp, #16]
 ;   b label5
 ; block5:
-;   mov x4, sp
-;   ldr x2, [x4]
+;   mov x2, sp
+;   ldr x2, [x2]
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret

cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif

@@ -13,28 +13,28 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   orr x7, xzr, #128
-;   sub x9, x7, x2
-;   lsr x11, x0, x2
-;   lsr x13, x1, x2
-;   orn w15, wzr, w2
-;   lsl x3, x1, #1
-;   lsl x3, x3, x15
-;   orr x5, x11, x3
+;   orr x5, xzr, #128
+;   sub x7, x5, x2
+;   lsr x9, x0, x2
+;   lsr x11, x1, x2
+;   orn w13, wzr, w2
+;   lsl x15, x1, #1
+;   lsl x3, x15, x13
+;   orr x3, x9, x3
 ;   ands xzr, x2, #64
-;   csel x8, x13, x5, ne
-;   csel x10, xzr, x13, ne
-;   lsl x12, x0, x9
-;   lsl x14, x1, x9
-;   orn w1, wzr, w9
-;   lsr x2, x0, #1
-;   lsr x4, x2, x1
-;   orr x6, x14, x4
-;   ands xzr, x9, #64
-;   csel x9, xzr, x12, ne
-;   csel x11, x12, x6, ne
-;   orr x1, x10, x11
-;   orr x0, x8, x9
+;   csel x6, x11, x3, ne
+;   csel x8, xzr, x11, ne
+;   lsl x10, x0, x7
+;   lsl x12, x1, x7
+;   orn w14, wzr, w7
+;   lsr x0, x0, #1
+;   lsr x2, x0, x14
+;   orr x4, x12, x2
+;   ands xzr, x7, #64
+;   csel x7, xzr, x10, ne
+;   csel x9, x10, x4, ne
+;   orr x1, x8, x9
+;   orr x0, x6, x7
 ;   ret
 
 function %f0(i64, i64) -> i64 {
@@ -64,13 +64,13 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   uxth w4, w0
-;   and w6, w1, #15
-;   sub w8, w6, #16
-;   sub w10, wzr, w8
-;   lsr w12, w4, w6
-;   lsl w14, w4, w10
-;   orr w0, w14, w12
+;   uxth w3, w0
+;   and w5, w1, #15
+;   sub w7, w5, #16
+;   sub w9, wzr, w7
+;   lsr w11, w3, w5
+;   lsl w13, w3, w9
+;   orr w0, w13, w11
 ;   ret
 
 function %f3(i8, i8) -> i8 {
@@ -80,13 +80,13 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   uxtb w4, w0
-;   and w6, w1, #7
-;   sub w8, w6, #8
-;   sub w10, wzr, w8
-;   lsr w12, w4, w6
-;   lsl w14, w4, w10
-;   orr w0, w14, w12
+;   uxtb w3, w0
+;   and w5, w1, #7
+;   sub w7, w5, #8
+;   sub w9, wzr, w7
+;   lsr w11, w3, w5
+;   lsl w13, w3, w9
+;   orr w0, w13, w11
 ;   ret
 
 function %i128_rotl(i128, i128) -> i128 {
@@ -96,28 +96,28 @@ block0(v0: i128, v1: i128):
 }
 
 ; block0:
-;   orr x7, xzr, #128
-;   sub x9, x7, x2
-;   lsl x11, x0, x2
-;   lsl x13, x1, x2
-;   orn w15, wzr, w2
-;   lsr x3, x0, #1
-;   lsr x3, x3, x15
-;   orr x5, x13, x3
+;   orr x5, xzr, #128
+;   sub x7, x5, x2
+;   lsl x9, x0, x2
+;   lsl x11, x1, x2
+;   orn w13, wzr, w2
+;   lsr x15, x0, #1
+;   lsr x3, x15, x13
+;   orr x3, x11, x3
 ;   ands xzr, x2, #64
-;   csel x8, xzr, x11, ne
-;   csel x10, x11, x5, ne
-;   lsr x12, x0, x9
-;   lsr x14, x1, x9
-;   orn w0, wzr, w9
-;   lsl x2, x1, #1
-;   lsl x4, x2, x0
-;   orr x6, x12, x4
-;   ands xzr, x9, #64
-;   csel x9, x14, x6, ne
-;   csel x11, xzr, x14, ne
-;   orr x0, x8, x9
-;   orr x1, x10, x11
+;   csel x6, xzr, x9, ne
+;   csel x8, x9, x3, ne
+;   lsr x10, x0, x7
+;   lsr x12, x1, x7
+;   orn w14, wzr, w7
+;   lsl x0, x1, #1
+;   lsl x2, x0, x14
+;   orr x4, x10, x2
+;   ands xzr, x7, #64
+;   csel x7, x12, x4, ne
+;   csel x9, xzr, x12, ne
+;   orr x0, x6, x7
+;   orr x1, x8, x9
 ;   ret
 
 function %f4(i64, i64) -> i64 {
@@ -127,8 +127,8 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   sub x4, xzr, x1
-;   ror x0, x0, x4
+;   sub x3, xzr, x1
+;   ror x0, x0, x3
 ;   ret
 
 function %f5(i32, i32) -> i32 {
@@ -138,8 +138,8 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sub w4, wzr, w1
-;   ror w0, w0, w4
+;   sub w3, wzr, w1
+;   ror w0, w0, w3
 ;   ret
 
 function %f6(i16, i16) -> i16 {
@@ -149,14 +149,14 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   sub w4, wzr, w1
-;   uxth w6, w0
-;   and w8, w4, #15
-;   sub w10, w8, #16
-;   sub w12, wzr, w10
-;   lsr w14, w6, w8
-;   lsl w0, w6, w12
-;   orr w0, w0, w14
+;   sub w3, wzr, w1
+;   uxth w5, w0
+;   and w7, w3, #15
+;   sub w9, w7, #16
+;   sub w11, wzr, w9
+;   lsr w13, w5, w7
+;   lsl w15, w5, w11
+;   orr w0, w15, w13
 ;   ret
 
 function %f7(i8, i8) -> i8 {
@@ -166,14 +166,14 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   sub w4, wzr, w1
-;   uxtb w6, w0
-;   and w8, w4, #7
-;   sub w10, w8, #8
-;   sub w12, wzr, w10
-;   lsr w14, w6, w8
-;   lsl w0, w6, w12
-;   orr w0, w0, w14
+;   sub w3, wzr, w1
+;   uxtb w5, w0
+;   and w7, w3, #7
+;   sub w9, w7, #8
+;   sub w11, wzr, w9
+;   lsr w13, w5, w7
+;   lsl w15, w5, w11
+;   orr w0, w15, w13
 ;   ret
 
 function %f8(i64, i64) -> i64 {
@@ -203,9 +203,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   uxth w4, w0
-;   and w6, w1, #15
-;   lsr w0, w4, w6
+;   uxth w3, w0
+;   and w5, w1, #15
+;   lsr w0, w3, w5
 ;   ret
 
 function %f11(i8, i8) -> i8 {
@@ -215,9 +215,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   uxtb w4, w0
-;   and w6, w1, #7
-;   lsr w0, w4, w6
+;   uxtb w3, w0
+;   and w5, w1, #7
+;   lsr w0, w3, w5
 ;   ret
 
 function %f12(i64, i64) -> i64 {
@@ -247,8 +247,8 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   and w4, w1, #15
-;   lsl w0, w0, w4
+;   and w3, w1, #15
+;   lsl w0, w0, w3
 ;   ret
 
 function %f15(i8, i8) -> i8 {
@@ -258,8 +258,8 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   and w4, w1, #7
-;   lsl w0, w0, w4
+;   and w3, w1, #7
+;   lsl w0, w0, w3
 ;   ret
 
 function %f16(i64, i64) -> i64 {
@@ -289,9 +289,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; block0:
-;   sxth w4, w0
-;   and w6, w1, #15
-;   asr w0, w4, w6
+;   sxth w3, w0
+;   and w5, w1, #15
+;   asr w0, w3, w5
 ;   ret
 
 function %f19(i8, i8) -> i8 {
@@ -301,9 +301,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; block0:
-;   sxtb w4, w0
-;   and w6, w1, #7
-;   asr w0, w4, w6
+;   sxtb w3, w0
+;   and w5, w1, #7
+;   asr w0, w3, w5
 ;   ret
 
 function %f20(i64) -> i64 {
@@ -347,10 +347,10 @@ block0(v0: i16):
 }
 
 ; block0:
-;   uxth w3, w0
-;   lsr w5, w3, #6
-;   lsl w7, w3, #10
-;   orr w0, w7, w5
+;   uxth w2, w0
+;   lsr w4, w2, #6
+;   lsl w6, w2, #10
+;   orr w0, w6, w4
 ;   ret
 
 function %f24(i8) -> i8 {
@@ -361,10 +361,10 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w3, w0
-;   lsr w5, w3, #5
-;   lsl w7, w3, #3
-;   orr w0, w7, w5
+;   uxtb w2, w0
+;   lsr w4, w2, #5
+;   lsl w6, w2, #3
+;   orr w0, w6, w4
 ;   ret
 
 function %f25(i64) -> i64 {

cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif

@@ -69,13 +69,13 @@ block0(v0: i64x2, v1: i64x2):
 }
 
 ; block0:
-;   movz x5, #1
-;   dup v5.2d, x5
-;   orr v16.16b, v0.16b, v1.16b
-;   and v18.16b, v16.16b, v5.16b
-;   ushr v20.2d, v0.2d, #1
-;   ushr v22.2d, v1.2d, #1
-;   add v24.2d, v20.2d, v22.2d
-;   add v0.2d, v18.2d, v24.2d
+;   movz x4, #1
+;   dup v4.2d, x4
+;   orr v7.16b, v0.16b, v1.16b
+;   and v17.16b, v7.16b, v4.16b
+;   ushr v19.2d, v0.2d, #1
+;   ushr v21.2d, v1.2d, #1
+;   add v23.2d, v19.2d, v21.2d
+;   add v0.2d, v17.2d, v23.2d
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif

@@ -103,9 +103,9 @@ block0:
 
 ; block0:
 ;   movi v0.16b, #0
+;   movi v3.16b, #0
 ;   movi v4.16b, #0
-;   movi v5.16b, #0
-;   bsl v0.16b, v0.16b, v4.16b, v5.16b
+;   bsl v0.16b, v0.16b, v3.16b, v4.16b
 ;   ret
 
 function %vselect_i16x8(i16x8, i16x8, i16x8) -> i16x8 {
@@ -146,10 +146,10 @@ block0(v0: i32):
 }
 
 ; block0:
-;   ldr q6, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
-;   and w4, w0, #7
-;   dup v7.16b, w4
-;   sshl v0.16b, v6.16b, v7.16b
+;   ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
+;   and w3, w0, #7
+;   dup v6.16b, w3
+;   sshl v0.16b, v5.16b, v6.16b
 ;   ret
 
 function %ushr_i8x16_imm() -> i8x16 {
@@ -161,12 +161,12 @@ block0:
 }
 
 ; block0:
-;   ldr q6, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
-;   movz x2, #1
-;   and w4, w2, #7
-;   sub x6, xzr, x4
-;   dup v16.16b, w6
-;   ushl v0.16b, v6.16b, v16.16b
+;   ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
+;   movz x1, #1
+;   and w3, w1, #7
+;   sub x5, xzr, x3
+;   dup v7.16b, w5
+;   ushl v0.16b, v5.16b, v7.16b
 ;   ret
 
 function %sshr_i8x16(i32) -> i8x16 {
@@ -177,11 +177,11 @@ block0(v0: i32):
 }
 
 ; block0:
-;   ldr q7, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
-;   and w4, w0, #7
-;   sub x6, xzr, x4
-;   dup v16.16b, w6
-;   sshl v0.16b, v7.16b, v16.16b
+;   ldr q6, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
+;   and w3, w0, #7
+;   sub x5, xzr, x3
+;   dup v7.16b, w5
+;   sshl v0.16b, v6.16b, v7.16b
 ;   ret
 
 function %sshr_i8x16_imm(i8x16, i32) -> i8x16 {
@@ -191,11 +191,11 @@ block0(v0: i8x16, v1: i32):
 }
 
 ; block0:
-;   movz x4, #3
-;   and w6, w4, #7
-;   sub x8, xzr, x6
-;   dup v18.16b, w8
-;   sshl v0.16b, v0.16b, v18.16b
+;   movz x3, #3
+;   and w5, w3, #7
+;   sub x7, xzr, x5
+;   dup v17.16b, w7
+;   sshl v0.16b, v0.16b, v17.16b
 ;   ret
 
 function %sshr_i64x2(i64x2, i32) -> i64x2 {
@@ -205,9 +205,9 @@ block0(v0: i64x2, v1: i32):
 }
 
 ; block0:
-;   and w4, w0, #63
-;   sub x6, xzr, x4
-;   dup v16.2d, x6
-;   sshl v0.2d, v0.2d, v16.2d
+;   and w3, w0, #63
+;   sub x5, xzr, x3
+;   dup v7.2d, x5
+;   sshl v0.2d, v0.2d, v7.2d
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif

@@ -9,8 +9,8 @@ block0(v0: i32x4, v1: i32x4):
 }
 
 ; block0:
-;   cmeq v4.4s, v0.4s, v1.4s
-;   mvn v0.16b, v4.16b
+;   cmeq v3.4s, v0.4s, v1.4s
+;   mvn v0.16b, v3.16b
 ;   ret
 
 function %icmp_ugt_i32x4(i32x4, i32x4) -> i32x4 {

cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif

@@ -14,10 +14,10 @@ block0:
 
 ; block0:
 ;   movi v30.16b, #0
-;   movz x5, #1
-;   fmov s31, w5
-;   ldr q4, pc+8 ; b 20 ; data.f128 0x11000000000000000000000000000000
-;   tbl v0.16b, { v30.16b, v31.16b }, v4.16b
+;   movz x4, #1
+;   fmov s31, w4
+;   ldr q3, pc+8 ; b 20 ; data.f128 0x11000000000000000000000000000000
+;   tbl v0.16b, { v30.16b, v31.16b }, v3.16b
 ;   ret
 
 function %shuffle_same_ssa_value() -> i8x16 {
@@ -28,11 +28,11 @@ block0:
 }
 
 ; block0:
-;   movz x4, #1
-;   fmov s31, w4
-;   ldr q3, pc+8 ; b 20 ; data.f128 0x13000000000000000000000000000000
+;   movz x3, #1
+;   fmov s31, w3
+;   ldr q2, pc+8 ; b 20 ; data.f128 0x13000000000000000000000000000000
 ;   mov v30.16b, v31.16b
-;   tbl v0.16b, { v30.16b, v31.16b }, v3.16b
+;   tbl v0.16b, { v30.16b, v31.16b }, v2.16b
 ;   ret
 
 function %swizzle() -> i8x16 {
@@ -44,9 +44,9 @@ block0:
 }
 
 ; block0:
+;   ldr q2, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
 ;   ldr q3, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
-;   ldr q4, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100
-;   tbl v0.16b, { v3.16b }, v4.16b
+;   tbl v0.16b, { v2.16b }, v3.16b
 ;   ret
 
 function %splat_i8(i8) -> i8x16 {
@@ -98,8 +98,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldr w4, [x0]
-;   fmov s0, w4
+;   ldr w3, [x0]
+;   fmov s0, w3
 ;   ret
 
 function %load32_zero_int(i32) -> i32x4 {

cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif

@@ -19,9 +19,9 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   umaxp v3.4s, v0.4s, v0.4s
-;   mov x5, v3.d[0]
-;   subs xzr, x5, #0
+;   umaxp v2.4s, v0.4s, v0.4s
+;   mov x4, v2.d[0]
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -32,9 +32,9 @@ block0(v0: i64x2):
 }
 
 ; block0:
-;   cmeq v3.2d, v0.2d, #0
-;   addp v5.2d, v3.2d, v3.2d
-;   fcmp d5, d5
+;   cmeq v2.2d, v0.2d, #0
+;   addp v4.2d, v2.2d, v2.2d
+;   fcmp d4, d4
 ;   cset x0, eq
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/simd-narrow.clif

@@ -9,9 +9,9 @@ block0(v0: i16x4, v1: i16x4):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
-;   sqxtn v0.8b, v4.8h
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v3.d[1], v1.d[0]
+;   sqxtn v0.8b, v3.8h
 ;   ret
 
 function %snarrow_i16x8(i16x8, i16x8) -> i8x16 {
@@ -32,9 +32,9 @@ block0(v0: i32x2, v1: i32x2):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
-;   sqxtn v0.4h, v4.4s
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v3.d[1], v1.d[0]
+;   sqxtn v0.4h, v3.4s
 ;   ret
 
 function %snarrow_i32x4(i32x4, i32x4) -> i16x8 {
@@ -66,9 +66,9 @@ block0(v0: i16x4, v1: i16x4):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
-;   sqxtun v0.8b, v4.8h
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v3.d[1], v1.d[0]
+;   sqxtun v0.8b, v3.8h
 ;   ret
 
 function %unarrow_i16x8(i16x8, i16x8) -> i8x16 {
@@ -89,9 +89,9 @@ block0(v0: i32x2, v1: i32x2):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
-;   sqxtun v0.4h, v4.4s
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v3.d[1], v1.d[0]
+;   sqxtun v0.4h, v3.4s
 ;   ret
 
 function %unarrow_i32x4(i32x4, i32x4) -> i16x8 {
@@ -123,9 +123,9 @@ block0(v0: i16x4, v1: i16x4):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
-;   uqxtn v0.8b, v4.8h
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v3.d[1], v1.d[0]
+;   uqxtn v0.8b, v3.8h
 ;   ret
 
 function %uunarrow_i16x8(i16x8, i16x8) -> i8x16 {
@@ -146,9 +146,9 @@ block0(v0: i32x2, v1: i32x2):
 }
 
 ; block0:
-;   mov v4.16b, v0.16b
-;   mov v4.d[1], v4.d[1], v1.d[0]
-;   uqxtn v0.4h, v4.4s
+;   mov v3.16b, v0.16b
+;   mov v3.d[1], v3.d[1], v1.d[0]
+;   uqxtn v0.4h, v3.4s
 ;   ret
 
 function %uunarrow_i32x4(i32x4, i32x4) -> i16x8 {

cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif

@@ -9,9 +9,9 @@ block0(v0: i8x8):
 }
 
 ; block0:
-;   uminv b3, v0.8b
-;   mov x5, v3.d[0]
-;   subs xzr, x5, #0
+;   uminv b2, v0.8b
+;   mov x4, v2.d[0]
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -22,9 +22,9 @@ block0(v0: i8x16):
 }
 
 ; block0:
-;   uminv b3, v0.16b
-;   mov x5, v3.d[0]
-;   subs xzr, x5, #0
+;   uminv b2, v0.16b
+;   mov x4, v2.d[0]
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -35,9 +35,9 @@ block0(v0: i16x4):
 }
 
 ; block0:
-;   uminv h3, v0.4h
-;   mov x5, v3.d[0]
-;   subs xzr, x5, #0
+;   uminv h2, v0.4h
+;   mov x4, v2.d[0]
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -48,9 +48,9 @@ block0(v0: i16x8):
 }
 
 ; block0:
-;   uminv h3, v0.8h
-;   mov x5, v3.d[0]
-;   subs xzr, x5, #0
+;   uminv h2, v0.8h
+;   mov x4, v2.d[0]
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -61,9 +61,9 @@ block0(v0: i32x2):
 }
 
 ; block0:
-;   mov x3, v0.d[0]
-;   subs xzr, xzr, x3, LSR 32
-;   ccmp w3, #0, #nZcv, ne
+;   mov x2, v0.d[0]
+;   subs xzr, xzr, x2, LSR 32
+;   ccmp w2, #0, #nZcv, ne
 ;   cset x0, ne
 ;   ret
 
@@ -74,9 +74,9 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   uminv s3, v0.4s
-;   mov x5, v3.d[0]
-;   subs xzr, x5, #0
+;   uminv s2, v0.4s
+;   mov x4, v2.d[0]
+;   subs xzr, x4, #0
 ;   cset x0, ne
 ;   ret
 
@@ -87,9 +87,9 @@ block0(v0: i64x2):
 }
 
 ; block0:
-;   cmeq v3.2d, v0.2d, #0
-;   addp v5.2d, v3.2d, v3.2d
-;   fcmp d5, d5
+;   cmeq v2.2d, v0.2d, #0
+;   addp v4.2d, v2.2d, v2.2d
+;   fcmp d4, d4
 ;   cset x0, eq
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/simd.clif

@@ -10,9 +10,9 @@ block0:
 }
 
 ; block0:
-;   movz x2, #1
-;   movk x2, x2, #1, LSL #48
-;   dup v0.2d, x2
+;   movz x1, #1
+;   movk x1, x1, #1, LSL #48
+;   dup v0.2d, x1
 ;   ret
 
 function %f2() -> i16x8 {
@@ -24,8 +24,8 @@ block0:
 }
 
 ; block0:
-;   movz x2, #42679
-;   dup v0.8h, w2
+;   movz x1, #42679
+;   dup v0.8h, w1
 ;   ret
 
 function %f4(i32, i8x16, i8x16) -> i8x16 {
@@ -74,9 +74,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   ldrb w7, [x0]
+;   ldrb w5, [x0]
 ;   ld1r { v0.16b }, [x1]
-;   dup v1.16b, w7
+;   dup v1.16b, w5
 ;   ret
 
 function %f8(i64, i64) -> i8x16, i8x16 {
@@ -88,9 +88,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   ldrb w7, [x0]
-;   dup v0.16b, w7
-;   dup v1.16b, w7
+;   ldrb w5, [x0]
+;   dup v0.16b, w5
+;   dup v1.16b, w5
 ;   ret
 
 function %f9() -> i32x2 {

cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif

@@ -10,9 +10,9 @@ block0:
 }
 
 ; block0:
-;   movz x1, #1
-;   movk x1, x1, #1, LSL #48
-;   fmov d0, x1
+;   movz x0, #1
+;   movk x0, x0, #1, LSL #48
+;   fmov d0, x0
 ;   ret
 
 function %f2() -> i32x4 {
@@ -23,8 +23,8 @@ block0:
 }
 
 ; block0:
-;   movz x1, #42679
-;   fmov s0, w1
+;   movz x0, #42679
+;   fmov s0, w0
 ;   ret
 
 function %f3() -> f32x4 {
@@ -35,8 +35,8 @@ block0:
 }
 
 ; block0:
-;   fmov s1, #1
-;   fmov s0, s1
+;   fmov s0, #1
+;   fmov s0, s0
 ;   ret
 
 function %f4() -> f64x2 {
@@ -47,7 +47,7 @@ block0:
 }
 
 ; block0:
-;   fmov d1, #1
-;   fmov d0, d1
+;   fmov d0, #1
+;   fmov d0, d0
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/stack.clif

@@ -53,8 +53,8 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #16
 ; block0:
-;   mov x2, sp
-;   ldr x0, [x2]
+;   mov x1, sp
+;   ldr x0, [x1]
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -74,8 +74,8 @@ block0:
 ;   movk w16, w16, #1, LSL #16
 ;   sub sp, sp, x16, UXTX
 ; block0:
-;   mov x2, sp
-;   ldr x0, [x2]
+;   mov x1, sp
+;   ldr x0, [x1]
 ;   movz w16, #34480
 ;   movk w16, w16, #1, LSL #16
 ;   add sp, sp, x16, UXTX
@@ -284,142 +284,142 @@ block0(v0: i8):
 ;   sub sp, sp, #1152
 ; block0:
 ;   str x0, [sp, #1000]
-;   movz x8, #2
-;   add x11, x8, #1
-;   str x11, [sp, #1136]
-;   movz x8, #4
-;   add x12, x8, #3
-;   str x12, [sp, #1128]
-;   movz x8, #6
-;   add x13, x8, #5
-;   str x13, [sp, #1120]
-;   movz x8, #8
-;   add x14, x8, #7
-;   str x14, [sp, #1112]
-;   movz x8, #10
-;   add x15, x8, #9
-;   str x15, [sp, #1104]
-;   movz x8, #12
-;   add x1, x8, #11
-;   str x1, [sp, #1096]
-;   movz x8, #14
-;   add x2, x8, #13
-;   str x2, [sp, #1088]
-;   movz x8, #16
-;   add x3, x8, #15
-;   str x3, [sp, #1080]
-;   movz x8, #18
-;   add x4, x8, #17
-;   str x4, [sp, #1072]
-;   movz x8, #20
-;   add x5, x8, #19
-;   str x5, [sp, #1064]
-;   movz x8, #22
-;   add x6, x8, #21
-;   str x6, [sp, #1056]
-;   movz x8, #24
-;   add x7, x8, #23
-;   str x7, [sp, #1048]
-;   movz x8, #26
-;   add x8, x8, #25
-;   str x8, [sp, #1040]
-;   movz x8, #28
-;   add x9, x8, #27
-;   str x9, [sp, #1032]
-;   movz x8, #30
-;   add x26, x8, #29
-;   str x26, [sp, #1024]
-;   movz x8, #32
-;   add x27, x8, #31
-;   str x27, [sp, #1016]
-;   movz x8, #34
-;   add x28, x8, #33
-;   movz x8, #36
-;   add x21, x8, #35
-;   str x21, [sp, #1008]
-;   movz x8, #38
-;   add x21, x8, #37
-;   movz x8, #30
-;   add x19, x8, #39
-;   movz x8, #32
-;   add x20, x8, #31
-;   movz x8, #34
-;   add x22, x8, #33
-;   movz x8, #36
-;   add x23, x8, #35
-;   movz x8, #38
-;   add x24, x8, #37
-;   movz x8, #30
-;   add x25, x8, #39
-;   movz x8, #32
-;   add x0, x8, #31
-;   movz x8, #34
-;   add x10, x8, #33
-;   movz x8, #36
-;   add x11, x8, #35
-;   movz x8, #38
-;   add x12, x8, #37
-;   movz x8, #30
-;   add x13, x8, #39
-;   movz x8, #32
-;   add x14, x8, #31
-;   movz x8, #34
-;   add x15, x8, #33
-;   movz x8, #36
-;   add x1, x8, #35
-;   movz x8, #38
-;   add x2, x8, #37
-;   ldr x3, [sp, #1136]
-;   add x3, x3, #39
-;   ldr x5, [sp, #1120]
-;   ldr x4, [sp, #1128]
-;   add x4, x4, x5
-;   ldr x5, [sp, #1104]
-;   ldr x8, [sp, #1112]
-;   add x5, x8, x5
-;   ldr x6, [sp, #1088]
-;   ldr x7, [sp, #1096]
-;   add x6, x7, x6
-;   ldr x7, [sp, #1072]
-;   ldr x8, [sp, #1080]
-;   add x7, x8, x7
-;   ldr x9, [sp, #1056]
-;   ldr x8, [sp, #1064]
+;   movz x6, #2
+;   add x9, x6, #1
+;   str x9, [sp, #1136]
+;   movz x6, #4
+;   add x10, x6, #3
+;   str x10, [sp, #1128]
+;   movz x6, #6
+;   add x11, x6, #5
+;   str x11, [sp, #1120]
+;   movz x6, #8
+;   add x12, x6, #7
+;   str x12, [sp, #1112]
+;   movz x6, #10
+;   add x13, x6, #9
+;   str x13, [sp, #1104]
+;   movz x6, #12
+;   add x14, x6, #11
+;   str x14, [sp, #1096]
+;   movz x6, #14
+;   add x15, x6, #13
+;   str x15, [sp, #1088]
+;   movz x6, #16
+;   add x1, x6, #15
+;   str x1, [sp, #1080]
+;   movz x6, #18
+;   add x2, x6, #17
+;   str x2, [sp, #1072]
+;   movz x6, #20
+;   add x3, x6, #19
+;   str x3, [sp, #1064]
+;   movz x6, #22
+;   add x4, x6, #21
+;   str x4, [sp, #1056]
+;   movz x6, #24
+;   add x5, x6, #23
+;   str x5, [sp, #1048]
+;   movz x6, #26
+;   add x6, x6, #25
+;   str x6, [sp, #1040]
+;   movz x6, #28
+;   add x7, x6, #27
+;   str x7, [sp, #1032]
+;   movz x6, #30
+;   add x24, x6, #29
+;   str x24, [sp, #1024]
+;   movz x6, #32
+;   add x25, x6, #31
+;   str x25, [sp, #1016]
+;   movz x6, #34
+;   add x26, x6, #33
+;   movz x6, #36
+;   add x27, x6, #35
+;   str x27, [sp, #1008]
+;   movz x6, #38
+;   add x27, x6, #37
+;   movz x6, #30
+;   add x28, x6, #39
+;   movz x6, #32
+;   add x21, x6, #31
+;   movz x6, #34
+;   add x19, x6, #33
+;   movz x6, #36
+;   add x20, x6, #35
+;   movz x6, #38
+;   add x22, x6, #37
+;   movz x6, #30
+;   add x23, x6, #39
+;   movz x6, #32
+;   add x0, x6, #31
+;   movz x6, #34
+;   add x8, x6, #33
+;   movz x6, #36
+;   add x9, x6, #35
+;   movz x6, #38
+;   add x10, x6, #37
+;   movz x6, #30
+;   add x11, x6, #39
+;   movz x6, #32
+;   add x12, x6, #31
+;   movz x6, #34
+;   add x13, x6, #33
+;   movz x6, #36
+;   add x14, x6, #35
+;   movz x6, #38
+;   add x15, x6, #37
+;   ldr x1, [sp, #1136]
+;   add x1, x1, #39
+;   ldr x3, [sp, #1120]
+;   ldr x2, [sp, #1128]
+;   add x2, x2, x3
+;   ldr x3, [sp, #1104]
+;   ldr x6, [sp, #1112]
+;   add x3, x6, x3
+;   ldr x4, [sp, #1088]
+;   ldr x5, [sp, #1096]
+;   add x4, x5, x4
+;   ldr x5, [sp, #1072]
+;   ldr x6, [sp, #1080]
+;   add x5, x6, x5
+;   ldr x7, [sp, #1056]
+;   ldr x6, [sp, #1064]
+;   add x6, x6, x7
+;   ldr x7, [sp, #1040]
+;   ldr x24, [sp, #1048]
+;   add x7, x24, x7
+;   ldr x24, [sp, #1024]
+;   ldr x25, [sp, #1032]
+;   add x24, x25, x24
+;   ldr x25, [sp, #1016]
+;   add x25, x25, x26
+;   ldr x26, [sp, #1008]
+;   add x26, x26, x27
+;   add x27, x28, x21
+;   add x28, x19, x20
+;   add x23, x22, x23
+;   add x8, x0, x8
+;   add x9, x9, x10
+;   add x10, x11, x12
+;   add x11, x13, x14
+;   add x12, x15, x1
+;   add x13, x2, x3
+;   add x14, x4, x5
+;   add x7, x6, x7
+;   add x15, x24, x25
+;   add x0, x26, x27
+;   add x1, x28, x23
 ;   add x8, x8, x9
-;   ldr x9, [sp, #1040]
-;   ldr x26, [sp, #1048]
-;   add x9, x26, x9
-;   ldr x26, [sp, #1024]
-;   ldr x27, [sp, #1032]
-;   add x26, x27, x26
-;   ldr x27, [sp, #1016]
-;   add x27, x27, x28
-;   ldr x28, [sp, #1008]
-;   add x28, x28, x21
-;   add x21, x19, x20
-;   add x19, x22, x23
-;   add x25, x24, x25
-;   add x10, x0, x10
-;   add x11, x11, x12
-;   add x12, x13, x14
-;   add x13, x15, x1
-;   add x14, x2, x3
-;   add x15, x4, x5
-;   add x0, x6, x7
-;   add x9, x8, x9
-;   add x1, x26, x27
-;   add x2, x28, x21
-;   add x3, x19, x25
-;   add x10, x10, x11
-;   add x11, x12, x13
-;   add x12, x14, x15
-;   add x9, x0, x9
-;   add x13, x1, x2
-;   add x10, x3, x10
-;   add x11, x11, x12
-;   add x9, x9, x13
-;   add x10, x10, x11
-;   add x1, x9, x10
+;   add x9, x10, x11
+;   add x10, x12, x13
+;   add x7, x14, x7
+;   add x11, x15, x0
+;   add x8, x1, x8
+;   add x9, x9, x10
+;   add x7, x7, x11
+;   add x8, x8, x9
+;   add x1, x7, x8
 ;   ldr x0, [sp, #1000]
 ;   add sp, sp, #1152
 ;   ldp x19, x20, [sp], #16
@@ -502,8 +502,8 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #16
 ; block0:
-;   mov x5, sp
-;   ldp x0, x1, [x5]
+;   mov x3, sp
+;   ldp x0, x1, [x3]
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -521,8 +521,8 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #32
 ; block0:
-;   add x5, sp, #32
-;   ldp x0, x1, [x5]
+;   add x3, sp, #32
+;   ldp x0, x1, [x3]
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -542,8 +542,8 @@ block0:
 ;   movk w16, w16, #1, LSL #16
 ;   sub sp, sp, x16, UXTX
 ; block0:
-;   mov x5, sp
-;   ldp x0, x1, [x5]
+;   mov x3, sp
+;   ldp x0, x1, [x3]
 ;   movz w16, #34480
 ;   movk w16, w16, #1, LSL #16
 ;   add sp, sp, x16, UXTX

cranelift/filetests/filetests/isa/aarch64/tls-elf-gd.clif

@@ -12,22 +12,21 @@ block0(v0: i32):
 
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
-;   str x25, [sp, #-16]!
+;   str x24, [sp, #-16]!
 ;   stp d14, d15, [sp, #-16]!
 ;   stp d12, d13, [sp, #-16]!
 ;   stp d10, d11, [sp, #-16]!
 ;   stp d8, d9, [sp, #-16]!
 ; block0:
-;   mov x25, x0
+;   mov x24, x0
 ;   elf_tls_get_addr x0, userextname0
-;   mov x7, x25
 ;   mov x1, x0
-;   mov x0, x7
+;   mov x0, x24
 ;   ldp d8, d9, [sp], #16
 ;   ldp d10, d11, [sp], #16
 ;   ldp d12, d13, [sp], #16
 ;   ldp d14, d15, [sp], #16
-;   ldr x25, [sp], #16
+;   ldr x24, [sp], #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif

@@ -9,8 +9,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   movz x3, #127
-;   adds w0, w0, w3
+;   movz x2, #127
+;   adds w0, w0, w2
 ;   b.lo 8 ; udf
 ;   ret
 
@@ -22,8 +22,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   movz x3, #127
-;   adds w0, w3, w0
+;   movz x2, #127
+;   adds w0, w2, w0
 ;   b.lo 8 ; udf
 ;   ret
 
@@ -46,8 +46,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz x3, #127
-;   adds x0, x0, x3
+;   movz x2, #127
+;   adds x0, x0, x2
 ;   b.lo 8 ; udf
 ;   ret
 
@@ -59,8 +59,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz x3, #127
-;   adds x0, x3, x0
+;   movz x2, #127
+;   adds x0, x2, x0
 ;   b.lo 8 ; udf
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/vhigh_bits.clif

@@ -8,17 +8,17 @@ block0(v0: i8x16):
 }
 
 ; block0:
-;   sshr v3.16b, v0.16b, #7
-;   movz x6, #513
-;   movk x6, x6, #2052, LSL #16
-;   movk x6, x6, #8208, LSL #32
-;   movk x6, x6, #32832, LSL #48
-;   dup v17.2d, x6
-;   and v20.16b, v3.16b, v17.16b
-;   ext v22.16b, v20.16b, v20.16b, #8
-;   zip1 v24.16b, v20.16b, v22.16b
-;   addv h26, v24.8h
-;   umov w0, v26.h[0]
+;   sshr v2.16b, v0.16b, #7
+;   movz x5, #513
+;   movk x5, x5, #2052, LSL #16
+;   movk x5, x5, #8208, LSL #32
+;   movk x5, x5, #32832, LSL #48
+;   dup v16.2d, x5
+;   and v19.16b, v2.16b, v16.16b
+;   ext v21.16b, v19.16b, v19.16b, #8
+;   zip1 v23.16b, v19.16b, v21.16b
+;   addv h25, v23.8h
+;   umov w0, v25.h[0]
 ;   ret
 
 function %f2(i8x16) -> i16 {
@@ -28,17 +28,17 @@ block0(v0: i8x16):
 }
 
 ; block0:
-;   sshr v3.16b, v0.16b, #7
-;   movz x6, #513
-;   movk x6, x6, #2052, LSL #16
-;   movk x6, x6, #8208, LSL #32
-;   movk x6, x6, #32832, LSL #48
-;   dup v17.2d, x6
-;   and v20.16b, v3.16b, v17.16b
-;   ext v22.16b, v20.16b, v20.16b, #8
-;   zip1 v24.16b, v20.16b, v22.16b
-;   addv h26, v24.8h
-;   umov w0, v26.h[0]
+;   sshr v2.16b, v0.16b, #7
+;   movz x5, #513
+;   movk x5, x5, #2052, LSL #16
+;   movk x5, x5, #8208, LSL #32
+;   movk x5, x5, #32832, LSL #48
+;   dup v16.2d, x5
+;   and v19.16b, v2.16b, v16.16b
+;   ext v21.16b, v19.16b, v19.16b, #8
+;   zip1 v23.16b, v19.16b, v21.16b
+;   addv h25, v23.8h
+;   umov w0, v25.h[0]
 ;   ret
 
 function %f3(i16x8) -> i8 {
@@ -48,11 +48,11 @@ block0(v0: i16x8):
 }
 
 ; block0:
-;   sshr v3.8h, v0.8h, #15
-;   ldr q5, pc+8 ; b 20 ; data.f128 0x00800040002000100008000400020001
-;   and v7.16b, v3.16b, v5.16b
-;   addv h17, v7.8h
-;   umov w0, v17.h[0]
+;   sshr v2.8h, v0.8h, #15
+;   ldr q4, pc+8 ; b 20 ; data.f128 0x00800040002000100008000400020001
+;   and v6.16b, v2.16b, v4.16b
+;   addv h16, v6.8h
+;   umov w0, v16.h[0]
 ;   ret
 
 function %f4(i32x4) -> i8 {
@@ -62,11 +62,11 @@ block0(v0: i32x4):
 }
 
 ; block0:
-;   sshr v3.4s, v0.4s, #31
-;   ldr q5, pc+8 ; b 20 ; data.f128 0x00000008000000040000000200000001
-;   and v7.16b, v3.16b, v5.16b
-;   addv s17, v7.4s
-;   mov w0, v17.s[0]
+;   sshr v2.4s, v0.4s, #31
+;   ldr q4, pc+8 ; b 20 ; data.f128 0x00000008000000040000000200000001
+;   and v6.16b, v2.16b, v4.16b
+;   addv s16, v6.4s
+;   mov w0, v16.s[0]
 ;   ret
 
 function %f5(i64x2) -> i8 {
@@ -76,10 +76,10 @@ block0(v0: i64x2):
 }
 
 ; block0:
-;   mov x3, v0.d[1]
-;   mov x5, v0.d[0]
-;   lsr x7, x3, #63
-;   lsr x9, x5, #63
-;   add x0, x9, x7, LSL 1
+;   mov x2, v0.d[1]
+;   mov x4, v0.d[0]
+;   lsr x6, x2, #63
+;   lsr x8, x4, #63
+;   add x0, x8, x6, LSL 1
 ;   ret