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Move %rsp to %rbp, not the reverse.

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This also takes away %rsp and %rbp from regalloc again. This may cause
tests to fail temporarily.
This commit is contained in:
Tyler McMullen
2017-11-29 03:16:37 -08:00
committed by Jakob Stoklund Olesen
parent e0c8ab49e1
commit b049916d35
2 changed files with 3 additions and 3 deletions
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4
lib/cretonne/src/isa/intel/abi.rs
View File

@@ -140,8 +140,8 @@ pub fn allocatable_registers(
flags: &shared_settings::Flags,
) -> AllocatableSet {
let mut regs = AllocatableSet::new();
//regs.take(GPR, RU::rsp as RegUnit);
//regs.take(GPR, RU::rbp as RegUnit);
regs.take(GPR, RU::rsp as RegUnit);
regs.take(GPR, RU::rbp as RegUnit);
// 32-bit arch only has 8 registers.
if !flags.is_64bit() {

2
lib/cretonne/src/isa/intel/mod.rs
View File

@@ -159,8 +159,8 @@ impl TargetIsa for Isa {
let mut pos = EncCursor::new(func, self).at_first_insertion_point(entry_ebb);
pos.ins().x86_push(fp);
pos.ins().copy_special(
RU::rbp as RegUnit,
RU::rsp as RegUnit,
RU::rbp as RegUnit,
);
if local_stack_size > 0 {
pos.ins().adjust_sp_imm(-(local_stack_size as i32));