diff --git a/lib/cretonne/src/isa/intel/abi.rs b/lib/cretonne/src/isa/intel/abi.rs
index 0c45a0e223..e8be53e848 100644
--- a/lib/cretonne/src/isa/intel/abi.rs
+++ b/lib/cretonne/src/isa/intel/abi.rs
@@ -140,8 +140,8 @@ pub fn allocatable_registers(
     flags: &shared_settings::Flags,
 ) -> AllocatableSet {
     let mut regs = AllocatableSet::new();
-    //regs.take(GPR, RU::rsp as RegUnit);
-    //regs.take(GPR, RU::rbp as RegUnit);
+    regs.take(GPR, RU::rsp as RegUnit);
+    regs.take(GPR, RU::rbp as RegUnit);
 
     // 32-bit arch only has 8 registers.
     if !flags.is_64bit() {
diff --git a/lib/cretonne/src/isa/intel/mod.rs b/lib/cretonne/src/isa/intel/mod.rs
index cfca41083a..662faddba1 100644
--- a/lib/cretonne/src/isa/intel/mod.rs
+++ b/lib/cretonne/src/isa/intel/mod.rs
@@ -159,8 +159,8 @@ impl TargetIsa for Isa {
             let mut pos = EncCursor::new(func, self).at_first_insertion_point(entry_ebb);
             pos.ins().x86_push(fp);
             pos.ins().copy_special(
-                RU::rbp as RegUnit,
                 RU::rsp as RegUnit,
+                RU::rbp as RegUnit,
             );
             if local_stack_size > 0 {
                 pos.ins().adjust_sp_imm(-(local_stack_size as i32));