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Add 32-bit ops to RV64.

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The 32-bit arithmetic instructions are encoded differently in the RISC-V 64-bit
mode.
This commit is contained in:
Jakob Stoklund Olesen
2016-08-26 16:13:22 -07:00
parent 176427e220
commit 8a1f87d32e
1 changed files with 3 additions and 0 deletions
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3
meta/isa/riscv/encodings.py
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@@ -22,6 +22,9 @@ for inst, inst_imm, f3, f7 in [
RV32.enc(inst_imm.i32, I, OPIMM(f3))
RV64.enc(inst_imm.i64, I, OPIMM(f3))
# 32-bit ops in RV64.
RV64.enc(base.iadd.i32, R, OP32(0b000, 0b0000000))
RV64.enc(base.isub.i32, R, OP32(0b000, 0b0100000))
# There are no andiw/oriw/xoriw variations.
RV64.enc(base.iadd_imm.i32, I, OPIMM32(0b000))