From 8a1f87d32e27e189e339d79720f03ee4ed479ddb Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Fri, 26 Aug 2016 16:13:22 -0700
Subject: [PATCH] Add 32-bit ops to RV64.

The 32-bit arithmetic instructions are encoded differently in the RISC-V 64-bit
mode.
---
 meta/isa/riscv/encodings.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/meta/isa/riscv/encodings.py b/meta/isa/riscv/encodings.py
index 099b6b5630..c339859730 100644
--- a/meta/isa/riscv/encodings.py
+++ b/meta/isa/riscv/encodings.py
@@ -22,6 +22,9 @@ for inst,           inst_imm,      f3,    f7 in [
         RV32.enc(inst_imm.i32, I, OPIMM(f3))
         RV64.enc(inst_imm.i64, I, OPIMM(f3))
 
+# 32-bit ops in RV64.
+RV64.enc(base.iadd.i32, R, OP32(0b000, 0b0000000))
+RV64.enc(base.isub.i32, R, OP32(0b000, 0b0100000))
 # There are no andiw/oriw/xoriw variations.
 RV64.enc(base.iadd_imm.i32, I, OPIMM32(0b000))