[machinst x64]: assert lane is correct size for extractlane

This change applies a good suggestion @bjorn3 made in #2230 that I forgot to implement there.

cranelift/codegen/src/isa/x64/lower.rs

@@ -2817,6 +2817,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             } else {
                 unreachable!();
             };
+            debug_assert!(lane < src_ty.lane_count() as u8);
 
             if !ty.is_float() {
                 let (sse_op, w_bit) = match ty.lane_bits() {