From 715be68101504d2c737617a7be98042bda56735a Mon Sep 17 00:00:00 2001
From: Andrew Brown <andrew.brown@intel.com>
Date: Tue, 29 Sep 2020 08:56:40 -0700
Subject: [PATCH] [machinst x64]: assert lane is correct size for extractlane

This change applies a good suggestion @bjorn3 made in #2230 that I forgot to implement there.
---
 cranelift/codegen/src/isa/x64/lower.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index e4093c1939..4b5108195a 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -2817,6 +2817,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             } else {
                 unreachable!();
             };
+            debug_assert!(lane < src_ty.lane_count() as u8);
 
             if !ty.is_float() {
                 let (sse_op, w_bit) = match ty.lane_bits() {