diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index e4093c1939..4b5108195a 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -2817,6 +2817,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             } else {
                 unreachable!();
             };
+            debug_assert!(lane < src_ty.lane_count() as u8);
 
             if !ty.is_float() {
                 let (sse_op, w_bit) = match ty.lane_bits() {