Add a RISC-V target.

Flesh out the directory structure for defining target instruction set
architectures. Use RISC-V as a startgin point because it is so simple.

meta/target/__init__.py

@@ -0,0 +1,16 @@
+"""
+Cretonne target definitions
+---------------------------
+
+The :py:mod:`target` package contains sub-packages for each target instruction
+set architecture supported by Cretonne.
+"""
+
+from . import riscv
+
+def all_targets():
+    """
+    Get a list of all the supported targets. Each target is represented as a
+    :py:class:`cretonne.Target` instance.
+    """
+    return [riscv.target]

meta/target/riscv/__init__.py

@@ -0,0 +1,30 @@
+"""
+RISC-V Target
+-------------
+
+`RISC-V <http://riscv.org/>`_ is an open instruction set architecture originally
+developed at UC Berkeley. It is a RISC-style ISA with either a 32-bit (RV32I) or
+64-bit (RV32I) base instruction set and a number of optional extensions:
+
+RV32M / RV64M
+    Integer multiplication and division.
+
+RV32A / RV64A
+    Atomics.
+
+RV32F / RV64F
+    Single-precision IEEE floating point.
+
+RV32D / RV64D
+    Double-precision IEEE floating point.
+
+RV32G / RV64G
+    General purpose instruction sets. This represents the union of the I, M, A,
+    F, and D instruction sets listed above.
+
+"""
+
+from cretonne import Target
+import cretonne.base
+
+target = Target('riscv', [cretonne.base.instructions])