From 6e2e7bfb736f6ba144519a2c75608be7253ce580 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Wed, 6 Apr 2016 11:32:43 -0700
Subject: [PATCH] Add a RISC-V target.

Flesh out the directory structure for defining target instruction set
architectures. Use RISC-V as a startgin point because it is so simple.
---
 cranelift/.gitignore          |  2 --
 cranelift/docs/metaref.rst    | 18 +++++++++++++++++-
 cranelift/src/.gitignore      |  2 ++
 meta/cretonne/__init__.py     | 18 ++++++++++++++++++
 meta/target/__init__.py       | 16 ++++++++++++++++
 meta/target/riscv/__init__.py | 30 ++++++++++++++++++++++++++++++
 6 files changed, 83 insertions(+), 3 deletions(-)
 create mode 100644 cranelift/src/.gitignore
 create mode 100644 meta/target/__init__.py
 create mode 100644 meta/target/riscv/__init__.py

diff --git a/cranelift/.gitignore b/cranelift/.gitignore
index 25eadf4e60..0d20b6487c 100644
--- a/cranelift/.gitignore
+++ b/cranelift/.gitignore
@@ -1,3 +1 @@
 *.pyc
-Cargo.lock
-target
diff --git a/cranelift/docs/metaref.rst b/cranelift/docs/metaref.rst
index e9b7c9a6ec..c8f8b0e265 100644
--- a/cranelift/docs/metaref.rst
+++ b/cranelift/docs/metaref.rst
@@ -11,7 +11,7 @@ domain specific language embedded in Python.
 An instruction set is described by a Python module under the :file:`meta`
 directory that has a global variable called ``instructions``. The basic
 Cretonne instruction set described in :doc:`langref` is defined by the Python
-module :mod:`cretonne.instrs`.
+module :mod:`cretonne.base`.
 
 .. module:: cretonne
 
@@ -74,3 +74,19 @@ class.
 .. autoclass:: Instruction
 .. autoclass:: InstructionGroup
     :members:
+
+Targets
+=======
+
+Cretonne can be compiled with support for multiple target instruction set
+architectures. Each ISA is represented by a :py:class`cretonne.Target` instance.
+
+.. autoclass:: Target
+
+The definitions for each supported target live in a package under
+:file:`meta/target`.
+
+.. automodule:: target
+    :members:
+
+.. automodule:: target.riscv
diff --git a/cranelift/src/.gitignore b/cranelift/src/.gitignore
new file mode 100644
index 0000000000..a9d37c560c
--- /dev/null
+++ b/cranelift/src/.gitignore
@@ -0,0 +1,2 @@
+target
+Cargo.lock
diff --git a/meta/cretonne/__init__.py b/meta/cretonne/__init__.py
index ff03ed198c..d69d5c35c4 100644
--- a/meta/cretonne/__init__.py
+++ b/meta/cretonne/__init__.py
@@ -267,3 +267,21 @@ class Instruction(object):
         for op in x:
             assert isinstance(op, Operand)
         return x
+
+#
+# Defining targets
+#
+class Target(object):
+    """
+    A target instruction set architecture.
+
+    The `Target` class collects everything known about a target ISA.
+
+    :param name: Short mnemonic name for the ISA.
+    :param instruction_groups: List of `InstructionGroup` instances that are
+        relevant for this ISA.
+    """
+
+    def __init__(self, name, instrution_groups):
+        self.name = name
+        self.instruction_groups = instrution_groups
diff --git a/meta/target/__init__.py b/meta/target/__init__.py
new file mode 100644
index 0000000000..bed730b207
--- /dev/null
+++ b/meta/target/__init__.py
@@ -0,0 +1,16 @@
+"""
+Cretonne target definitions
+---------------------------
+
+The :py:mod:`target` package contains sub-packages for each target instruction
+set architecture supported by Cretonne.
+"""
+
+from . import riscv
+
+def all_targets():
+    """
+    Get a list of all the supported targets. Each target is represented as a
+    :py:class:`cretonne.Target` instance.
+    """
+    return [riscv.target]
diff --git a/meta/target/riscv/__init__.py b/meta/target/riscv/__init__.py
new file mode 100644
index 0000000000..e9b9926e31
--- /dev/null
+++ b/meta/target/riscv/__init__.py
@@ -0,0 +1,30 @@
+"""
+RISC-V Target
+-------------
+
+`RISC-V <http://riscv.org/>`_ is an open instruction set architecture originally
+developed at UC Berkeley. It is a RISC-style ISA with either a 32-bit (RV32I) or
+64-bit (RV32I) base instruction set and a number of optional extensions:
+
+RV32M / RV64M
+    Integer multiplication and division.
+
+RV32A / RV64A
+    Atomics.
+
+RV32F / RV64F
+    Single-precision IEEE floating point.
+
+RV32D / RV64D
+    Double-precision IEEE floating point.
+
+RV32G / RV64G
+    General purpose instruction sets. This represents the union of the I, M, A,
+    F, and D instruction sets listed above.
+
+"""
+
+from cretonne import Target
+import cretonne.base
+
+target = Target('riscv', [cretonne.base.instructions])