6e2e7bfb73
Flesh out the directory structure for defining target instruction set architectures. Use RISC-V as a startgin point because it is so simple.
31 lines
716 B
Python
31 lines
716 B
Python
"""
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RISC-V Target
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-------------
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`RISC-V <http://riscv.org/>`_ is an open instruction set architecture originally
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developed at UC Berkeley. It is a RISC-style ISA with either a 32-bit (RV32I) or
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64-bit (RV32I) base instruction set and a number of optional extensions:
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RV32M / RV64M
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Integer multiplication and division.
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RV32A / RV64A
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Atomics.
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RV32F / RV64F
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Single-precision IEEE floating point.
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RV32D / RV64D
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Double-precision IEEE floating point.
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RV32G / RV64G
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General purpose instruction sets. This represents the union of the I, M, A,
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F, and D instruction sets listed above.
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"""
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from cretonne import Target
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import cretonne.base
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target = Target('riscv', [cretonne.base.instructions])
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