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arm64: Implement Vselect opcode

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This is implemented the same as Bitselect, as the controlling vector
is a boolean vector. A boolean vector in cranelift has elements
that are either 0 or all 1s, so it can be used to select elements
lane wise.

Copyright (c) 2020, Arm Limited.
This commit is contained in:
Joey Gouly
2020-07-22 12:50:29 +01:00
parent 399ee0a54c
commit 5355c3e3d5
1 changed files with 2 additions and 2 deletions
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4
cranelift/codegen/src/isa/aarch64/lower_inst.rs
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@@ -1152,9 +1152,10 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
} }
} }
Opcode::Bitselect => { Opcode::Bitselect | Opcode::Vselect => {
let ty = ty.unwrap(); let ty = ty.unwrap();
if ty_bits(ty) < 128 { if ty_bits(ty) < 128 {
debug_assert_ne!(Opcode::Vselect, op);
let tmp = ctx.alloc_tmp(RegClass::I64, I64); let tmp = ctx.alloc_tmp(RegClass::I64, I64);
let rd = get_output_reg(ctx, outputs[0]); let rd = get_output_reg(ctx, outputs[0]);
let rcond = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None); let rcond = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
@@ -1664,7 +1665,6 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
Opcode::Shuffle Opcode::Shuffle
| Opcode::Vsplit | Opcode::Vsplit
| Opcode::Vconcat | Opcode::Vconcat
| Opcode::Vselect
| Opcode::Insertlane | Opcode::Insertlane
| Opcode::ScalarToVector | Opcode::ScalarToVector
| Opcode::Swizzle | Opcode::Swizzle