diff --git a/cranelift/codegen/src/isa/aarch64/lower_inst.rs b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
index 9dec7f9c7f..a14928db5d 100644
--- a/cranelift/codegen/src/isa/aarch64/lower_inst.rs
+++ b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
@@ -1152,9 +1152,10 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             }
         }
 
-        Opcode::Bitselect => {
+        Opcode::Bitselect | Opcode::Vselect => {
             let ty = ty.unwrap();
             if ty_bits(ty) < 128 {
+                debug_assert_ne!(Opcode::Vselect, op);
                 let tmp = ctx.alloc_tmp(RegClass::I64, I64);
                 let rd = get_output_reg(ctx, outputs[0]);
                 let rcond = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
@@ -1664,7 +1665,6 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
         Opcode::Shuffle
         | Opcode::Vsplit
         | Opcode::Vconcat
-        | Opcode::Vselect
         | Opcode::Insertlane
         | Opcode::ScalarToVector
         | Opcode::Swizzle