From 5355c3e3d52e506d83724fa10ead7dd9213f83b3 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Wed, 22 Jul 2020 12:50:29 +0100 Subject: [PATCH] arm64: Implement Vselect opcode This is implemented the same as Bitselect, as the controlling vector is a boolean vector. A boolean vector in cranelift has elements that are either 0 or all 1s, so it can be used to select elements lane wise. Copyright (c) 2020, Arm Limited. --- cranelift/codegen/src/isa/aarch64/lower_inst.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/lower_inst.rs b/cranelift/codegen/src/isa/aarch64/lower_inst.rs index 9dec7f9c7f..a14928db5d 100644 --- a/cranelift/codegen/src/isa/aarch64/lower_inst.rs +++ b/cranelift/codegen/src/isa/aarch64/lower_inst.rs @@ -1152,9 +1152,10 @@ pub(crate) fn lower_insn_to_regs>( } } - Opcode::Bitselect => { + Opcode::Bitselect | Opcode::Vselect => { let ty = ty.unwrap(); if ty_bits(ty) < 128 { + debug_assert_ne!(Opcode::Vselect, op); let tmp = ctx.alloc_tmp(RegClass::I64, I64); let rd = get_output_reg(ctx, outputs[0]); let rcond = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None); @@ -1664,7 +1665,6 @@ pub(crate) fn lower_insn_to_regs>( Opcode::Shuffle | Opcode::Vsplit | Opcode::Vconcat - | Opcode::Vselect | Opcode::Insertlane | Opcode::ScalarToVector | Opcode::Swizzle