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4185d7b2d6044273d728e7230c56b2d8c8fda4bd
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Author SHA1 Message Date
Alexis Engelke
4185d7b2d6 encode: Support FD/TD encodings 2021-04-02 11:26:12 +02:00
Alexis Engelke
fa52782e76 encode: Enforce 15-byte limit 2021-04-02 11:00:24 +02:00
Alexis Engelke
d9183228d0 encode: Actually encode LOCK prefix 2021-04-02 10:59:06 +02:00
Alexis Engelke
2d9587bc16 encode: Fix encoding of memory operand 
When a modrm_idx is used without a ModRM being present, the encoder
attempted to encode memory operands using O/OA/AO encodings.
 2021-04-02 10:54:04 +02:00
Alexis Engelke
51ffe2598e ci: Fix GitHub CI 2021-03-28 15:17:35 +02:00
Alexis Engelke
cf8d1be15f encode: Fix erroneous encoding of SREG push/pop 2021-03-23 13:25:30 +01:00
Alexis Engelke
5faa90a292 encode: Support RVMR encoding 2021-03-23 12:55:43 +01:00
Alexis Engelke
0521ff7d42 decode: Fix VBLENDVP[SD] opcodes 2021-03-23 12:52:37 +01:00
Alexis Engelke
b5994b2f2d ci: Add build description for builds.sr.ht 2021-02-06 12:44:24 +01:00
Alexis Engelke
4f2366afd1 instrs: Add VIA PadLock and AMD RDPRU 2021-01-23 16:47:30 +01:00
Alexis Engelke
f7567c89bd instrs: Fix VMOVSS/VMOVSD with memory operand 2021-01-23 16:44:16 +01:00
Alexis Engelke
e8f440c713 instrs: Minor fix with mandatory prefixes 2021-01-23 16:43:52 +01:00
Alexis Engelke
d7b9c97681 instrs: Remove MPX instructions 
These instructions have plenty of corner cases and some instructions
have a different usage of the memory operand. Given that MPX is already
deprecated by Intel, it seems that the better option is to decode these
(rarely occuring) instructions as NOPs.
 2021-01-23 16:18:12 +01:00
Alexis Engelke
0efd44cc28 instrs: Add some missing opcodes and FPU aliases 2021-01-23 16:17:42 +01:00
Alexis Engelke
103fc536b0 instrs: Fix operands of VRCPPS/VSQRTP[SD]/VRSQRTPS 2021-01-23 14:39:48 +01:00
Alexis Engelke
f17d84cee6 format: Emit XACQUIRE/XRELEASE 
As CMPXCHGD has a mandatory prefix table, it is absolutely necessary
that the presence of any tables does not modify any decoding state.
 2021-01-23 14:35:08 +01:00
Alexis Engelke
ab63a3c921 instrs: Fix mandatory prefixes of CMPXCHG8B/16B 2021-01-23 14:30:45 +01:00
Alexis Engelke
7919b8115a format: Emit REP/REPNZ only for string instruction 2021-01-23 14:29:29 +01:00
Alexis Engelke
fe68dbb743 decode: Fix LOCK handling for MOV CR/DR 2021-01-23 14:28:27 +01:00
Alexis Engelke
95371637ea format: Add names for bound registers 2021-01-23 14:05:42 +01:00
Alexis Engelke
363698db3b parseinstrs: Move decode table gen to new function 2021-01-23 13:59:59 +01:00
Alexis Engelke
85fdaa3a9b instrs: Remove incorrect NFx specifiers 
The new trie implementation is more flexible and allows omitting
prefixes even with a ModRM specifier in the opcode. Use this flexibility
to simplify instruction descriptions.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
dc399390a4 parseinstrs: Refactor mapping of opcode to Trie 2021-01-23 13:25:23 +01:00
Alexis Engelke
13a2456458 parseinstrs: Simplify trie implementation 2021-01-23 13:25:23 +01:00
Alexis Engelke
43910a6227 parseinstrs: Avoid redundant encoding of InstrDesc 2021-01-23 13:25:23 +01:00
Alexis Engelke
09d3886577 parseinstrs: Move regtype encoding to InstrDesc 2021-01-23 13:25:23 +01:00
Alexis Engelke
d6278de812 parseinstrs: Use tuples/ints for indexing in trie 
This avoids useless internal string formatting.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
1390bae341 parseinstr: Create optype string in descriptor 
The raw encoding representation is now only used in InstrDesc.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
801fe4bc43 parseinstrs: Generalize immediate size computation 2021-01-23 13:25:23 +01:00
Alexis Engelke
62018556a1 parseinstrs: Simplify operand kind parsing 2021-01-23 13:25:23 +01:00
Alexis Engelke
bd611902b0 parseinstrs: Add separate ModRM indicator to desc 
Some instructions have no ModRM operand and no extended opcode but still
consume a ModRM byte.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
8561d77c91 format: Minor non-functional changes 2021-01-10 18:55:05 +01:00
Alexis Engelke
cb90c2c54d instr: Add weak NOP for PREFETCH register encoding 2021-01-10 18:54:18 +01:00
Alexis Engelke
9d7b584121 decode: Verify 3DNow! opcode validity 2021-01-10 18:53:32 +01:00
Alexis Engelke
80df5ff47c instrs: Add reserved NOP/PREFETCH as weak opcodes 2021-01-10 16:53:27 +01:00
Alexis Engelke
f1e18c208c instrs: Add AMD-only MOVTNSS/MOVNTSD 2021-01-10 16:49:53 +01:00
Alexis Engelke
1458bf9673 encode: Support VEX-encoded instructions 2021-01-10 16:03:40 +01:00
Alexis Engelke
9245a97248 instrs: Add several AMD-only instructions 
- 3DNow! instructions have a trailing immediate byte which indicates the
  opcode. Decoding this with the existing table structure requires more
  effort (in particular, a new lookup table after decoding ModRM would
  be required). Given that AMD even removed 3DNow! over 10 years ago, it
  appears unlikely that this will ever be fully supported. Adding the
  RMI-encoded pseudo-instruction "3DNOW" just to support that opcode.
- FEMMS is a legacy 3DNow! instruction.
- EXTRQ/INSERTQ are instructions with an "unusual" encoding and
  operation mode. This is another instance of 16-bit immediates.
- SVM (AMD's variant of VMX) and SNP instructions are AMD-only.
 2021-01-10 15:18:44 +01:00
Alexis Engelke
51072cac9c format: Generalize ENTER/JMPF/CALLF op. formatting 2021-01-10 15:15:30 +01:00
Alexis Engelke
c050b34ff9 instrs: Add support for undocumented instructions 
Undocumented instruction are not decoded by default.

- SALC: undocumented in any recent manual and unsupported by newer
  Intel CPUs. Including as listed by [1,2].
- Undocumented FPU instructions: see [2].

[1]: http://www.rcollins.org/secrets/opcodes/SALC.html
[2]: https://github.com/xoreaxeaxeax/sandsifter/issues/33
 2021-01-10 15:04:37 +01:00
Alexis Engelke
b8decc8064 instrs: Add AMD encoding of SHL/6 and TEST/1 
- SHL (SAL) encoding with /6: this is not documented by Intel and
  documented by AMD as present, but unsupported by tools.
- TEST encoding with /1: undocumented by Intel, documented by AMD.
 2021-01-10 15:03:23 +01:00
Alexis Engelke
fcb39f5cbe instrs: Add support for AESKL/AESKLE 2021-01-10 14:15:14 +01:00
Alexis Engelke
862b6d285c instrs: Minor operand size fixes 2021-01-10 14:13:44 +01:00
Alexis Engelke
d40ee6db66 instrs: Add FLD and fix FUCOMIP instructions 2021-01-10 14:08:29 +01:00
Alexis Engelke
c87264ace3 instrs: Add MMX PSHUFW instruction 2021-01-10 14:02:39 +01:00
Alexis Engelke
dd4263b169 instrs: Support far jumps/calls encoded target 2021-01-10 12:31:07 +01:00
Alexis Engelke
2f295e5476 instrs: Exact register size for scalar VEX ops 2021-01-10 12:15:49 +01:00
Alexis Engelke
96e513c8ea breaking! instrs: Decode VMOVS[SD] loads correctly 
These instruction ignore the VEX operand if the source operand is a
memory location.

API compatibility: separate handling for different operand types in the
second and third operand (REG+REG vs. MEM+NONE) is needed.
 2021-01-10 12:12:26 +01:00
Alexis Engelke
e86ea540b5 instrs: Fixup register decoding for PEXTR* 2021-01-10 12:11:27 +01:00
Alexis Engelke
a81582cc3a breaking! instrs: Decode MOVLHPS/MOVHLPS 
Now that we support different /r and /m encodings on the same opcode, we
can easily identify MOVLHPS/MOVHLPS as different instructions.

API compatibility: existing code can point the new MOVLHPS/MOVHLPS
mnemonics to the existing handler for MOVHPS/MOVLPS.
 2021-01-10 12:11:27 +01:00