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6b1a5e8b1b20abcecfb388ca1aede31b599770f2
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57 Commits

Author SHA1 Message Date
Amanieu d'Antras
6b1a5e8b1b Address review feedback 2022-01-11 22:27:15 +00:00
Amanieu d'Antras
ee4de54240 Guard trace! behind cfg!(debug_assertions) 
Even if the trace log level is disabled, the presence of the trace!
macro still has a significant impact on performance because it is
present in the inner loops of the allocator.

Removing the trace! calls at compile-time reduces instruction count by
~7%.
 2022-01-11 13:30:13 +00:00
Amanieu d'Antras
693fb6a975 Only emit DefAlloc edits when the "checker" feature is enabled. 
This reduces instruction counts by ~2% when disabled.
 2022-01-11 13:03:24 +00:00
Amanieu d'Antras
74928b83fa Replace all assert! with debug_assert! 
This results in a ~6% reduction in instruction count.
 2022-01-11 03:54:08 +00:00
Amanieu d'Antras
8ab44c383e Add a helper to iterate over insts and edits of a block in order 2021-12-27 22:08:36 +01:00
Amanieu d'Antras
51493ab03a Apply review feedback 2021-12-12 00:33:30 +00:00
Amanieu d'Antras
38ffc479c2 Simplify the internal representation of PReg 2021-12-11 22:39:19 +00:00
Amanieu d'Antras
8f435243e0 Properly handle fixed stack slots during multi-fixed-reg fixup 2021-12-11 22:39:14 +00:00
Amanieu d'Antras
77e6a9e0d7 Add support for fixed stack slots 
This works by allowing a PReg to be marked as being a stack location
instead of a physical register.
 2021-12-11 22:31:58 +00:00
Amanieu d'Antras
0cb3a8019f Rework the API for outgoing blockparams 2021-12-01 01:43:20 +00:00
Amanieu d'Antras
a516e6d6f3 Return safepoint_slots as Allocations instead of SpillSlots 
This enables us to support reftype vregs in register locations in the
future.
 2021-11-16 00:47:43 +00:00
Amanieu d'Antras
358c831b31 Remove regs from MachineEnv 
It isn't exactly clear what purpose it serves.
 2021-09-19 16:40:27 +01:00
Amanieu d'Antras
af527aca88 Fix PReg indexing with >32 pregs 2021-09-19 16:39:56 +01:00
Amanieu d'Antras
9e2ab3d5f7 Address review feedback 2021-09-14 13:12:52 +01:00
Amanieu d'Antras
35ed2109b1 Adjust Operand encoding 
The encoding for OperandConstraint is adjusted to free up 2 bits which
allows for 2^21 vregs and 2^6 pregs.
 2021-09-13 08:33:17 +01:00
Amanieu d'Antras
a243c4e575 Remove Function::is_call 
The documentation says that this is only used for heuristics, but it
is never actually called. This should be removed for now and perhaps
added back later if we find an actual use for it.
 2021-09-09 11:16:11 +01:00
Chris Fallin
6f0893d69d Address review comments. 2021-08-31 17:56:06 -07:00
Chris Fallin
6389071e09 Address review comments. 2021-08-31 17:42:50 -07:00
Chris Fallin
b19fa4857f Rename operand positions to Early and Late, and make weights f16/f32 values. 2021-08-31 17:31:23 -07:00
Chris Fallin
3a18564e98 Addressed more review comments. 2021-08-30 17:51:55 -07:00
Chris Fallin
6d313f2b56 Address review comments: more doc comments and some minor refactorings. 2021-08-30 17:15:37 -07:00
Chris Fallin
ffc06b2099 Debug output for Operands: omit default/most common positions. 2021-08-12 14:49:42 -07:00
Chris Fallin
c071e44fc0 Derive PartialOrd/Ord/Hash for Operand. 2021-08-12 14:43:13 -07:00
Chris Fallin
7652b4b109 Review feedback. 2021-08-12 14:27:20 -07:00
Chris Fallin
2f856435f4 Review feedback. 2021-08-12 14:08:10 -07:00
Chris Fallin
3e1e0f39b6 Convert all log::debug to log::trace. 2021-08-12 12:05:19 -07:00
Chris Fallin
84285c26fb Rename OperandPolicy to OperandConstraint as per feedback from @julian-seward1. 2021-08-12 11:17:52 -07:00
Chris Fallin
245c212289 Revert "Add fixed-non-allocatable operand support." 
This feature needs more thought; for now we will of course continue to
support pinned vregs, but perhaps we can do better for
"pass-through-and-forget" operands that are given non-allocatable
registers.

This reverts commit 736f636c36.
 2021-06-20 23:03:44 -07:00
Chris Fallin
22eed0a6ae Make bitvec public; it is used by regalloc.rs shim too. 2021-06-19 12:47:02 -07:00
Chris Fallin
736f636c36 Add fixed-non-allocatable operand support. 2021-06-19 12:17:18 -07:00
Chris Fallin
50eb6fc42f Keep internal modules private, but re-export under fuzzing feature flag 2021-06-19 12:08:37 -07:00
Chris Fallin
36975b8b6f Add doc-comment note on Edit that stack-to-stack moves are never generated. 2021-06-19 11:34:05 -07:00
Chris Fallin
6ec6207717 Add design document. 2021-06-18 13:59:12 -07:00
Chris Fallin
1bd1248cb5 Avoid stack-to-stack moves by allocating an extra spillslot and re-using the scratch reg instead. 2021-06-10 22:36:02 -07:00
Chris Fallin
c6bcd3c941 WIP: redundant-move elimination. 2021-06-07 21:15:32 -07:00
Chris Fallin
2a5f571b80 WIP: Handle moves between realregs (pregs) and vregs somewhat specially, by converting into operand constraints 
Still has a fuzzbug in interaction between R->R and V->R moves. Will
likely rework to make pinned-vreg handling more general but want to save
a checkpoint here; idea for rework:
- set allocs immediately if an Operand is a pinned vreg;
- reserve preg ranges;
- then, in rest of liveness computation / LR construction, convert
  pinned-vregs to operands with constraints, but otherwise do not
  special-case as we do in this commit.
 2021-05-20 19:53:19 -07:00
Chris Fallin
f1c6dfe807 Optionally show annotations in final allocation/program dump based on RegallocOptions flag 2021-05-19 16:36:36 -07:00
Chris Fallin
e1f67e860f Pinned VRegs for use with regalloc.rs shim to support RealRegs. 2021-05-18 22:40:43 -07:00
Chris Fallin
f0fbf3aa0c Rework data structures: bundles have a SmallVec of ranges, and ranges a SmallVec of uses. 
Appears to be a small speed improvement on the highly-artificial
fuzz-generator test inputs; Cranelift tests TBD.
 2021-05-17 22:44:10 -07:00
Chris Fallin
5b55948feb Check branch-args for conflicts with edge-move placement. 2021-05-13 17:25:11 -07:00
Chris Fallin
1f9258bea5 Detect undefined liveins. 2021-05-12 01:06:27 -07:00
Chris Fallin
37fa3ec763 Improve prog-move handling: no use/def records, just directly connect the LRs. 
Also requires some metadata in edit output to properly hook up the
checker in regalloc.rs to track user-moves without seeing the original
insts with operands.
 2021-05-11 23:59:12 -07:00
Chris Fallin
4f26b1c78f Properly handle prog-moves with fixed srcs or dests 2021-05-09 13:35:38 -07:00
Chris Fallin
b9e89885c4 Error checking: properly signal a crit-edge requirement failure (used for regalloc.rs fuzzer) 2021-05-08 21:48:58 -07:00
Chris Fallin
a6e3128821 Support mod (modify) operands, for better efficiency with regalloc.rs/Cranelift shim. 2021-05-07 19:48:34 -07:00
Chris Fallin
df59b5ede4 Inline all the things (ProgPoint edition) 2021-05-07 17:55:04 -07:00
Chris Fallin
4f6346768e Pinned-VReg mechanism. 2021-05-07 17:45:51 -07:00
Chris Fallin
2ba518517d Fuzzbugfix: actually do need eager liveness computation; must uphold invariant that all earlier-in-postorder blocks have full livein sets. 2021-05-06 23:29:59 -07:00
Chris Fallin
02b6516acd Some memory-size/bitpacking optimizations 2021-05-06 20:47:17 -07:00
Chris Fallin
ab828b6c86 MachineEnv fields are public 2021-05-05 23:14:04 -07:00