T0b1/regalloc2
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  • db8e06d3a8 WIP main Tobias Schwarz 2023-06-21 20:43:36 +02:00
  • 3f379b9d69 WIP T0b1 2023-06-15 02:26:17 +02:00
  • c1f2b0f3a3 WIP T0b1 2023-06-09 00:35:20 +02:00
  • 7a7dc20731 find_free_preg Tobias Schwarz 2023-06-06 19:20:42 +02:00
  • 9f7d6bb3b4 WIP T0b1 2023-05-25 02:30:08 +02:00
  • 6e6e408a05 WIP Tobias Schwarz 2023-05-24 20:00:52 +02:00
  • b6cccb7ecb WIP T0b1 2023-05-23 13:37:23 +02:00
  • 8746af2882 more stuff in regs T0b1 2023-05-05 23:37:09 +02:00
  • 8fb8aa15b0 fixed first reg version T0b1 2023-05-05 02:10:23 +02:00
  • b6cc306d7a first steps to keeping stuff in register T0b1 2023-04-30 23:10:59 +02:00
  • 12e996f7de dont alloc a new stack slot if value dies on edge T0b1 2023-04-30 01:31:52 +02:00
  • ef1e46d8ef first try handly cycles/chains (doesnt work) T0b1 2023-04-28 01:10:49 +02:00
  • a0404ec851 cur changes T0b1 2023-04-18 12:18:44 +02:00
  • a0e2851620 reuse stack slot if variable dies outgoing T0b1 2023-04-16 15:09:54 +02:00
  • d9bbbcfbe2 save some work T0b1 2023-04-16 14:43:18 +02:00
  • f5f984c81a Revert "try using bitmap instead of indexset" T0b1 2023-04-16 14:24:26 +02:00
  • 74873feb96 Revert "try bigger smallvec for vregs" T0b1 2023-04-16 14:24:23 +02:00
  • 75fdc9d3a4 try bigger smallvec for vregs T0b1 2023-04-16 14:10:24 +02:00
  • 84a1e58b97 try using bitmap instead of indexset T0b1 2023-04-16 13:52:37 +02:00
  • 8b724e1796 fix unused Result T0b1 2023-04-16 03:24:32 +02:00
  • 74f8e9a1fd calc live bitmaps T0b1 2023-04-16 03:23:36 +02:00
  • d31dbaaa16 calculate use positions T0b1 2023-04-16 02:03:50 +02:00
  • 9d1dbadd04 fix stackmaps T0b1 2023-04-16 01:17:49 +02:00
  • c4a0d85b72 dont calc cfginfo T0b1 2023-04-15 03:11:32 +02:00
  • dcb95541a7 only do clobber string computation if tracing T0b1 2023-04-14 19:36:21 +02:00
  • 2c8b9a680f change regs_allocated to PRegSet T0b1 2023-04-14 19:33:54 +02:00
  • e2061d2e04 first impl T0b1 2023-04-14 18:18:15 +02:00
  • 993074a974 something T0b1 2023-04-13 03:38:59 +02:00
  • 706c44513e init T0b1 2023-04-12 03:49:50 +02:00
  • f0e9cde328 Use drain instead of clear (#123) Trevor Elliott 2023-04-06 14:21:42 -07:00
  • 9c6d6dc9aa Slightly more efficient vec initialization (#120) Johan Milanov 2023-04-03 22:49:36 +02:00
  • 2bd03256b3 Make regalloc2 #![no_std] (#119) Amanieu d'Antras 2023-03-09 20:25:59 +01:00
  • 7354cfedde Remove support for program moves (#118) Amanieu d'Antras 2023-03-05 01:38:05 +01:00
  • 54f074e507 Re-introduce optional dedicated scratch registers (#117) Amanieu d'Antras 2023-03-04 23:49:10 +01:00
  • 34a9ae7379 Misc refactorings (#116) Trevor Elliott 2023-02-28 10:42:13 -08:00
  • 1e8da4f99b Bump version to 0.6.1. (#115) Chris Fallin 2023-02-15 18:06:40 -08:00
  • 7bb83a3361 checker: Use a couple of Rust idioms (#114) Jamey Sharp 2023-02-15 17:59:20 -08:00
  • c3e513c4cb Fix checker when empty blocks result in unchanged-from-Top entry state. (#113) Chris Fallin 2023-02-15 17:42:51 -08:00
  • 50b9cf8fe2 Bump to version 0.6.0 (#112) Trevor Elliott 2023-02-07 14:57:22 -08:00
  • 376294e828 Fix indent/conditional removal in #108 that removed wrong brace. (#111) Chris Fallin 2023-01-25 13:20:26 -08:00
  • 0edb11d3a7 Remove mod operands. (#109) Chris Fallin 2023-01-24 17:41:46 -08:00
  • e09f6519a6 Remove pinned VRegs. (#108) Chris Fallin 2023-01-24 17:31:41 -08:00
  • e41c6140de Bump to 0.5.1 (#106) Trevor Elliott 2022-12-06 12:51:08 -08:00
  • bc398bd19b SSA Validator Fixes (#105) Trevor Elliott 2022-11-30 16:31:27 -08:00
  • 346b7f38a3 Bump to 0.5.0 (#104) Trevor Elliott 2022-11-29 10:03:24 -08:00
  • 7f0d0b98d0 Expose ssa verification as a regalloc2 option (#102) Trevor Elliott 2022-11-29 09:30:59 -08:00
  • 25b08c6cff Bump the checkout action to v3 to avoid node12 deprecation (#103) Trevor Elliott 2022-11-28 17:55:01 -08:00
  • 51561285d3 Add a From<&MachineEnv> impl for PRegSet (#101) Trevor Elliott 2022-11-09 11:31:56 -08:00
  • b41b1f9a3c Use maximum inline capacity available for SmallVec<VRegIndex> in SpillSet (#100) Nick Fitzgerald 2022-11-02 12:16:22 -07:00
  • eb0a8fd22f Bump to version 0.4.2 (#99) Nick Fitzgerald 2022-11-01 10:30:30 -07:00
  • fdcf7b694f Avoid indexing and use iteration (#98) Nick Fitzgerald 2022-11-01 10:00:09 -07:00
  • b4eedf3f32 Fix the moves fuzz target. (#97) Chris Fallin 2022-10-21 09:08:27 -07:00
  • d6b15095c5 Add explicit dependency on libfuzzer-sys (#96) Alex Crichton 2022-10-21 10:33:50 -05:00
  • eb259e8aba Some small perf improvements (#95) Jamey Sharp 2022-10-11 08:23:02 -07:00
  • 1efaa73943 Modify a SmallVec inline size for UseList to be slightly larger. (#93) Chris Fallin 2022-10-07 13:37:27 -07:00
  • 6394913c1d Add README note that non-SSA support is deprecated. (#94) Chris Fallin 2022-10-05 10:43:15 -07:00
  • 227a9fde91 Cache HashSet in try_to_allocate_bundle_to_reg (#90) Amanieu d'Antras 2022-09-27 00:14:43 +01:00
  • 67f5c167a8 Fix documentation for inst_clobbers (#89) Amanieu d'Antras 2022-09-27 00:14:08 +01:00
  • 061963f469 Version 0.4.1. (#86) Chris Fallin 2022-09-22 15:20:16 -07:00
  • bcfc10c44e Fix fallback-split behavior: trim start of minimal bundle wrt start of original LR. (#85) Chris Fallin 2022-09-22 15:09:49 -07:00
  • 0fb9c03e09 Version 0.4.0. (#84) Chris Fallin 2022-09-20 17:27:38 -07:00
  • b98e8ad517 Version 0.3.3. (#83) Chris Fallin 2022-09-20 16:08:01 -07:00
  • 1b38a71e38 Some fixes to allow for call instructions to name args, returns, and clobbers with constraints. (#74) Chris Fallin 2022-09-20 15:58:20 -07:00
  • 906a053208 Remove register class from SpillSlot (#80) Amanieu d'Antras 2022-09-21 05:05:23 +08:00
  • 3db1b7199b Fix design doc typo (#82) Jeffrey Crocker 2022-09-20 17:04:56 -04:00
  • 520cafa129 Handle fixed stack slots in the move resolver (#78) Amanieu d'Antras 2022-09-20 03:27:24 +08:00
  • 1495c1e342 Add fixed-non-allocatable operand support (#77) Amanieu d'Antras 2022-09-20 03:23:53 +08:00
  • aeef47a06b Make more PReg & VReg methods const (#76) Amanieu d'Antras 2022-09-12 19:03:29 +02:00
  • be47ac39e8 Fuzzing function generator: bound the debug-labels size. (#73) Chris Fallin 2022-08-31 10:10:38 -07:00
  • ad39c66fe7 Fix typo. (#71) Teymour Aldridge 2022-08-05 11:24:36 +08:00
  • 81c11d37d6 Version 0.3.2 (#70) Jamey Sharp 2022-08-03 15:25:45 -07:00
  • 47cb8234b6 Remove old tests and reexport libfuzzer from fuzzing module (#69) Jamey Sharp 2022-08-03 14:28:37 -07:00
  • 1f915bb9b6 validate_ssa: Check def uniqueness first (#68) Jamey Sharp 2022-08-03 10:52:50 -07:00
  • 1955c6dfb5 Only record vreg definitions when fuzzing (#66) Jamey Sharp 2022-07-29 10:25:27 -07:00
  • 0eb3deb384 Version 0.3.1. (#65) Chris Fallin 2022-07-20 10:57:15 -07:00
  • a33b044d6c Streamline log enablement (#64) Benjamin Bouvier 2022-07-20 19:44:31 +02:00
  • 8bede950d0 Release 0.3.0. (#63) Chris Fallin 2022-06-27 14:09:15 -07:00
  • 4eb2a2528b Limit split count per original bundle with fallback 1-to-N split. (#59) Chris Fallin 2022-06-27 13:23:09 -07:00
  • 9733cb2227 Clobbers: use a more efficient bitmask representation in API. (#58) Chris Fallin 2022-06-27 12:27:19 -07:00
  • 06b3baf9f9 Version 0.2.3. (#61) Chris Fallin 2022-06-27 11:37:57 -07:00
  • 68aa61571b Bugfix: no hole in liveranges for pinned vreg move src. (#60) Chris Fallin 2022-06-27 11:21:19 -07:00
  • b78ccbce6e Version 0.2.2. (#57) Chris Fallin 2022-06-03 16:15:54 -07:00
  • 427e041f1c Fix spillslot allocation to actually reuse spillslots. (#56) Chris Fallin 2022-06-03 16:01:10 -07:00
  • 257c5ccc18 Bump version to 0.2.1. (#55) Chris Fallin 2022-05-31 14:33:55 -07:00
  • 52818a7ed6 Handle conflicting Before and After fixed-reg constraints with a copy. (#54) Chris Fallin 2022-05-31 14:01:27 -07:00
  • 0395614545 Bump version to 0.2.0. (#52) Chris Fallin 2022-05-23 11:13:16 -07:00
  • 869c21e79c Remove an explicitly-set-aside scratch register per class. (#51) Chris Fallin 2022-05-23 10:48:37 -07:00
  • 33611a68b9 Bump to version 0.1.3. (#50) Chris Fallin 2022-05-16 22:44:35 -07:00
  • 1379c65a6a Handle conflict-related liverange splits arising from stack constraints without falling back to spill bundle. (#49) Chris Fallin 2022-05-16 22:36:51 -07:00
  • 9b83635980 Bump version to 0.1.2. (#44) Chris Fallin 2022-04-18 13:20:07 -07:00
  • a5c48fda8a Support program moves, including pinned vregs, in the checker. (#43) Chris Fallin 2022-04-18 10:36:26 -07:00
  • f307ed170c Bump version to 0.1.1. (#41) Chris Fallin 2022-04-13 10:37:43 -07:00
  • 4cac1614bf Add serde support for exposed types. (#40) Chris Fallin 2022-04-13 10:14:00 -07:00
  • 94cd6c421c Bump version to 0.1.0 for release. (#39) Chris Fallin 2022-04-04 16:37:01 -07:00
  • 0cb08095e6 Make multiple defs of one vreg possible on one instruction. (#38) Chris Fallin 2022-04-04 16:22:05 -07:00
  • a369150213 Make some improvements to clarity of checker implementation. (#37) Chris Fallin 2022-03-30 11:23:56 -07:00
  • ad41f8a7a5 Record vreg classes explicitly during liverange pass. (#35) Chris Fallin 2022-03-29 14:00:14 -07:00
  • 433e8b3776 Early defs reserve a register for whole instruction. (#32) Chris Fallin 2022-03-18 10:32:49 -07:00
  • 4f1161d9e4 Generalize debug-info support a bit. (#34) Chris Fallin 2022-03-18 10:32:27 -07:00
  • 00dc692489 Allow for reused inputs when the reused vreg is also used as other (normal) uses. (#33) Chris Fallin 2022-03-18 10:14:27 -07:00