Jakob Stoklund Olesen e641c97670 Add RISC-V encodings for brz and brnz. ...

These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.

2017-04-03 15:20:57 -07:00

..

arm32

Add a section about implementation limits.

2017-02-24 11:08:15 -08:00

arm64

Generate register class descriptors.

2017-01-20 14:23:06 -08:00

intel

Generate register class descriptors.

2017-01-20 14:23:06 -08:00

riscv

Add RISC-V encodings for brz and brnz.

2017-04-03 15:20:57 -07:00

__init__.py

Fixed for mypy 0.501.

2017-03-03 09:08:28 -08:00