Jakob Stoklund Olesen dcad3fa339 Fix coloring bug with combined constraints and global values. ...

The Intel instruction "v1 = ushr v2, v2" will implicitly fix the output
register for v2 to %rcx because the output is tied to the first input
operand and the second input operand is fixed to %rcx.

Make sure we handle this transitive constraint when checking for
interference with the globally live registers.

Fixes #218

2018-01-17 15:51:08 -08:00

..

cfg

Convert the CFG traversal tests to file tests.

2017-12-08 13:58:18 -08:00

domtree

Dominator tree pre-order.

2017-12-08 17:43:15 -08:00

isa

Align IntelGOTPCRel4 with R_X86_64_GOTPCREL.

2017-12-15 16:17:32 -06:00

licm

Disallow branching to the entry block.

2017-10-09 15:02:17 -07:00

parser

Add docs and tests for copy_special instruction. Fixes encoding issue that tests revealed.

2017-12-05 11:49:12 -08:00

regalloc

Fix coloring bug with combined constraints and global values.

2018-01-17 15:51:08 -08:00

simple_gvn

Mark spill and fill as can_store and can_load.

2017-10-19 13:11:33 -07:00

verifier

Fix verifier bug in unreachable code.

2018-01-09 10:47:49 -08:00

wasm

Legalize fcvt_to_sint and fcvt_to_uint for Intel64.

2017-09-28 12:00:38 -07:00