Jakob Stoklund Olesen d2ddc700a8 Add the br_icmp instruction. ...

This instruction behaves like icmp fused with brnz, and it can be used
to represent fused compare+branch instruction on Intel when optimizing
for macro-op fusion.

RISC-V provides compare-and-branch instructions directly, and it is
needed there too.

2017-04-03 15:04:42 -07:00

..

branch.cton

Limit type inference for controlling type variables in write.rs

2017-03-22 14:45:38 -07:00

call.cton

Parse signature and function declarations.

2016-10-18 13:19:24 -07:00

instruction_encoding.cton

We now parse and record a ValueLoc for each SSA value result of each instruction. Code currently not passing tests.

2017-03-09 07:19:28 -08:00

keywords.cton

Don't have keywords in the lexer and parser.

2016-09-20 13:00:37 -07:00

rewrite.cton

Wrap FunctionName in a newtype struct.

2016-09-19 15:09:25 -07:00

ternary.cton

Integer subtraction with borrow flags.

2016-09-23 15:47:39 -07:00

tiny.cton

Add the br_icmp instruction.

2017-04-03 15:04:42 -07:00